1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright 2019 NXP
4 * Copyright 2019-2020 Variscite Ltd.
5 * Copyright (C) 2020 Krzysztof Kozlowski <krzk
6 */
7
8 #include "imx8mn.dtsi"
9
10 / {
11 model = "Variscite VAR-SOM-MX8MN modul
12 compatible = "variscite,var-som-mx8mn"
13
14 chosen {
15 stdout-path = &uart4;
16 };
17
18 memory@40000000 {
19 device_type = "memory";
20 reg = <0x0 0x40000000 0 0x4000
21 };
22
23 reg_eth_phy: regulator-eth-phy {
24 compatible = "regulator-fixed"
25 pinctrl-names = "default";
26 pinctrl-0 = <&pinctrl_reg_eth_
27 regulator-name = "eth_phy_pwr"
28 regulator-min-microvolt = <330
29 regulator-max-microvolt = <330
30 regulator-enable-ramp-delay =
31 gpio = <&gpio2 9 GPIO_ACTIVE_H
32 enable-active-high;
33 };
34
35 reg_3v3_fixed: regulator-3v3-fixed {
36 compatible = "regulator-fixed"
37 regulator-name = "fixed_3v3";
38 regulator-min-microvolt = <330
39 regulator-max-microvolt = <330
40 regulator-always-on;
41 };
42 };
43
44 &A53_0 {
45 cpu-supply = <&buck2_reg>;
46 };
47
48 &A53_1 {
49 cpu-supply = <&buck2_reg>;
50 };
51
52 &A53_2 {
53 cpu-supply = <&buck2_reg>;
54 };
55
56 &A53_3 {
57 cpu-supply = <&buck2_reg>;
58 };
59
60 &ecspi1 {
61 pinctrl-names = "default";
62 pinctrl-0 = <&pinctrl_ecspi1>;
63 cs-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>
64 <&gpio1 0 GPIO_ACTIVE_LOW>
65 /delete-property/ dmas;
66 /delete-property/ dma-names;
67 status = "okay";
68
69 /* Resistive touch controller */
70 touchscreen@0 {
71 reg = <0>;
72 compatible = "ti,ads7846";
73 pinctrl-names = "default";
74 pinctrl-0 = <&pinctrl_restouch
75 interrupt-parent = <&gpio1>;
76 interrupts = <3 IRQ_TYPE_EDGE_
77
78 spi-max-frequency = <1500000>;
79 pendown-gpio = <&gpio1 3 GPIO_
80
81 ti,x-min = /bits/ 16 <125>;
82 touchscreen-size-x = <4008>;
83 ti,y-min = /bits/ 16 <282>;
84 touchscreen-size-y = <3864>;
85 ti,x-plate-ohms = /bits/ 16 <1
86 touchscreen-max-pressure = <25
87 touchscreen-average-samples =
88 ti,debounce-tol = /bits/ 16 <3
89 ti,debounce-rep = /bits/ 16 <1
90 ti,settle-delay-usec = /bits/
91 ti,keep-vref-on;
92 wakeup-source;
93 };
94 };
95
96 &fec1 {
97 pinctrl-names = "default", "sleep";
98 pinctrl-0 = <&pinctrl_fec1>;
99 pinctrl-1 = <&pinctrl_fec1_sleep>;
100 phy-mode = "rgmii";
101 phy-handle = <ðphy>;
102 phy-supply = <®_eth_phy>;
103 fsl,magic-packet;
104 status = "okay";
105
106 mdio {
107 #address-cells = <1>;
108 #size-cells = <0>;
109
110 ethphy: ethernet-phy@4 { /* AR
111 compatible = "ethernet
112 reg = <4>;
113 reset-gpios = <&gpio1
114 reset-assert-us = <100
115 /*
116 * Deassert delay:
117 * ADIN1300 requires 5
118 * AR8033 requires 1
119 */
120 reset-deassert-us = <2
121 };
122 };
123 };
124
125 &i2c1 {
126 clock-frequency = <400000>;
127 pinctrl-names = "default";
128 pinctrl-0 = <&pinctrl_i2c1>;
129 status = "okay";
130
131 pmic@4b {
132 compatible = "rohm,bd71847";
133 reg = <0x4b>;
134 pinctrl-names = "default";
135 pinctrl-0 = <&pinctrl_pmic>;
136 interrupt-parent = <&gpio2>;
137 interrupts = <8 IRQ_TYPE_LEVEL
138 rohm,reset-snvs-powered;
139
140 regulators {
141 buck1_reg: BUCK1 {
142 regulator-name
143 regulator-min-
144 regulator-max-
145 regulator-boot
146 regulator-alwa
147 regulator-ramp
148 };
149
150 buck2_reg: BUCK2 {
151 regulator-name
152 regulator-min-
153 regulator-max-
154 regulator-boot
155 regulator-alwa
156 regulator-ramp
157 rohm,dvs-run-v
158 rohm,dvs-idle-
159 };
160
161 buck3_reg: BUCK3 {
162 regulator-name
163 regulator-min-
164 regulator-max-
165 regulator-boot
166 regulator-alwa
167 };
168
169 buck4_reg: BUCK4 {
170 regulator-name
171 regulator-min-
172 regulator-max-
173 regulator-boot
174 regulator-alwa
175 };
176
177 buck5_reg: BUCK5 {
178 regulator-name
179 regulator-min-
180 regulator-max-
181 regulator-boot
182 regulator-alwa
183 };
184
185 buck6_reg: BUCK6 {
186 regulator-name
187 regulator-min-
188 regulator-max-
189 regulator-boot
190 regulator-alwa
191 };
192
193 ldo1_reg: LDO1 {
194 regulator-name
195 regulator-min-
196 regulator-max-
197 regulator-boot
198 regulator-alwa
199 };
200
201 ldo2_reg: LDO2 {
202 regulator-name
203 regulator-min-
204 regulator-max-
205 regulator-boot
206 regulator-alwa
207 };
208
209 ldo3_reg: LDO3 {
210 regulator-name
211 regulator-min-
212 regulator-max-
213 regulator-boot
214 regulator-alwa
215 };
216
217 ldo4_reg: LDO4 {
218 regulator-name
219 regulator-min-
220 regulator-max-
221 regulator-alwa
222 };
223
224 ldo5_reg: LDO5 {
225 regulator-name
226 regulator-min-
227 regulator-max-
228 regulator-alwa
229 };
230
231 ldo6_reg: LDO6 {
232 regulator-name
233 regulator-min-
234 regulator-max-
235 regulator-boot
236 regulator-alwa
237 };
238 };
239 };
240
241 eeprom_som: eeprom@52 {
242 compatible = "atmel,24c04";
243 reg = <0x52>;
244 pagesize = <16>;
245 vcc-supply = <®_3v3_fixed>;
246 };
247 };
248
249 &i2c3 {
250 clock-frequency = <400000>;
251 pinctrl-names = "default";
252 pinctrl-0 = <&pinctrl_i2c3>;
253 status = "okay";
254
255 /* TODO: configure audio, as of now ju
256 wm8904: codec@1a {
257 compatible = "wlf,wm8904";
258 reg = <0x1a>;
259 status = "disabled";
260 };
261 };
262
263 &snvs_pwrkey {
264 status = "okay";
265 };
266
267 /* Bluetooth */
268 &uart2 {
269 pinctrl-names = "default";
270 pinctrl-0 = <&pinctrl_uart2>;
271 assigned-clocks = <&clk IMX8MN_CLK_UAR
272 assigned-clock-parents = <&clk IMX8MN_
273 uart-has-rtscts;
274 status = "okay";
275 };
276
277 /* Console */
278 &uart4 {
279 pinctrl-names = "default";
280 pinctrl-0 = <&pinctrl_uart4>;
281 status = "okay";
282 };
283
284 &usbotg1 {
285 dr_mode = "otg";
286 usb-role-switch;
287 status = "okay";
288 };
289
290 /* WIFI */
291 &usdhc1 {
292 #address-cells = <1>;
293 #size-cells = <0>;
294 pinctrl-names = "default", "state_100m
295 pinctrl-0 = <&pinctrl_usdhc1>;
296 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
297 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
298 bus-width = <4>;
299 non-removable;
300 keep-power-in-suspend;
301 status = "okay";
302
303 brcmf: bcrmf@1 {
304 reg = <1>;
305 compatible = "brcm,bcm4329-fma
306 };
307 };
308
309 /* SD */
310 &usdhc2 {
311 assigned-clocks = <&clk IMX8MN_CLK_USD
312 assigned-clock-rates = <200000000>;
313 pinctrl-names = "default", "state_100m
314 pinctrl-0 = <&pinctrl_usdhc2>, <&pinct
315 pinctrl-1 = <&pinctrl_usdhc2_100mhz>,
316 pinctrl-2 = <&pinctrl_usdhc2_200mhz>,
317 cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>
318 bus-width = <4>;
319 vmmc-supply = <®_usdhc2_vmmc>;
320 status = "okay";
321 };
322
323 /* eMMC */
324 &usdhc3 {
325 assigned-clocks = <&clk IMX8MN_CLK_USD
326 assigned-clock-rates = <400000000>;
327 pinctrl-names = "default", "state_100m
328 pinctrl-0 = <&pinctrl_usdhc3>;
329 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
330 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
331 bus-width = <8>;
332 non-removable;
333 status = "okay";
334 };
335
336 &wdog1 {
337 pinctrl-names = "default";
338 pinctrl-0 = <&pinctrl_wdog>;
339 fsl,ext-reset-output;
340 status = "okay";
341 };
342
343 &iomuxc {
344 pinctrl_ecspi1: ecspi1grp {
345 fsl,pins = <
346 MX8MN_IOMUXC_ECSPI1_SC
347 MX8MN_IOMUXC_ECSPI1_MO
348 MX8MN_IOMUXC_ECSPI1_MI
349 MX8MN_IOMUXC_GPIO1_IO1
350 MX8MN_IOMUXC_GPIO1_IO0
351 >;
352 };
353
354 pinctrl_fec1: fec1grp {
355 fsl,pins = <
356 MX8MN_IOMUXC_ENET_MDC_
357 MX8MN_IOMUXC_ENET_MDIO
358 MX8MN_IOMUXC_ENET_TD3_
359 MX8MN_IOMUXC_ENET_TD2_
360 MX8MN_IOMUXC_ENET_TD1_
361 MX8MN_IOMUXC_ENET_TD0_
362 MX8MN_IOMUXC_ENET_RD3_
363 MX8MN_IOMUXC_ENET_RD2_
364 MX8MN_IOMUXC_ENET_RD1_
365 MX8MN_IOMUXC_ENET_RD0_
366 MX8MN_IOMUXC_ENET_TXC_
367 MX8MN_IOMUXC_ENET_RXC_
368 MX8MN_IOMUXC_ENET_RX_C
369 MX8MN_IOMUXC_ENET_TX_C
370 MX8MN_IOMUXC_GPIO1_IO0
371 >;
372 };
373
374 pinctrl_fec1_sleep: fec1sleepgrp {
375 fsl,pins = <
376 MX8MN_IOMUXC_ENET_MDC_
377 MX8MN_IOMUXC_ENET_MDIO
378 MX8MN_IOMUXC_ENET_TD3_
379 MX8MN_IOMUXC_ENET_TD2_
380 MX8MN_IOMUXC_ENET_TD1_
381 MX8MN_IOMUXC_ENET_TD0_
382 MX8MN_IOMUXC_ENET_RD3_
383 MX8MN_IOMUXC_ENET_RD2_
384 MX8MN_IOMUXC_ENET_RD1_
385 MX8MN_IOMUXC_ENET_RD0_
386 MX8MN_IOMUXC_ENET_TXC_
387 MX8MN_IOMUXC_ENET_RXC_
388 MX8MN_IOMUXC_ENET_RX_C
389 MX8MN_IOMUXC_ENET_TX_C
390 MX8MN_IOMUXC_GPIO1_IO0
391 >;
392 };
393
394 pinctrl_i2c1: i2c1grp {
395 fsl,pins = <
396 MX8MN_IOMUXC_I2C1_SCL_
397 MX8MN_IOMUXC_I2C1_SDA_
398 >;
399 };
400
401 pinctrl_i2c3: i2c3grp {
402 fsl,pins = <
403 MX8MN_IOMUXC_I2C3_SCL_
404 MX8MN_IOMUXC_I2C3_SDA_
405 >;
406 };
407
408 pinctrl_pmic: pmicirqgrp {
409 fsl,pins = <
410 MX8MN_IOMUXC_SD1_DATA6
411 >;
412 };
413
414 pinctrl_reg_eth_phy: regethphygrp {
415 fsl,pins = <
416 MX8MN_IOMUXC_SD1_DATA7
417 >;
418 };
419
420 pinctrl_restouch: restouchgrp {
421 fsl,pins = <
422 MX8MN_IOMUXC_GPIO1_IO0
423 >;
424 };
425
426 pinctrl_uart2: uart2grp {
427 fsl,pins = <
428 MX8MN_IOMUXC_SAI3_TXFS
429 MX8MN_IOMUXC_SAI3_TXC_
430 MX8MN_IOMUXC_SAI3_RXC_
431 MX8MN_IOMUXC_SAI3_RXD_
432 >;
433 };
434
435 pinctrl_uart4: uart4grp {
436 fsl,pins = <
437 MX8MN_IOMUXC_UART4_RXD
438 MX8MN_IOMUXC_UART4_TXD
439 >;
440 };
441
442 pinctrl_usdhc1: usdhc1grp {
443 fsl,pins = <
444 MX8MN_IOMUXC_SD1_CLK_U
445 MX8MN_IOMUXC_SD1_CMD_U
446 MX8MN_IOMUXC_SD1_DATA0
447 MX8MN_IOMUXC_SD1_DATA1
448 MX8MN_IOMUXC_SD1_DATA2
449 MX8MN_IOMUXC_SD1_DATA3
450 >;
451 };
452
453 pinctrl_usdhc1_100mhz: usdhc1-100mhzgr
454 fsl,pins = <
455 MX8MN_IOMUXC_SD1_CLK_U
456 MX8MN_IOMUXC_SD1_CMD_U
457 MX8MN_IOMUXC_SD1_DATA0
458 MX8MN_IOMUXC_SD1_DATA1
459 MX8MN_IOMUXC_SD1_DATA2
460 MX8MN_IOMUXC_SD1_DATA3
461 >;
462 };
463
464 pinctrl_usdhc1_200mhz: usdhc1-200mhzgr
465 fsl,pins = <
466 MX8MN_IOMUXC_SD1_CLK_U
467 MX8MN_IOMUXC_SD1_CMD_U
468 MX8MN_IOMUXC_SD1_DATA0
469 MX8MN_IOMUXC_SD1_DATA1
470 MX8MN_IOMUXC_SD1_DATA2
471 MX8MN_IOMUXC_SD1_DATA3
472 >;
473 };
474
475 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
476 fsl,pins = <
477 MX8MN_IOMUXC_GPIO1_IO1
478 >;
479 };
480
481 pinctrl_usdhc2: usdhc2grp {
482 fsl,pins = <
483 MX8MN_IOMUXC_SD2_CLK_U
484 MX8MN_IOMUXC_SD2_CMD_U
485 MX8MN_IOMUXC_SD2_DATA0
486 MX8MN_IOMUXC_SD2_DATA1
487 MX8MN_IOMUXC_SD2_DATA2
488 MX8MN_IOMUXC_SD2_DATA3
489 MX8MN_IOMUXC_GPIO1_IO0
490 >;
491 };
492
493 pinctrl_usdhc2_100mhz: usdhc2-100mhzgr
494 fsl,pins = <
495 MX8MN_IOMUXC_SD2_CLK_U
496 MX8MN_IOMUXC_SD2_CMD_U
497 MX8MN_IOMUXC_SD2_DATA0
498 MX8MN_IOMUXC_SD2_DATA1
499 MX8MN_IOMUXC_SD2_DATA2
500 MX8MN_IOMUXC_SD2_DATA3
501 MX8MN_IOMUXC_GPIO1_IO0
502 >;
503 };
504
505 pinctrl_usdhc2_200mhz: usdhc2-200mhzgr
506 fsl,pins = <
507 MX8MN_IOMUXC_SD2_CLK_U
508 MX8MN_IOMUXC_SD2_CMD_U
509 MX8MN_IOMUXC_SD2_DATA0
510 MX8MN_IOMUXC_SD2_DATA1
511 MX8MN_IOMUXC_SD2_DATA2
512 MX8MN_IOMUXC_SD2_DATA3
513 MX8MN_IOMUXC_GPIO1_IO0
514 >;
515 };
516
517 pinctrl_usdhc3: usdhc3grp {
518 fsl,pins = <
519 MX8MN_IOMUXC_NAND_WE_B
520 MX8MN_IOMUXC_NAND_WP_B
521 MX8MN_IOMUXC_NAND_DATA
522 MX8MN_IOMUXC_NAND_DATA
523 MX8MN_IOMUXC_NAND_DATA
524 MX8MN_IOMUXC_NAND_DATA
525 MX8MN_IOMUXC_NAND_RE_B
526 MX8MN_IOMUXC_NAND_CE2_
527 MX8MN_IOMUXC_NAND_CE3_
528 MX8MN_IOMUXC_NAND_CLE_
529 MX8MN_IOMUXC_NAND_CE1_
530 >;
531 };
532
533 pinctrl_usdhc3_100mhz: usdhc3-100mhzgr
534 fsl,pins = <
535 MX8MN_IOMUXC_NAND_WE_B
536 MX8MN_IOMUXC_NAND_WP_B
537 MX8MN_IOMUXC_NAND_DATA
538 MX8MN_IOMUXC_NAND_DATA
539 MX8MN_IOMUXC_NAND_DATA
540 MX8MN_IOMUXC_NAND_DATA
541 MX8MN_IOMUXC_NAND_RE_B
542 MX8MN_IOMUXC_NAND_CE2_
543 MX8MN_IOMUXC_NAND_CE3_
544 MX8MN_IOMUXC_NAND_CLE_
545 MX8MN_IOMUXC_NAND_CE1_
546 >;
547 };
548
549 pinctrl_usdhc3_200mhz: usdhc3-200mhzgr
550 fsl,pins = <
551 MX8MN_IOMUXC_NAND_WE_B
552 MX8MN_IOMUXC_NAND_WP_B
553 MX8MN_IOMUXC_NAND_DATA
554 MX8MN_IOMUXC_NAND_DATA
555 MX8MN_IOMUXC_NAND_DATA
556 MX8MN_IOMUXC_NAND_DATA
557 MX8MN_IOMUXC_NAND_RE_B
558 MX8MN_IOMUXC_NAND_CE2_
559 MX8MN_IOMUXC_NAND_CE3_
560 MX8MN_IOMUXC_NAND_CLE_
561 MX8MN_IOMUXC_NAND_CE1_
562 >;
563 };
564
565 pinctrl_wdog: wdoggrp {
566 fsl,pins = <
567 MX8MN_IOMUXC_GPIO1_IO0
568 >;
569 };
570 };
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