1 // SPDX-License-Identifier: GPL-2.0-or-later O
2 /*
3 * Copyright 2021-2022 TQ-Systems GmbH
4 * Author: Alexander Stein <alexander.stein@tq-
5 */
6
7 /dts-v1/;
8
9 #include <dt-bindings/leds/common.h>
10 #include <dt-bindings/net/ti-dp83867.h>
11 #include <dt-bindings/phy/phy-imx8-pcie.h>
12 #include <dt-bindings/pwm/pwm.h>
13 #include "imx8mp-tqma8mpql.dtsi"
14
15 / {
16 model = "TQ-Systems i.MX8MPlus TQMa8MP
17 compatible = "tq,imx8mp-tqma8mpql-mba8
18 chassis-type = "embedded";
19
20 chosen {
21 stdout-path = &uart4;
22 };
23
24 iio-hwmon {
25 compatible = "iio-hwmon";
26 io-channels = <&adc 0>, <&adc
27 };
28
29 aliases {
30 mmc0 = &usdhc3;
31 mmc1 = &usdhc2;
32 mmc2 = &usdhc1;
33 rtc0 = &pcf85063;
34 rtc1 = &snvs_rtc;
35 spi0 = &flexspi;
36 spi1 = &ecspi1;
37 spi2 = &ecspi2;
38 spi3 = &ecspi3;
39 };
40
41 backlight_lvds: backlight {
42 compatible = "pwm-backlight";
43 pinctrl-names = "default";
44 pinctrl-0 = <&pinctrl_backligh
45 pwms = <&pwm2 0 5000000 0>;
46 brightness-levels = <0 4 8 16
47 default-brightness-level = <7>
48 power-supply = <®_vcc_12v0>
49 enable-gpios = <&gpio3 19 GPIO
50 status = "disabled";
51 };
52
53 clk_xtal25: clk-xtal25 {
54 compatible = "fixed-clock";
55 #clock-cells = <0>;
56 clock-frequency = <25000000>;
57 };
58
59 connector {
60 compatible = "gpio-usb-b-conne
61 type = "micro";
62 label = "X29";
63 pinctrl-names = "default";
64 pinctrl-0 = <&pinctrl_usbcon0>
65 id-gpios = <&gpio1 10 GPIO_ACT
66
67 port {
68 usb_dr_connector: endp
69 remote-endpoin
70 };
71 };
72 };
73
74 fan0: pwm-fan {
75 compatible = "pwm-fan";
76 pinctrl-names = "default";
77 pinctrl-0 = <&pinctrl_pwmfan>;
78 fan-supply = <®_pwm_fan>;
79 #cooling-cells = <2>;
80 /* typical 25 kHz -> 40.000 ns
81 pwms = <&pwm3 0 40000 PWM_POLA
82 cooling-levels = <0 32 64 128
83 pulses-per-revolution = <2>;
84 interrupt-parent = <&gpio5>;
85 interrupts = <18 IRQ_TYPE_EDGE
86 status = "disabled";
87 };
88
89 gpio-keys {
90 compatible = "gpio-keys";
91 pinctrl-names = "default";
92 pinctrl-0 = <&pinctrl_gpiobutt
93 autorepeat;
94
95 switch-1 {
96 label = "S12";
97 linux,code = <BTN_0>;
98 gpios = <&gpio5 27 GPI
99 wakeup-source;
100 };
101
102 switch-2 {
103 label = "S13";
104 linux,code = <BTN_1>;
105 gpios = <&gpio5 26 GPI
106 wakeup-source;
107 };
108 };
109
110 gpio-leds {
111 compatible = "gpio-leds";
112 pinctrl-names = "default";
113 pinctrl-0 = <&pinctrl_gpioled>
114
115 led-0 {
116 color = <LED_COLOR_ID_
117 function = LED_FUNCTIO
118 function-enumerator =
119 gpios = <&gpio5 5 GPIO
120 linux,default-trigger
121 };
122
123 led-1 {
124 color = <LED_COLOR_ID_
125 function = LED_FUNCTIO
126 gpios = <&gpio5 4 GPIO
127 linux,default-trigger
128 };
129
130 led-2 {
131 color = <LED_COLOR_ID_
132 function = LED_FUNCTIO
133 function-enumerator =
134 gpios = <&gpio5 3 GPIO
135 };
136 };
137
138 hdmi-connector {
139 compatible = "hdmi-connector";
140 label = "X44";
141 type = "a";
142
143 port {
144 hdmi_connector_in: end
145 remote-endpoin
146 };
147 };
148 };
149
150 display: display {
151 /*
152 * Display is not fixed, so co
153 * DT overlay
154 */
155 pinctrl-names = "default";
156 pinctrl-0 = <&pinctrl_lvdsdisp
157 power-supply = <®_vcc_3v3>;
158 enable-gpios = <&gpio3 20 GPIO
159 backlight = <&backlight_lvds>;
160 status = "disabled";
161 };
162
163 reg_pwm_fan: regulator-pwm-fan {
164 compatible = "regulator-fixed"
165 pinctrl-names = "default";
166 pinctrl-0 = <&pinctrl_regpwmfa
167 regulator-name = "FAN_PWR";
168 regulator-min-microvolt = <120
169 regulator-max-microvolt = <120
170 gpio = <&gpio4 27 GPIO_ACTIVE_
171 enable-active-high;
172 vin-supply = <®_vcc_12v0>;
173 };
174
175 reg_usdhc2_vmmc: regulator-usdhc2 {
176 compatible = "regulator-fixed"
177 pinctrl-names = "default";
178 pinctrl-0 = <&pinctrl_reg_usdh
179 regulator-name = "VSD_3V3";
180 regulator-min-microvolt = <330
181 regulator-max-microvolt = <330
182 gpio = <&gpio2 19 GPIO_ACTIVE_
183 enable-active-high;
184 startup-delay-us = <100>;
185 off-on-delay-us = <12000>;
186 };
187
188 reg_vcc_12v0: regulator-12v0 {
189 compatible = "regulator-fixed"
190 pinctrl-names = "default";
191 pinctrl-0 = <&pinctrl_reg12v0>
192 regulator-name = "VCC_12V0";
193 regulator-min-microvolt = <120
194 regulator-max-microvolt = <120
195 gpio = <&gpio2 6 GPIO_ACTIVE_H
196 enable-active-high;
197 };
198
199 reg_vcc_1v8: regulator-1v8 {
200 compatible = "regulator-fixed"
201 regulator-name = "VCC_1V8";
202 regulator-min-microvolt = <180
203 regulator-max-microvolt = <180
204 };
205
206 reg_vcc_3v3: regulator-3v3 {
207 compatible = "regulator-fixed"
208 regulator-name = "VCC_3V3";
209 regulator-min-microvolt = <330
210 regulator-max-microvolt = <330
211 };
212
213 reg_vcc_5v0: regulator-5v0 {
214 compatible = "regulator-fixed"
215 regulator-name = "VCC_5V0";
216 regulator-min-microvolt = <500
217 regulator-max-microvolt = <500
218 };
219
220 reserved-memory {
221 #address-cells = <2>;
222 #size-cells = <2>;
223 ranges;
224
225 /* global autoconfigured regio
226 linux,cma {
227 compatible = "shared-d
228 reusable;
229 size = <0 0x38000000>;
230 alloc-ranges = <0 0x40
231 linux,cma-default;
232 };
233 };
234
235 sound {
236 compatible = "fsl,imx-audio-tl
237 model = "tq-tlv320aic32x";
238 audio-cpu = <&sai3>;
239 audio-codec = <&tlv320aic3x04>
240 };
241
242 thermal-zones {
243 soc-thermal {
244 trips {
245 soc_active0: t
246 temper
247 hyster
248 type =
249 };
250
251 soc_active1: t
252 temper
253 hyster
254 type =
255 };
256
257 soc_active2: t
258 temper
259 hyster
260 type =
261 };
262 };
263
264 cooling-maps {
265 map1 {
266 trip =
267 coolin
268 };
269
270 map2 {
271 trip =
272 coolin
273 };
274
275 map3 {
276 trip =
277 coolin
278 };
279 };
280 };
281 };
282 };
283
284 &ecspi1 {
285 pinctrl-names = "default";
286 pinctrl-0 = <&pinctrl_ecspi1>;
287 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
288 status = "okay";
289 };
290
291 &ecspi2 {
292 pinctrl-names = "default";
293 pinctrl-0 = <&pinctrl_ecspi2>;
294 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>
295 status = "okay";
296 };
297
298 &ecspi3 {
299 pinctrl-names = "default";
300 pinctrl-0 = <&pinctrl_ecspi3>;
301 cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>
302 status = "okay";
303
304 adc: adc@0 {
305 reg = <0>;
306 compatible = "microchip,mcp320
307 /* 100 ksps * 18 */
308 spi-max-frequency = <1800000>;
309 vref-supply = <®_vcc_3v3>;
310 #io-channel-cells = <1>;
311 };
312 };
313
314 &eqos {
315 pinctrl-names = "default";
316 pinctrl-0 = <&pinctrl_eqos>, <&pinctrl
317 phy-mode = "rgmii-id";
318 phy-handle = <ðphy3>;
319 status = "okay";
320
321 mdio {
322 compatible = "snps,dwmac-mdio"
323 #address-cells = <1>;
324 #size-cells = <0>;
325
326 ethphy3: ethernet-phy@3 {
327 compatible = "ethernet
328 reg = <3>;
329 ti,rx-internal-delay =
330 ti,tx-internal-delay =
331 ti,fifo-depth = <DP838
332 ti,dp83867-rxctrl-stra
333 ti,clk-output-sel = <D
334 reset-gpios = <&gpio4
335 reset-assert-us = <500
336 reset-deassert-us = <5
337 enet-phy-lane-no-swap;
338 interrupt-parent = <&g
339 interrupts = <3 IRQ_TY
340 };
341 };
342 };
343
344 &fec {
345 pinctrl-names = "default";
346 pinctrl-0 = <&pinctrl_fec>, <&pinctrl_
347 phy-mode = "rgmii-id";
348 phy-handle = <ðphy0>;
349 fsl,magic-packet;
350 status = "okay";
351
352 mdio {
353 #address-cells = <1>;
354 #size-cells = <0>;
355
356 ethphy0: ethernet-phy@0 {
357 compatible = "ethernet
358 reg = <0>;
359 ti,rx-internal-delay =
360 ti,tx-internal-delay =
361 ti,fifo-depth = <DP838
362 ti,dp83867-rxctrl-stra
363 ti,clk-output-sel = <D
364 reset-gpios = <&gpio4
365 reset-assert-us = <500
366 reset-deassert-us = <5
367 enet-phy-lane-no-swap;
368 interrupt-parent = <&g
369 interrupts = <1 IRQ_TY
370 };
371 };
372 };
373
374 &flexcan1 {
375 pinctrl-names = "default";
376 pinctrl-0 = <&pinctrl_flexcan1>;
377 xceiver-supply = <®_vcc_3v3>;
378 status = "okay";
379 };
380
381 &flexcan2 {
382 pinctrl-names = "default";
383 pinctrl-0 = <&pinctrl_flexcan2>;
384 xceiver-supply = <®_vcc_3v3>;
385 status = "okay";
386 };
387
388 &gpio1 {
389 pinctrl-names = "default";
390 pinctrl-0 = <&pinctrl_gpio1>;
391
392 gpio-line-names = "GPO1", "GPO0", "",
393 "", "", "GPO2", "GPI
394 "PMIC_IRQ", "GPI1",
395 "OTG_PWR", "", "GPI2
396 "", "", "", "",
397 "", "", "", "",
398 "", "", "", "",
399 "", "", "", "";
400 };
401
402 &gpio2 {
403 pinctrl-names = "default";
404 pinctrl-0 = <&pinctrl_hoggpio2>;
405
406 gpio-line-names = "", "", "", "",
407 "", "", "VCC12V_EN",
408 "", "", "CLKREQ#", "
409 "USDHC2_CD", "", "",
410 "", "", "", "V_SD3V3
411 "", "", "", "",
412 "", "", "", "",
413 "", "", "", "";
414
415 perst-hog {
416 gpio-hog;
417 gpios = <7 0>;
418 output-high;
419 line-name = "PERST#";
420 };
421
422 clkreq-hog {
423 gpio-hog;
424 gpios = <10 0>;
425 input;
426 line-name = "CLKREQ#";
427 };
428
429 pewake-hog {
430 gpio-hog;
431 gpios = <11 0>;
432 input;
433 line-name = "PEWAKE#";
434 };
435 };
436
437 &gpio3 {
438 gpio-line-names = "", "", "", "",
439 "", "", "", "",
440 "", "", "", "",
441 "", "", "LVDS0_RESET
442 "", "", "", "LVDS0_B
443 "LVDS0_PWR_EN", "",
444 "", "", "", "",
445 "", "", "", "";
446 };
447
448 &gpio4 {
449 pinctrl-names = "default";
450 pinctrl-0 = <&pinctrl_gpio4>;
451
452 gpio-line-names = "ENET0_RST#", "ENET0
453 "", "", "", "",
454 "", "", "", "",
455 "", "", "", "",
456 "", "", "DP_IRQ", "D
457 "HDMI_OC#", "TEMP_EV
458 "", "", "", "FAN_PWR
459 "RTC_EVENT#", "CODEC
460
461 pcie-refclkreq-hog {
462 gpio-hog;
463 gpios = <22 0>;
464 output-high;
465 line-name = "PCIE_REFCLK_OE#";
466 };
467 };
468
469 &gpio5 {
470 gpio-line-names = "", "", "", "LED2",
471 "LED1", "LED0", "CSI
472 "CSI0_TRIGGER", "CSI
473 "", "ECSPI2_SS0", ""
474 "", "", "", "",
475 "", "", "", "",
476 "", "ECSPI3_SS0", "S
477 "", "", "", "";
478 };
479
480 &hdmi_pvi {
481 status = "okay";
482 };
483
484 &hdmi_tx {
485 pinctrl-names = "default";
486 pinctrl-0 = <&pinctrl_hdmi>;
487 status = "okay";
488
489 ports {
490 port@1 {
491 hdmi_tx_out: endpoint
492 remote-endpoin
493 };
494 };
495 };
496 };
497
498 &hdmi_tx_phy {
499 status = "okay";
500 };
501
502 &i2c2 {
503 clock-frequency = <384000>;
504 pinctrl-names = "default", "gpio";
505 pinctrl-0 = <&pinctrl_i2c2>;
506 pinctrl-1 = <&pinctrl_i2c2_gpio>;
507 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HI
508 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HI
509 status = "okay";
510
511 tlv320aic3x04: audio-codec@18 {
512 compatible = "ti,tlv320aic32x4
513 pinctrl-names = "default";
514 pinctrl-0 = <&pinctrl_tlv320ai
515 reg = <0x18>;
516 clock-names = "mclk";
517 clocks = <&audio_blk_ctrl IMX8
518 reset-gpios = <&gpio4 29 GPIO_
519 iov-supply = <®_vcc_1v8>;
520 ldoin-supply = <®_vcc_3v3>;
521 };
522
523 se97_1c: temperature-sensor@1c {
524 compatible = "nxp,se97b", "jed
525 reg = <0x1c>;
526 };
527
528 at24c02_54: eeprom@54 {
529 compatible = "nxp,se97b", "atm
530 reg = <0x54>;
531 pagesize = <16>;
532 vcc-supply = <®_vcc_3v3>;
533 };
534
535 pcieclk: clock-generator@6a {
536 compatible = "renesas,9fgv0241
537 reg = <0x6a>;
538 clocks = <&clk_xtal25>;
539 #clock-cells = <1>;
540 };
541 };
542
543 &i2c4 {
544 clock-frequency = <384000>;
545 pinctrl-names = "default", "gpio";
546 pinctrl-0 = <&pinctrl_i2c4>;
547 pinctrl-1 = <&pinctrl_i2c4_gpio>;
548 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HI
549 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HI
550 status = "okay";
551 };
552
553 &i2c6 {
554 clock-frequency = <384000>;
555 pinctrl-names = "default", "gpio";
556 pinctrl-0 = <&pinctrl_i2c6>;
557 pinctrl-1 = <&pinctrl_i2c6_gpio>;
558 scl-gpios = <&gpio2 2 (GPIO_ACTIVE_HIG
559 sda-gpios = <&gpio2 3 (GPIO_ACTIVE_HIG
560 status = "okay";
561 };
562
563 &lcdif3 {
564 status = "okay";
565 };
566
567 &pcf85063 {
568 /* RTC_EVENT# is connected on MBa8MPxL
569 pinctrl-names = "default";
570 pinctrl-0 = <&pinctrl_pcf85063>;
571 interrupt-parent = <&gpio4>;
572 interrupts = <28 IRQ_TYPE_EDGE_FALLING
573 };
574
575 &pcie_phy {
576 fsl,clkreq-unsupported;
577 fsl,refclk-pad-mode = <IMX8_PCIE_REFCL
578 clocks = <&pcieclk 0>;
579 clock-names = "ref";
580 status = "okay";
581 };
582
583 &pcie {
584 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
585 <&clk IMX8MP_CLK_HSIO_AXI>,
586 <&clk IMX8MP_CLK_PCIE_ROOT>;
587 clock-names = "pcie", "pcie_bus", "pci
588 assigned-clocks = <&clk IMX8MP_CLK_PCI
589 assigned-clock-rates = <10000000>;
590 assigned-clock-parents = <&clk IMX8MP_
591 status = "okay";
592 };
593
594 &pwm2 {
595 pinctrl-names = "default";
596 pinctrl-0 = <&pinctrl_pwm2>;
597 status = "disabled";
598 };
599
600 &pwm3 {
601 pinctrl-names = "default";
602 pinctrl-0 = <&pinctrl_pwm3>;
603 status = "okay";
604 };
605
606 &sai3 {
607 pinctrl-names = "default";
608 pinctrl-0 = <&pinctrl_sai3>;
609 assigned-clocks = <&clk IMX8MP_CLK_SAI
610 assigned-clock-parents = <&clk IMX8MP_
611 assigned-clock-rates = <12288000>;
612 fsl,sai-mclk-direction-output;
613 status = "okay";
614 };
615
616 &snvs_pwrkey {
617 status = "okay";
618 };
619
620 &uart1 {
621 pinctrl-names = "default";
622 pinctrl-0 = <&pinctrl_uart1>;
623 assigned-clocks = <&clk IMX8MP_CLK_UAR
624 assigned-clock-parents = <&clk IMX8MP_
625 status = "okay";
626 };
627
628 &uart2 {
629 pinctrl-names = "default";
630 pinctrl-0 = <&pinctrl_uart2>;
631 assigned-clocks = <&clk IMX8MP_CLK_UAR
632 assigned-clock-parents = <&clk IMX8MP_
633 status = "okay";
634 };
635
636 &uart3 {
637 pinctrl-names = "default";
638 pinctrl-0 = <&pinctrl_uart3>;
639 assigned-clocks = <&clk IMX8MP_CLK_UAR
640 assigned-clock-parents = <&clk IMX8MP_
641 status = "okay";
642 };
643
644 &uart4 {
645 /* console */
646 pinctrl-names = "default";
647 pinctrl-0 = <&pinctrl_uart4>;
648 status = "okay";
649 };
650
651 &usb3_0 {
652 pinctrl-names = "default";
653 pinctrl-0 = <&pinctrl_usb0>;
654 fsl,over-current-active-low;
655 status = "okay";
656 };
657
658 &usb3_1 {
659 fsl,disable-port-power-control;
660 fsl,permanently-attached;
661 status = "okay";
662 };
663
664 &usb3_phy0 {
665 vbus-supply = <®_vcc_5v0>;
666 status = "okay";
667 };
668
669 &usb3_phy1 {
670 vbus-supply = <®_vcc_5v0>;
671 status = "okay";
672 };
673
674 &usb_dwc3_0 {
675 /* dual role is implemented, but not a
676 hnp-disable;
677 srp-disable;
678 adp-disable;
679 dr_mode = "otg";
680 usb-role-switch;
681 role-switch-default-mode = "peripheral
682 status = "okay";
683
684 port {
685 usb3_dwc: endpoint {
686 remote-endpoint = <&us
687 };
688 };
689 };
690
691 &usb_dwc3_1 {
692 dr_mode = "host";
693 #address-cells = <1>;
694 #size-cells = <0>;
695 pinctrl-names = "default";
696 pinctrl-0 = <&pinctrl_usbhub>;
697 status = "okay";
698
699 hub_2_0: hub@1 {
700 compatible = "usb451,8142";
701 reg = <1>;
702 peer-hub = <&hub_3_0>;
703 reset-gpios = <&gpio1 11 GPIO_
704 vdd-supply = <®_vcc_3v3>;
705 };
706
707 hub_3_0: hub@2 {
708 compatible = "usb451,8140";
709 reg = <2>;
710 peer-hub = <&hub_2_0>;
711 reset-gpios = <&gpio1 11 GPIO_
712 vdd-supply = <®_vcc_3v3>;
713 };
714 };
715
716 &usdhc2 {
717 pinctrl-names = "default", "state_100m
718 pinctrl-0 = <&pinctrl_usdhc2>, <&pinct
719 pinctrl-1 = <&pinctrl_usdhc2_100mhz>,
720 pinctrl-2 = <&pinctrl_usdhc2_200mhz>,
721 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>
722 vmmc-supply = <®_usdhc2_vmmc>;
723 no-mmc;
724 no-sdio;
725 disable-wp;
726 bus-width = <4>;
727 status = "okay";
728 };
729
730 &iomuxc {
731 pinctrl_backlight: backlightgrp {
732 fsl,pins = <MX8MP_IOMUXC_SAI5_
733 };
734
735 pinctrl_flexcan1: flexcan1grp {
736 fsl,pins = <MX8MP_IOMUXC_SAI5_
737 <MX8MP_IOMUXC_SAI5_
738 };
739
740 pinctrl_flexcan2: flexcan2grp {
741 fsl,pins = <MX8MP_IOMUXC_SAI5_
742 <MX8MP_IOMUXC_SAI5_
743 };
744
745 /* only on X57, primary used as CSI0 c
746 pinctrl_ecspi1: ecspi1grp {
747 fsl,pins = <MX8MP_IOMUXC_ECSPI
748 <MX8MP_IOMUXC_ECSPI
749 <MX8MP_IOMUXC_ECSPI
750 <MX8MP_IOMUXC_ECSPI
751 };
752
753 /* on X63 and optionally on X57, can a
754 pinctrl_ecspi2: ecspi2grp {
755 fsl,pins = <MX8MP_IOMUXC_ECSPI
756 <MX8MP_IOMUXC_ECSPI
757 <MX8MP_IOMUXC_ECSPI
758 <MX8MP_IOMUXC_ECSPI
759 };
760
761 pinctrl_ecspi3: ecspi3grp {
762 fsl,pins = <MX8MP_IOMUXC_UART1
763 <MX8MP_IOMUXC_UART1
764 <MX8MP_IOMUXC_UART2
765 <MX8MP_IOMUXC_UART2
766 };
767
768 pinctrl_eqos: eqosgrp {
769 fsl,pins = <MX8MP_IOMUXC_ENET_
770 <MX8MP_IOMUXC_ENET_
771 <MX8MP_IOMUXC_ENET_
772 <MX8MP_IOMUXC_ENET_
773 <MX8MP_IOMUXC_ENET_
774 <MX8MP_IOMUXC_ENET_
775 <MX8MP_IOMUXC_ENET_
776 <MX8MP_IOMUXC_ENET_
777 <MX8MP_IOMUXC_ENET_
778 <MX8MP_IOMUXC_ENET_
779 <MX8MP_IOMUXC_ENET_
780 <MX8MP_IOMUXC_ENET_
781 <MX8MP_IOMUXC_ENET_
782 <MX8MP_IOMUXC_ENET_
783 };
784
785 pinctrl_eqos_event: eqosevtgrp {
786 fsl,pins = <MX8MP_IOMUXC_SAI2_
787 <MX8MP_IOMUXC_SAI2_
788 };
789
790 pinctrl_eqos_phy: eqosphygrp {
791 fsl,pins = <MX8MP_IOMUXC_SAI1_
792 <MX8MP_IOMUXC_SAI1_
793 };
794
795 pinctrl_fec: fecgrp {
796 fsl,pins = <MX8MP_IOMUXC_SAI1_
797 <MX8MP_IOMUXC_SAI1_
798 <MX8MP_IOMUXC_SAI1_
799 <MX8MP_IOMUXC_SAI1_
800 <MX8MP_IOMUXC_SAI1_
801 <MX8MP_IOMUXC_SAI1_
802 <MX8MP_IOMUXC_SAI1_
803 <MX8MP_IOMUXC_SAI1_
804 <MX8MP_IOMUXC_SAI1_
805 <MX8MP_IOMUXC_SAI1_
806 <MX8MP_IOMUXC_SAI1_
807 <MX8MP_IOMUXC_SAI1_
808 <MX8MP_IOMUXC_SAI1_
809 <MX8MP_IOMUXC_SAI1_
810 };
811
812 pinctrl_fec_event: fecevtgrp {
813 fsl,pins = <MX8MP_IOMUXC_SAI1_
814 <MX8MP_IOMUXC_SAI1_
815 };
816
817 pinctrl_fec_phy: fecphygrp {
818 fsl,pins = <MX8MP_IOMUXC_SAI1_
819 <MX8MP_IOMUXC_SAI1_
820 };
821
822 pinctrl_fec_phyalt: fecphyaltgrp {
823 fsl,pins = <MX8MP_IOMUXC_SAI2_
824 <MX8MP_IOMUXC_SAI2_
825 };
826
827 pinctrl_gpiobutton: gpiobuttongrp {
828 fsl,pins = <MX8MP_IOMUXC_UART3
829 <MX8MP_IOMUXC_UART3
830 };
831
832 pinctrl_gpioled: gpioledgrp {
833 fsl,pins = <MX8MP_IOMUXC_SPDIF
834 <MX8MP_IOMUXC_SPDIF
835 <MX8MP_IOMUXC_SPDIF
836 };
837
838 pinctrl_gpio1: gpio1grp {
839 fsl,pins = <MX8MP_IOMUXC_GPIO1
840 <MX8MP_IOMUXC_GPIO1
841 <MX8MP_IOMUXC_GPIO1
842 <MX8MP_IOMUXC_GPIO1
843 <MX8MP_IOMUXC_GPIO1
844 <MX8MP_IOMUXC_GPIO1
845 <MX8MP_IOMUXC_GPIO1
846 <MX8MP_IOMUXC_GPIO1
847 };
848
849 pinctrl_gpio4: gpio4grp {
850 fsl,pins = <MX8MP_IOMUXC_SAI1_
851 <MX8MP_IOMUXC_SAI2_
852 };
853
854 pinctrl_hdmi: hdmigrp {
855 fsl,pins = <MX8MP_IOMUXC_HDMI_
856 <MX8MP_IOMUXC_HDMI_
857 <MX8MP_IOMUXC_HDMI_
858 <MX8MP_IOMUXC_HDMI_
859 };
860
861 pinctrl_hoggpio2: hoggpio2grp {
862 fsl,pins = <MX8MP_IOMUXC_SD1_D
863 <MX8MP_IOMUXC_SD1_R
864 <MX8MP_IOMUXC_SD1_S
865 };
866
867 pinctrl_i2c2: i2c2grp {
868 fsl,pins = <MX8MP_IOMUXC_I2C2_
869 <MX8MP_IOMUXC_I2C2_
870 };
871
872 pinctrl_i2c2_gpio: i2c2-gpiogrp {
873 fsl,pins = <MX8MP_IOMUXC_I2C2_
874 <MX8MP_IOMUXC_I2C2_
875 };
876
877 pinctrl_i2c4: i2c4grp {
878 fsl,pins = <MX8MP_IOMUXC_I2C4_
879 <MX8MP_IOMUXC_I2C4_
880 };
881
882 pinctrl_i2c4_gpio: i2c4-gpiogrp {
883 fsl,pins = <MX8MP_IOMUXC_I2C4_
884 <MX8MP_IOMUXC_I2C4_
885 };
886
887 pinctrl_i2c6: i2c6grp {
888 fsl,pins = <MX8MP_IOMUXC_SD1_D
889 <MX8MP_IOMUXC_SD1_D
890 };
891
892 pinctrl_i2c6_gpio: i2c6-gpiogrp {
893 fsl,pins = <MX8MP_IOMUXC_SD1_D
894 <MX8MP_IOMUXC_SD1_D
895 };
896
897 pinctrl_lvdsdisplay: lvdsdisplaygrp {
898 fsl,pins = <MX8MP_IOMUXC_SAI5_
899 };
900
901 pinctrl_pcf85063: pcf85063grp {
902 fsl,pins = <MX8MP_IOMUXC_SAI3_
903 };
904
905 /* LVDS Backlight */
906 pinctrl_pwm2: pwm2grp {
907 fsl,pins = <MX8MP_IOMUXC_SAI5_
908 };
909
910 /* FAN */
911 pinctrl_pwm3: pwm3grp {
912 fsl,pins = <MX8MP_IOMUXC_I2C3_
913 };
914
915 pinctrl_pwmfan: pwmfangrp {
916 fsl,pins = <MX8MP_IOMUXC_I2C3_
917 };
918
919 pinctrl_reg12v0: reg12v0grp {
920 fsl,pins = <MX8MP_IOMUXC_SD1_D
921 };
922
923 pinctrl_regpwmfan: regpwmfangrp {
924 fsl,pins = <MX8MP_IOMUXC_SAI2_
925 };
926
927 pinctrl_sai3: sai3grp {
928 fsl,pins = <
929 MX8MP_IOMUXC_SAI3_TXFS
930 MX8MP_IOMUXC_SAI3_TXC_
931 MX8MP_IOMUXC_SAI3_RXD_
932 MX8MP_IOMUXC_SAI3_TXD_
933 MX8MP_IOMUXC_SAI3_MCLK
934 >;
935 };
936
937 pinctrl_tlv320aic3x04: tlv320aic3x04gr
938 fsl,pins = <
939 /* CODEC RST# */
940 MX8MP_IOMUXC_SAI3_RXC_
941 >;
942 };
943
944 /* X61 */
945 pinctrl_uart1: uart1grp {
946 fsl,pins = <MX8MP_IOMUXC_SD1_C
947 <MX8MP_IOMUXC_SD1_C
948 };
949
950 /* X61 */
951 pinctrl_uart2: uart2grp {
952 fsl,pins = <MX8MP_IOMUXC_SD1_D
953 <MX8MP_IOMUXC_SD1_D
954 };
955
956 pinctrl_uart3: uart3grp {
957 fsl,pins = <MX8MP_IOMUXC_SD1_D
958 <MX8MP_IOMUXC_SD1_D
959 };
960
961 pinctrl_uart4: uart4grp {
962 fsl,pins = <MX8MP_IOMUXC_UART4
963 <MX8MP_IOMUXC_UART4
964 };
965
966 pinctrl_usb0: usb0grp {
967 fsl,pins = <MX8MP_IOMUXC_GPIO1
968 <MX8MP_IOMUXC_GPIO1
969 };
970
971 pinctrl_usbcon0: usb0congrp {
972 fsl,pins = <MX8MP_IOMUXC_GPIO1
973 };
974
975 pinctrl_usbhub: usbhubgrp {
976 fsl,pins = <MX8MP_IOMUXC_GPIO1
977 };
978
979 pinctrl_usdhc2: usdhc2grp {
980 fsl,pins = <MX8MP_IOMUXC_SD2_C
981 <MX8MP_IOMUXC_SD2_C
982 <MX8MP_IOMUXC_SD2_D
983 <MX8MP_IOMUXC_SD2_D
984 <MX8MP_IOMUXC_SD2_D
985 <MX8MP_IOMUXC_SD2_D
986 <MX8MP_IOMUXC_GPIO1
987 };
988
989 pinctrl_usdhc2_100mhz: usdhc2-100mhzgr
990 fsl,pins = <MX8MP_IOMUXC_SD2_C
991 <MX8MP_IOMUXC_SD2_C
992 <MX8MP_IOMUXC_SD2_D
993 <MX8MP_IOMUXC_SD2_D
994 <MX8MP_IOMUXC_SD2_D
995 <MX8MP_IOMUXC_SD2_D
996 <MX8MP_IOMUXC_GPIO1
997 };
998
999 pinctrl_usdhc2_200mhz: usdhc2-200mhzgr
1000 fsl,pins = <MX8MP_IOMUXC_SD2_
1001 <MX8MP_IOMUXC_SD2_
1002 <MX8MP_IOMUXC_SD2_
1003 <MX8MP_IOMUXC_SD2_
1004 <MX8MP_IOMUXC_SD2_
1005 <MX8MP_IOMUXC_SD2_
1006 <MX8MP_IOMUXC_GPIO
1007 };
1008
1009 pinctrl_usdhc2_gpio: usdhc2-gpiogrp {
1010 fsl,pins = <MX8MP_IOMUXC_SD2_
1011 };
1012 };
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