1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2018 Einfochips
4 * Copyright 2019 Linaro Ltd.
5 */
6
7 /dts-v1/;
8
9 #include "imx8qxp.dtsi"
10
11 / {
12 model = "Einfochips i.MX8QXP AI_ML";
13 compatible = "einfochips,imx8qxp-ai_ml
14
15 aliases {
16 serial1 = &lpuart1;
17 serial2 = &lpuart2;
18 serial3 = &lpuart3;
19 };
20
21 chosen {
22 stdout-path = &lpuart2;
23 };
24
25 memory@80000000 {
26 device_type = "memory";
27 reg = <0x00000000 0x80000000 0
28 };
29
30 leds {
31 compatible = "gpio-leds";
32 pinctrl-names = "default";
33 pinctrl-0 = <&pinctrl_leds>;
34
35 user-led1 {
36 label = "green:user1";
37 gpios = <&lsio_gpio4 1
38 linux,default-trigger
39 };
40
41 user-led2 {
42 label = "green:user2";
43 gpios = <&lsio_gpio0 6
44 linux,default-trigger
45 };
46
47 user-led3 {
48 label = "green:user3";
49 gpios = <&lsio_gpio0 7
50 linux,default-trigger
51 default-state = "off";
52 };
53
54 user-led4 {
55 label = "green:user4";
56 gpios = <&lsio_gpio4 2
57 panic-indicator;
58 linux,default-trigger
59 };
60
61 wlan-active-led {
62 label = "yellow:wlan";
63 gpios = <&lsio_gpio4 1
64 linux,default-trigger
65 default-state = "off";
66 };
67
68 bt-active-led {
69 label = "blue:bt";
70 gpios = <&lsio_gpio4 1
71 linux,default-trigger
72 default-state = "off";
73 };
74 };
75
76 sdio_pwrseq: sdio-pwrseq {
77 compatible = "mmc-pwrseq-simpl
78 pinctrl-names = "default";
79 pinctrl-0 = <&pinctrl_wifi_reg
80 reset-gpios = <&lsio_gpio3 24
81 };
82 };
83
84 /* BT */
85 &lpuart0 {
86 pinctrl-names = "default";
87 pinctrl-0 = <&pinctrl_lpuart0>;
88 uart-has-rtscts;
89 status = "okay";
90 };
91
92 /* LS-UART0 */
93 &lpuart1 {
94 pinctrl-names = "default";
95 pinctrl-0 = <&pinctrl_lpuart1>;
96 status = "okay";
97 };
98
99 /* Debug */
100 &lpuart2 {
101 pinctrl-names = "default";
102 pinctrl-0 = <&pinctrl_lpuart2>;
103 status = "okay";
104 };
105
106 /* PCI-E UART */
107 &lpuart3 {
108 pinctrl-names = "default";
109 pinctrl-0 = <&pinctrl_lpuart3>;
110 status = "okay";
111 };
112
113 &fec1 {
114 pinctrl-names = "default";
115 pinctrl-0 = <&pinctrl_fec1>;
116 phy-mode = "rgmii-id";
117 phy-handle = <ðphy0>;
118 fsl,magic-packet;
119 status = "okay";
120
121 mdio {
122 #address-cells = <1>;
123 #size-cells = <0>;
124
125 ethphy0: ethernet-phy@0 {
126 compatible = "ethernet
127 reg = <0>;
128 };
129 };
130 };
131
132 /* WiFi */
133 &usdhc1 {
134 #address-cells = <1>;
135 #size-cells = <0>;
136 assigned-clocks = <&clk IMX_SC_R_SDHC_
137 assigned-clock-rates = <200000000>;
138 pinctrl-names = "default";
139 pinctrl-0 = <&pinctrl_usdhc1>;
140 bus-width = <4>;
141 no-sd;
142 non-removable;
143 mmc-pwrseq = <&sdio_pwrseq>;
144 status = "okay";
145
146 brcmf: wifi@1 {
147 reg = <1>;
148 compatible = "brcm,bcm4329-fma
149 };
150 };
151
152 /* SD */
153 &usdhc2 {
154 assigned-clocks = <&clk IMX_SC_R_SDHC_
155 assigned-clock-rates = <200000000>;
156 pinctrl-names = "default";
157 pinctrl-0 = <&pinctrl_usdhc2>;
158 bus-width = <4>;
159 cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE
160 status = "okay";
161 };
162
163 &iomuxc {
164 pinctrl_fec1: fec1grp {
165 fsl,pins = <
166 IMX8QXP_ENET0_MDC_CONN
167 IMX8QXP_ENET0_MDIO_CON
168 IMX8QXP_ENET0_RGMII_TX
169 IMX8QXP_ENET0_RGMII_TX
170 IMX8QXP_ENET0_RGMII_TX
171 IMX8QXP_ENET0_RGMII_TX
172 IMX8QXP_ENET0_RGMII_TX
173 IMX8QXP_ENET0_RGMII_TX
174 IMX8QXP_ENET0_RGMII_RX
175 IMX8QXP_ENET0_RGMII_RX
176 IMX8QXP_ENET0_RGMII_RX
177 IMX8QXP_ENET0_RGMII_RX
178 IMX8QXP_ENET0_RGMII_RX
179 IMX8QXP_ENET0_RGMII_RX
180 >;
181 };
182
183 pinctrl_leds: ledsgrp {
184 fsl,pins = <
185 IMX8QXP_ESAI0_TX2_RX3_
186 IMX8QXP_ESAI0_TX3_RX2_
187 IMX8QXP_EMMC0_DATA7_LS
188 IMX8QXP_USDHC1_WP_LSIO
189 IMX8QXP_EMMC0_STROBE_L
190 IMX8QXP_EMMC0_RESET_B_
191 >;
192 };
193
194 pinctrl_lpuart0: lpuart0grp {
195 fsl,pins = <
196 IMX8QXP_UART0_RX_ADMA_
197 IMX8QXP_UART0_TX_ADMA_
198 IMX8QXP_FLEXCAN0_TX_AD
199 IMX8QXP_FLEXCAN0_RX_AD
200 >;
201 };
202
203 pinctrl_lpuart1: lpuart1grp {
204 fsl,pins = <
205 IMX8QXP_UART1_RX_ADMA_
206 IMX8QXP_UART1_TX_ADMA_
207 >;
208 };
209
210 pinctrl_lpuart2: lpuart2grp {
211 fsl,pins = <
212 IMX8QXP_UART2_RX_ADMA_
213 IMX8QXP_UART2_TX_ADMA_
214 >;
215 };
216
217 pinctrl_lpuart3: lpuart3grp {
218 fsl,pins = <
219 IMX8QXP_FLEXCAN2_RX_AD
220 IMX8QXP_FLEXCAN2_TX_AD
221 >;
222 };
223
224 pinctrl_usdhc1: usdhc1grp {
225 fsl,pins = <
226 IMX8QXP_EMMC0_CLK_CONN
227 IMX8QXP_EMMC0_CMD_CONN
228 IMX8QXP_EMMC0_DATA0_CO
229 IMX8QXP_EMMC0_DATA1_CO
230 IMX8QXP_EMMC0_DATA2_CO
231 IMX8QXP_EMMC0_DATA3_CO
232 >;
233 };
234
235 pinctrl_usdhc2: usdhc2grp {
236 fsl,pins = <
237 IMX8QXP_USDHC1_CLK_CON
238 IMX8QXP_USDHC1_CMD_CON
239 IMX8QXP_USDHC1_DATA0_C
240 IMX8QXP_USDHC1_DATA1_C
241 IMX8QXP_USDHC1_DATA2_C
242 IMX8QXP_USDHC1_DATA3_C
243 IMX8QXP_USDHC1_VSELECT
244 IMX8QXP_USDHC1_CD_B_LS
245 >;
246 };
247
248 pinctrl_wifi_reg_on: wifiregongrp {
249 fsl,pins = <
250 IMX8QXP_QSPI0B_SS1_B_L
251 >;
252 };
253 };
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