1 /* SPDX-License-Identifier: GPL-2.0-only OR MI 1 2 /* 3 * Copyright 2024 NXP 4 */ 5 6 #ifndef __CLOCK_IMX95_H 7 #define __CLOCK_IMX95_H 8 9 /* The index should match i.MX95 SCMI Firmware 10 #define IMX95_CLK_32K 1 11 #define IMX95_CLK_24M 2 12 #define IMX95_CLK_FRO 3 13 #define IMX95_CLK_SYSPLL1_VCO 4 14 #define IMX95_CLK_SYSPLL1_PFD0_UNGATED 5 15 #define IMX95_CLK_SYSPLL1_PFD0 6 16 #define IMX95_CLK_SYSPLL1_PFD0_DIV2 7 17 #define IMX95_CLK_SYSPLL1_PFD1_UNGATED 8 18 #define IMX95_CLK_SYSPLL1_PFD1 9 19 #define IMX95_CLK_SYSPLL1_PFD1_DIV2 10 20 #define IMX95_CLK_SYSPLL1_PFD2_UNGATED 11 21 #define IMX95_CLK_SYSPLL1_PFD2 12 22 #define IMX95_CLK_SYSPLL1_PFD2_DIV2 13 23 #define IMX95_CLK_AUDIOPLL1_VCO 14 24 #define IMX95_CLK_AUDIOPLL1 15 25 #define IMX95_CLK_AUDIOPLL2_VCO 16 26 #define IMX95_CLK_AUDIOPLL2 17 27 #define IMX95_CLK_VIDEOPLL1_VCO 18 28 #define IMX95_CLK_VIDEOPLL1 19 29 #define IMX95_CLK_RESERVED20 20 30 #define IMX95_CLK_RESERVED21 21 31 #define IMX95_CLK_RESERVED22 22 32 #define IMX95_CLK_RESERVED23 23 33 #define IMX95_CLK_ARMPLL_VCO 24 34 #define IMX95_CLK_ARMPLL_PFD0_UNGATED 25 35 #define IMX95_CLK_ARMPLL_PFD0 26 36 #define IMX95_CLK_ARMPLL_PFD1_UNGATED 27 37 #define IMX95_CLK_ARMPLL_PFD1 28 38 #define IMX95_CLK_ARMPLL_PFD2_UNGATED 29 39 #define IMX95_CLK_ARMPLL_PFD2 30 40 #define IMX95_CLK_ARMPLL_PFD3_UNGATED 31 41 #define IMX95_CLK_ARMPLL_PFD3 32 42 #define IMX95_CLK_DRAMPLL_VCO 33 43 #define IMX95_CLK_DRAMPLL 34 44 #define IMX95_CLK_HSIOPLL_VCO 35 45 #define IMX95_CLK_HSIOPLL 36 46 #define IMX95_CLK_LDBPLL_VCO 37 47 #define IMX95_CLK_LDBPLL 38 48 #define IMX95_CLK_EXT1 39 49 #define IMX95_CLK_EXT2 40 50 51 #define IMX95_CCM_NUM_CLK_SRC 41 52 53 #define IMX95_CLK_ADC (IM 54 #define IMX95_CLK_TMU (IM 55 #define IMX95_CLK_BUSAON (IM 56 #define IMX95_CLK_CAN1 (IM 57 #define IMX95_CLK_I3C1 (IM 58 #define IMX95_CLK_I3C1SLOW (IM 59 #define IMX95_CLK_LPI2C1 (IM 60 #define IMX95_CLK_LPI2C2 (IM 61 #define IMX95_CLK_LPSPI1 (IM 62 #define IMX95_CLK_LPSPI2 (IM 63 #define IMX95_CLK_LPTMR1 (IM 64 #define IMX95_CLK_LPUART1 (IM 65 #define IMX95_CLK_LPUART2 (IM 66 #define IMX95_CLK_M33 (IM 67 #define IMX95_CLK_M33SYSTICK (IM 68 #define IMX95_CLK_MQS1 (IM 69 #define IMX95_CLK_PDM (IM 70 #define IMX95_CLK_SAI1 (IM 71 #define IMX95_CLK_SENTINEL (IM 72 #define IMX95_CLK_TPM2 (IM 73 #define IMX95_CLK_TSTMR1 (IM 74 #define IMX95_CLK_CAMAPB (IM 75 #define IMX95_CLK_CAMAXI (IM 76 #define IMX95_CLK_CAMCM0 (IM 77 #define IMX95_CLK_CAMISI (IM 78 #define IMX95_CLK_MIPIPHYCFG (IM 79 #define IMX95_CLK_MIPIPHYPLLBYPASS (IM 80 #define IMX95_CLK_MIPIPHYPLLREF (IM 81 #define IMX95_CLK_MIPITESTBYTE (IM 82 #define IMX95_CLK_A55 (IM 83 #define IMX95_CLK_A55MTRBUS (IM 84 #define IMX95_CLK_A55PERIPH (IM 85 #define IMX95_CLK_DRAMALT (IM 86 #define IMX95_CLK_DRAMAPB (IM 87 #define IMX95_CLK_DISPAPB (IM 88 #define IMX95_CLK_DISPAXI (IM 89 #define IMX95_CLK_DISPDP (IM 90 #define IMX95_CLK_DISPOCRAM (IM 91 #define IMX95_CLK_DISPUSB31 (IM 92 #define IMX95_CLK_DISP1PIX (IM 93 #define IMX95_CLK_DISP2PIX (IM 94 #define IMX95_CLK_DISP3PIX (IM 95 #define IMX95_CLK_GPUAPB (IM 96 #define IMX95_CLK_GPU (IM 97 #define IMX95_CLK_HSIOACSCAN480M (IM 98 #define IMX95_CLK_HSIOACSCAN80M (IM 99 #define IMX95_CLK_HSIO (IM 100 #define IMX95_CLK_HSIOPCIEAUX (IM 101 #define IMX95_CLK_HSIOPCIETEST160M (IM 102 #define IMX95_CLK_HSIOPCIETEST400M (IM 103 #define IMX95_CLK_HSIOPCIETEST500M (IM 104 #define IMX95_CLK_HSIOUSBTEST50M (IM 105 #define IMX95_CLK_HSIOUSBTEST60M (IM 106 #define IMX95_CLK_BUSM7 (IM 107 #define IMX95_CLK_M7 (IM 108 #define IMX95_CLK_M7SYSTICK (IM 109 #define IMX95_CLK_BUSNETCMIX (IM 110 #define IMX95_CLK_ENET (IM 111 #define IMX95_CLK_ENETPHYTEST200M (IM 112 #define IMX95_CLK_ENETPHYTEST500M (IM 113 #define IMX95_CLK_ENETPHYTEST667M (IM 114 #define IMX95_CLK_ENETREF (IM 115 #define IMX95_CLK_ENETTIMER1 (IM 116 #define IMX95_CLK_MQS2 (IM 117 #define IMX95_CLK_SAI2 (IM 118 #define IMX95_CLK_NOCAPB (IM 119 #define IMX95_CLK_NOC (IM 120 #define IMX95_CLK_NPUAPB (IM 121 #define IMX95_CLK_NPU (IM 122 #define IMX95_CLK_CCMCKO1 (IM 123 #define IMX95_CLK_CCMCKO2 (IM 124 #define IMX95_CLK_CCMCKO3 (IM 125 #define IMX95_CLK_CCMCKO4 (IM 126 #define IMX95_CLK_VPUAPB (IM 127 #define IMX95_CLK_VPU (IM 128 #define IMX95_CLK_VPUDSP (IM 129 #define IMX95_CLK_VPUJPEG (IM 130 #define IMX95_CLK_AUDIOXCVR (IM 131 #define IMX95_CLK_BUSWAKEUP (IM 132 #define IMX95_CLK_CAN2 (IM 133 #define IMX95_CLK_CAN3 (IM 134 #define IMX95_CLK_CAN4 (IM 135 #define IMX95_CLK_CAN5 (IM 136 #define IMX95_CLK_FLEXIO1 (IM 137 #define IMX95_CLK_FLEXIO2 (IM 138 #define IMX95_CLK_FLEXSPI1 (IM 139 #define IMX95_CLK_I3C2 (IM 140 #define IMX95_CLK_I3C2SLOW (IM 141 #define IMX95_CLK_LPI2C3 (IM 142 #define IMX95_CLK_LPI2C4 (IM 143 #define IMX95_CLK_LPI2C5 (IM 144 #define IMX95_CLK_LPI2C6 (IM 145 #define IMX95_CLK_LPI2C7 (IM 146 #define IMX95_CLK_LPI2C8 (IM 147 #define IMX95_CLK_LPSPI3 (IM 148 #define IMX95_CLK_LPSPI4 (IM 149 #define IMX95_CLK_LPSPI5 (IM 150 #define IMX95_CLK_LPSPI6 (IM 151 #define IMX95_CLK_LPSPI7 (IM 152 #define IMX95_CLK_LPSPI8 (IM 153 #define IMX95_CLK_LPTMR2 (IM 154 #define IMX95_CLK_LPUART3 (IM 155 #define IMX95_CLK_LPUART4 (IM 156 #define IMX95_CLK_LPUART5 (IM 157 #define IMX95_CLK_LPUART6 (IM 158 #define IMX95_CLK_LPUART7 (IM 159 #define IMX95_CLK_LPUART8 (IM 160 #define IMX95_CLK_SAI3 (IM 161 #define IMX95_CLK_SAI4 (IM 162 #define IMX95_CLK_SAI5 (IM 163 #define IMX95_CLK_SPDIF (IM 164 #define IMX95_CLK_SWOTRACE (IM 165 #define IMX95_CLK_TPM4 (IM 166 #define IMX95_CLK_TPM5 (IM 167 #define IMX95_CLK_TPM6 (IM 168 #define IMX95_CLK_TSTMR2 (IM 169 #define IMX95_CLK_USBPHYBURUNIN (IM 170 #define IMX95_CLK_USDHC1 (IM 171 #define IMX95_CLK_USDHC2 (IM 172 #define IMX95_CLK_USDHC3 (IM 173 #define IMX95_CLK_V2XPK (IM 174 #define IMX95_CLK_WAKEUPAXI (IM 175 #define IMX95_CLK_XSPISLVROOT (IM 176 #define IMX95_CLK_SEL_EXT (IM 177 #define IMX95_CLK_SEL_A55C0 (IM 178 #define IMX95_CLK_SEL_A55C1 (IM 179 #define IMX95_CLK_SEL_A55C2 (IM 180 #define IMX95_CLK_SEL_A55C3 (IM 181 #define IMX95_CLK_SEL_A55C4 (IM 182 #define IMX95_CLK_SEL_A55C5 (IM 183 #define IMX95_CLK_SEL_A55P (IM 184 #define IMX95_CLK_SEL_DRAM (IM 185 #define IMX95_CLK_SEL_TEMPSENSE (IM 186 187 #endif /* __CLOCK_IMX95_H */ 188
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