1 // SPDX-License-Identifier: GPL-2.0-or-later O
2 /*
3 * NXP S32G2 SoC family
4 *
5 * Copyright (c) 2021 SUSE LLC
6 * Copyright 2017-2021, 2024 NXP
7 */
8
9 #include <dt-bindings/interrupt-controller/arm
10
11 / {
12 compatible = "nxp,s32g2";
13 interrupt-parent = <&gic>;
14 #address-cells = <2>;
15 #size-cells = <2>;
16
17 reserved-memory {
18 #address-cells = <2>;
19 #size-cells = <2>;
20 ranges;
21
22 scmi_buf: shm@d0000000 {
23 compatible = "arm,scmi
24 reg = <0x0 0xd0000000
25 no-map;
26 };
27 };
28
29 cpus {
30 #address-cells = <1>;
31 #size-cells = <0>;
32
33 cpu0: cpu@0 {
34 device_type = "cpu";
35 compatible = "arm,cort
36 reg = <0x0>;
37 enable-method = "psci"
38 next-level-cache = <&c
39 };
40
41 cpu1: cpu@1 {
42 device_type = "cpu";
43 compatible = "arm,cort
44 reg = <0x1>;
45 enable-method = "psci"
46 next-level-cache = <&c
47 };
48
49 cpu2: cpu@100 {
50 device_type = "cpu";
51 compatible = "arm,cort
52 reg = <0x100>;
53 enable-method = "psci"
54 next-level-cache = <&c
55 };
56
57 cpu3: cpu@101 {
58 device_type = "cpu";
59 compatible = "arm,cort
60 reg = <0x101>;
61 enable-method = "psci"
62 next-level-cache = <&c
63 };
64
65 cluster0_l2: l2-cache0 {
66 compatible = "cache";
67 cache-level = <2>;
68 cache-unified;
69 };
70
71 cluster1_l2: l2-cache1 {
72 compatible = "cache";
73 cache-level = <2>;
74 cache-unified;
75 };
76 };
77
78 pmu {
79 compatible = "arm,cortex-a53-p
80 interrupts = <GIC_PPI 7 IRQ_TY
81 };
82
83 timer {
84 compatible = "arm,armv8-timer"
85 interrupts = <GIC_PPI 13 IRQ_T
86 <GIC_PPI 14 IRQ_T
87 <GIC_PPI 11 IRQ_T
88 <GIC_PPI 10 IRQ_T
89 };
90
91 firmware {
92 scmi {
93 compatible = "arm,scmi
94 arm,smc-id = <0xc20000
95 #address-cells = <1>;
96 #size-cells = <0>;
97 shmem = <&scmi_buf>;
98
99 clks: protocol@14 {
100 reg = <0x14>;
101 #clock-cells =
102 };
103 };
104
105 psci {
106 compatible = "arm,psci
107 method = "smc";
108 };
109 };
110
111 soc@0 {
112 compatible = "simple-bus";
113 #address-cells = <1>;
114 #size-cells = <1>;
115 ranges = <0 0 0 0x80000000>;
116
117 pinctrl: pinctrl@4009c240 {
118 compatible = "nxp,s32g
119 /* MSCR0-MSCR1
120 reg = <0x4009c240 0x19
121 /* MSCR112-MSC
122 <0x44010400 0x2c
123 /* MSCR144-MSC
124 <0x44010480 0xbc
125 /* IMCR0-IMCR8
126 <0x4009ca40 0x15
127 /* IMCR119-IMC
128 <0x44010c1c 0x45
129 /* IMCR430-IMC
130 <0x440110f8 0x10
131
132 jtag_pins: jtag-pins {
133 jtag-grp0 {
134 pinmux
135 input-
136 bias-p
137 slew-r
138 };
139
140 jtag-grp1 {
141 pinmux
142 slew-r
143 };
144
145 jtag-grp2 {
146 pinmux
147 input-
148 bias-p
149 slew-r
150 };
151
152 jtag-grp3 {
153 pinmux
154
155
156 };
157
158 jtag-grp4 {
159 pinmux
160 input-
161 bias-p
162 slew-r
163 };
164 };
165 };
166
167 uart0: serial@401c8000 {
168 compatible = "nxp,s32g
169 "fsl,s32v
170 reg = <0x401c8000 0x30
171 interrupts = <GIC_SPI
172 status = "disabled";
173 };
174
175 uart1: serial@401cc000 {
176 compatible = "nxp,s32g
177 "fsl,s32v
178 reg = <0x401cc000 0x30
179 interrupts = <GIC_SPI
180 status = "disabled";
181 };
182
183 uart2: serial@402bc000 {
184 compatible = "nxp,s32g
185 "fsl,s32v
186 reg = <0x402bc000 0x30
187 interrupts = <GIC_SPI
188 status = "disabled";
189 };
190
191 usdhc0: mmc@402f0000 {
192 compatible = "nxp,s32g
193 reg = <0x402f0000 0x10
194 interrupts = <GIC_SPI
195 clocks = <&clks 32>, <
196 clock-names = "ipg", "
197 bus-width = <8>;
198 status = "disabled";
199 };
200
201 gic: interrupt-controller@5080
202 compatible = "arm,gic-
203 reg = <0x50800000 0x10
204 <0x50880000 0x80
205 <0x50400000 0x20
206 <0x50410000 0x20
207 <0x50420000 0x20
208 interrupts = <GIC_PPI
209 interrupt-controller;
210 #interrupt-cells = <3>
211 };
212 };
213 };
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