1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Device Tree Include file for Marvell Armada
4 *
5 * Copyright (C) 2016 Marvell
6 *
7 * Gregory CLEMENT <gregory.clement@free-electr
8 *
9 */
10
11 #include <dt-bindings/interrupt-controller/arm
12
13 / {
14 model = "Marvell Armada 37xx SoC";
15 compatible = "marvell,armada3700";
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
19
20 aliases {
21 serial0 = &uart0;
22 serial1 = &uart1;
23 };
24
25 reserved-memory {
26 #address-cells = <2>;
27 #size-cells = <2>;
28 ranges;
29
30 /*
31 * The PSCI firmware region de
32 * and should be updated by th
33 */
34 psci-area@4000000 {
35 reg = <0 0x4000000 0 0
36 no-map;
37 };
38
39 tee@4400000 {
40 reg = <0 0x4400000 0 0
41 no-map;
42 };
43 };
44
45 cpus {
46 #address-cells = <1>;
47 #size-cells = <0>;
48 cpu0: cpu@0 {
49 device_type = "cpu";
50 compatible = "arm,cort
51 reg = <0>;
52 clocks = <&nb_periph_c
53 enable-method = "psci"
54 };
55 };
56
57 psci {
58 compatible = "arm,psci-0.2";
59 method = "smc";
60 };
61
62 timer {
63 compatible = "arm,armv8-timer"
64 interrupts = <GIC_PPI 13 IRQ_T
65 <GIC_PPI 14 IRQ_T
66 <GIC_PPI 11 IRQ_T
67 <GIC_PPI 10 IRQ_T
68 };
69
70 pmu {
71 compatible = "arm,cortex-a53-p
72 interrupts = <GIC_PPI 7 IRQ_TY
73 };
74
75 soc {
76 compatible = "simple-bus";
77 #address-cells = <2>;
78 #size-cells = <2>;
79 ranges;
80
81 internal-regs@d0000000 {
82 #address-cells = <1>;
83 #size-cells = <1>;
84 compatible = "simple-b
85 /* 32M internal regist
86 ranges = <0x0 0x0 0xd0
87
88 wdt: watchdog@8300 {
89 compatible = "
90 reg = <0x8300
91 marvell,system
92 clocks = <&xta
93 };
94
95 cpu_misc: system-contr
96 compatible = "
97 "
98 reg = <0xd000
99 };
100
101 spi0: spi@10600 {
102 compatible = "
103 #address-cells
104 #size-cells =
105 reg = <0x10600
106 clocks = <&nb_
107 interrupts = <
108 num-cs = <4>;
109 status = "disa
110 };
111
112 i2c0: i2c@11000 {
113 compatible = "
114 reg = <0x11000
115 #address-cells
116 #size-cells =
117 clocks = <&nb_
118 interrupts = <
119 mrvl,i2c-fast-
120 status = "disa
121 };
122
123 i2c1: i2c@11080 {
124 compatible = "
125 reg = <0x11080
126 #address-cells
127 #size-cells =
128 clocks = <&nb_
129 interrupts = <
130 mrvl,i2c-fast-
131 status = "disa
132 };
133
134 avs: avs@11500 {
135 compatible = "
136 "
137 reg = <0x11500
138 };
139
140 uartclk: clock-control
141 compatible = "
142 reg = <0x12010
143 clocks = <&tbg
144 <&tbg
145 clock-names =
146
147 #clock-cells =
148 };
149
150 uart0: serial@12000 {
151 compatible = "
152 reg = <0x12000
153 clocks = <&uar
154 interrupts =
155 <GIC_SPI 11 IR
156 <GIC_SPI 12 IR
157 <GIC_SPI 13 IR
158 interrupt-name
159 status = "disa
160 };
161
162 uart1: serial@12200 {
163 compatible = "
164 reg = <0x12200
165 clocks = <&uar
166 interrupts =
167 <GIC_SPI 30 IR
168 <GIC_SPI 31 IR
169 interrupt-name
170 status = "disa
171 };
172
173 nb_periph_clk: nb-peri
174 compatible = "
175 "
176 reg = <0x13000
177 clocks = <&tbg
178 <&tbg 3>, <&xt
179 #clock-cells =
180 };
181
182 sb_periph_clk: sb-peri
183 compatible = "
184 reg = <0x18000
185 clocks = <&tbg
186 <&tbg 3>, <&xt
187 #clock-cells =
188 };
189
190 tbg: tbg@13200 {
191 compatible = "
192 reg = <0x13200
193 clocks = <&xta
194 #clock-cells =
195 };
196
197 pinctrl_nb: pinctrl@13
198 compatible = "
199 "
200 reg = <0x13800
201 /* MPP1[19:0]
202 gpionb: gpio {
203 #gpio-
204 gpio-r
205 gpio-c
206 interr
207 #inter
208 interr
209 <GIC_S
210 <GIC_S
211 <GIC_S
212 <GIC_S
213 <GIC_S
214 <GIC_S
215 <GIC_S
216 <GIC_S
217 <GIC_S
218 <GIC_S
219 <GIC_S
220 <GIC_S
221 };
222
223 xtalclk: xtal-
224 compat
225 clock-
226 #clock
227 };
228
229 spi_quad_pins:
230 groups
231 functi
232 };
233
234 spi_cs1_pins:
235 groups
236 functi
237 };
238
239 i2c1_pins: i2c
240 groups
241 functi
242 };
243
244 i2c2_pins: i2c
245 groups
246 functi
247 };
248
249 uart1_pins: ua
250 groups
251 functi
252 };
253
254 uart2_pins: ua
255 groups
256 functi
257 };
258
259 mmc_pins: mmc-
260 groups
261 functi
262 };
263 };
264
265 nb_pm: syscon@14000 {
266 compatible = "
267 "
268 reg = <0x14000
269 };
270
271 comphy: phy@18300 {
272 compatible = "
273 reg = <0x18300
274 <0x1F000
275 <0x5C000
276 <0xe0178
277 reg-names = "c
278 "l
279 "l
280 "l
281 #address-cells
282 #size-cells =
283 clocks = <&xta
284 clock-names =
285
286 comphy0: phy@0
287 reg =
288 #phy-c
289 };
290
291 comphy1: phy@1
292 reg =
293 #phy-c
294 };
295
296 comphy2: phy@2
297 reg =
298 #phy-c
299 };
300 };
301
302 pinctrl_sb: pinctrl@18
303 compatible = "
304 "
305 reg = <0x18800
306 /* MPP2[23:0]
307 gpiosb: gpio {
308 #gpio-
309 gpio-r
310 gpio-c
311 interr
312 #inter
313 interr
314 <GIC_S
315 <GIC_S
316 <GIC_S
317 <GIC_S
318 <GIC_S
319 };
320
321 rgmii_pins: mi
322 groups
323 functi
324 };
325
326 smi_pins: smi-
327 groups
328 functi
329 };
330
331 sdio_pins: sdi
332 groups
333 functi
334 };
335
336 pcie_reset_pin
337 groups
338 functi
339 };
340
341 pcie_clkreq_pi
342 groups
343 functi
344 };
345 };
346
347 eth0: ethernet@30000 {
348 compatible
349 reg = <0x30
350 interrupts
351 clocks = <&
352 status = "d
353 };
354
355 mdio: mdio@32004 {
356 #address-cells
357 #size-cells =
358 compatible = "
359 reg = <0x32004
360 };
361
362 eth1: ethernet@40000 {
363 compatible = "
364 reg = <0x40000
365 interrupts = <
366 clocks = <&sb_
367 status = "disa
368 };
369
370 usb3: usb@58000 {
371 compatible = "
372 "generic-xhci"
373 reg = <0x58000
374 marvell,usb-mi
375 interrupts = <
376 clocks = <&sb_
377 phys = <&comph
378 phy-names = "u
379 status = "disa
380 };
381
382 usb2_utmi_otg_phy: phy
383 compatible = "
384 reg = <0x5d000
385 marvell,usb-mi
386 #phy-cells = <
387 };
388
389 usb32_syscon: system-c
390 compatible = "
391 "syscon";
392 reg = <0x5d800
393 };
394
395 usb2: usb@5e000 {
396 compatible = "
397 reg = <0x5e000
398 marvell,usb-mi
399 interrupts = <
400 phys = <&usb2_
401 phy-names = "u
402 status = "disa
403 };
404
405 usb2_utmi_host_phy: ph
406 compatible = "
407 reg = <0x5f000
408 marvell,usb-mi
409 #phy-cells = <
410 };
411
412 usb2_syscon: system-co
413 compatible = "
414 "syscon";
415 reg = <0x5f800
416 };
417
418 xor@60900 {
419 compatible = "
420 reg = <0x60900
421 <0x60b00
422
423 xor10 {
424 interr
425 };
426 xor11 {
427 interr
428 };
429 };
430
431 crypto: crypto@90000 {
432 compatible = "
433 reg = <0x90000
434 interrupts = <
435 <
436 <
437 <
438 <
439 <
440 interrupt-name
441
442 clocks = <&nb_
443 };
444
445 rwtm: mailbox@b0000 {
446 compatible = "
447 reg = <0xb0000
448 interrupts = <
449 #mbox-cells =
450 };
451
452 sdhci1: mmc@d0000 {
453 compatible = "
454 "
455 reg = <0xd0000
456 <0x1e808
457 interrupts = <
458 clocks = <&nb_
459 clock-names =
460 status = "disa
461 };
462
463 sdhci0: mmc@d8000 {
464 compatible = "
465 "
466 reg = <0xd8000
467 <0x17808
468 interrupts = <
469 clocks = <&nb_
470 clock-names =
471 status = "disa
472 };
473
474 sata: sata@e0000 {
475 compatible = "
476 reg = <0xe0000
477 interrupts = <
478 clocks = <&nb_
479 phys = <&comph
480 phy-names = "s
481 status = "disa
482 };
483
484 gic: interrupt-control
485 compatible = "
486 #interrupt-cel
487 interrupt-cont
488 reg = <0x1d000
489 <0x1d400
490 <0x1d800
491 <0x1d900
492 <0x1da00
493 interrupts = <
494 };
495 };
496
497 pcie0: pcie@d0070000 {
498 compatible = "marvell,
499 device_type = "pci";
500 status = "disabled";
501 reg = <0 0xd0070000 0
502 #address-cells = <3>;
503 #size-cells = <2>;
504 bus-range = <0x00 0xff
505 interrupts = <GIC_SPI
506 #interrupt-cells = <1>
507 clocks = <&sb_periph_c
508 msi-parent = <&pcie0>;
509 msi-controller;
510 /*
511 * The 128 MiB address
512 * dedicated for PCIe
513 * with size a power o
514 * IO at the end and t
515 * (totaling 127 MiB)
516 */
517 ranges = <0x82000000 0
518 0x81000000 0
519 interrupt-map-mask = <
520 interrupt-map = <0 0 0
521 <0 0 0
522 <0 0 0
523 <0 0 0
524 max-link-speed = <2>;
525 phys = <&comphy1 0>;
526 pcie_intc: interrupt-c
527 interrupt-cont
528 #interrupt-cel
529 };
530 };
531 };
532
533 firmware {
534 armada-3700-rwtm {
535 compatible = "marvell,
536 mboxes = <&rwtm 0>;
537 status = "okay";
538 };
539 };
540 };
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