1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2020 MediaTek Inc.
4 * Copyright (c) 2020 BayLibre, SAS.
5 * Author: Fabien Parent <fparent@baylibre.com>
6 */
7
8 #include <dt-bindings/clock/mt8167-clk.h>
9 #include <dt-bindings/memory/mt8167-larb-port.
10 #include <dt-bindings/power/mt8167-power.h>
11
12 #include "mt8167-pinfunc.h"
13
14 #include "mt8516.dtsi"
15
16 / {
17 compatible = "mediatek,mt8167";
18
19 soc {
20 topckgen: topckgen@10000000 {
21 compatible = "mediatek
22 reg = <0 0x10000000 0
23 #clock-cells = <1>;
24 };
25
26 infracfg: infracfg@10001000 {
27 compatible = "mediatek
28 reg = <0 0x10001000 0
29 #clock-cells = <1>;
30 };
31
32 apmixedsys: apmixedsys@1001800
33 compatible = "mediatek
34 reg = <0 0x10018000 0
35 #clock-cells = <1>;
36 };
37
38 scpsys: syscon@10006000 {
39 compatible = "mediatek
40 reg = <0 0x10006000 0
41
42 spm: power-controller
43 compatible = "
44 #address-cells
45 #size-cells =
46 #power-domain-
47
48 /* power domai
49 power-domain@M
50 reg =
51 clocks
52 clock-
53 #power
54 mediat
55 };
56
57 power-domain@M
58 reg =
59 clocks
60
61 clock-
62 #power
63 };
64
65 power-domain@M
66 reg =
67 clocks
68 clock-
69 #power
70 };
71
72 power-domain@M
73 reg =
74 clocks
75
76 clock-
77 #addre
78 #size-
79 #power
80 mediat
81
82 power-
83
84
85
86
87
88
89
90
91
92
93 };
94 };
95
96 power-domain@M
97 reg =
98 #power
99 mediat
100 };
101 };
102 };
103
104 imgsys: syscon@15000000 {
105 compatible = "mediatek
106 reg = <0 0x15000000 0
107 #clock-cells = <1>;
108 };
109
110 vdecsys: syscon@16000000 {
111 compatible = "mediatek
112 reg = <0 0x16000000 0
113 #clock-cells = <1>;
114 };
115
116 pio: pinctrl@1000b000 {
117 compatible = "mediatek
118 reg = <0 0x1000b000 0
119 mediatek,pctl-regmap =
120 gpio-controller;
121 #gpio-cells = <2>;
122 interrupt-controller;
123 #interrupt-cells = <2>
124 interrupts = <GIC_SPI
125 };
126
127 mmsys: syscon@14000000 {
128 compatible = "mediatek
129 reg = <0 0x14000000 0
130 #clock-cells = <1>;
131 };
132
133 smi_common: smi@14017000 {
134 compatible = "mediatek
135 reg = <0 0x14017000 0
136 clocks = <&mmsys CLK_M
137 <&mmsys CLK_M
138 clock-names = "apb", "
139 power-domains = <&spm
140 };
141
142 larb0: larb@14016000 {
143 compatible = "mediatek
144 reg = <0 0x14016000 0
145 mediatek,smi = <&smi_c
146 clocks = <&mmsys CLK_M
147 <&mmsys CLK_M
148 clock-names = "apb", "
149 power-domains = <&spm
150 };
151
152 larb1: larb@15001000 {
153 compatible = "mediatek
154 reg = <0 0x15001000 0
155 mediatek,smi = <&smi_c
156 clocks = <&imgsys CLK_
157 <&imgsys CLK_
158 clock-names = "apb", "
159 power-domains = <&spm
160 };
161
162 larb2: larb@16010000 {
163 compatible = "mediatek
164 reg = <0 0x16010000 0
165 mediatek,smi = <&smi_c
166 clocks = <&vdecsys CLK
167 <&vdecsys CLK
168 clock-names = "apb", "
169 power-domains = <&spm
170 };
171
172 iommu: m4u@10203000 {
173 compatible = "mediatek
174 reg = <0 0x10203000 0
175 mediatek,larbs = <&lar
176 interrupts = <GIC_SPI
177 #iommu-cells = <1>;
178 };
179 };
180 };
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