1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2014 MediaTek Inc.
4 * Author: Eddie Huang <eddie.huang@mediatek.co
5 */
6
7 #include <dt-bindings/clock/mt8173-clk.h>
8 #include <dt-bindings/interrupt-controller/irq
9 #include <dt-bindings/interrupt-controller/arm
10 #include <dt-bindings/memory/mt8173-larb-port.
11 #include <dt-bindings/phy/phy.h>
12 #include <dt-bindings/power/mt8173-power.h>
13 #include <dt-bindings/reset/mt8173-resets.h>
14 #include <dt-bindings/gce/mt8173-gce.h>
15 #include <dt-bindings/thermal/thermal.h>
16 #include "mt8173-pinfunc.h"
17
18 / {
19 compatible = "mediatek,mt8173";
20 interrupt-parent = <&sysirq>;
21 #address-cells = <2>;
22 #size-cells = <2>;
23
24 aliases {
25 ovl0 = &ovl0;
26 ovl1 = &ovl1;
27 rdma0 = &rdma0;
28 rdma1 = &rdma1;
29 rdma2 = &rdma2;
30 wdma0 = &wdma0;
31 wdma1 = &wdma1;
32 color0 = &color0;
33 color1 = &color1;
34 split0 = &split0;
35 split1 = &split1;
36 dpi0 = &dpi0;
37 dsi0 = &dsi0;
38 dsi1 = &dsi1;
39 mdp-rdma0 = &mdp_rdma0;
40 mdp-rdma1 = &mdp_rdma1;
41 mdp-rsz0 = &mdp_rsz0;
42 mdp-rsz1 = &mdp_rsz1;
43 mdp-rsz2 = &mdp_rsz2;
44 mdp-wdma0 = &mdp_wdma0;
45 mdp-wrot0 = &mdp_wrot0;
46 mdp-wrot1 = &mdp_wrot1;
47 serial0 = &uart0;
48 serial1 = &uart1;
49 serial2 = &uart2;
50 serial3 = &uart3;
51 };
52
53 cluster0_opp: opp-table-0 {
54 compatible = "operating-points
55 opp-shared;
56 opp-507000000 {
57 opp-hz = /bits/ 64 <50
58 opp-microvolt = <85900
59 };
60 opp-702000000 {
61 opp-hz = /bits/ 64 <70
62 opp-microvolt = <90800
63 };
64 opp-1001000000 {
65 opp-hz = /bits/ 64 <10
66 opp-microvolt = <98300
67 };
68 opp-1105000000 {
69 opp-hz = /bits/ 64 <11
70 opp-microvolt = <10090
71 };
72 opp-1209000000 {
73 opp-hz = /bits/ 64 <12
74 opp-microvolt = <10340
75 };
76 opp-1300000000 {
77 opp-hz = /bits/ 64 <13
78 opp-microvolt = <10570
79 };
80 opp-1508000000 {
81 opp-hz = /bits/ 64 <15
82 opp-microvolt = <11090
83 };
84 opp-1703000000 {
85 opp-hz = /bits/ 64 <17
86 opp-microvolt = <11250
87 };
88 };
89
90 cluster1_opp: opp-table-1 {
91 compatible = "operating-points
92 opp-shared;
93 opp-507000000 {
94 opp-hz = /bits/ 64 <50
95 opp-microvolt = <82800
96 };
97 opp-702000000 {
98 opp-hz = /bits/ 64 <70
99 opp-microvolt = <86700
100 };
101 opp-1001000000 {
102 opp-hz = /bits/ 64 <10
103 opp-microvolt = <92700
104 };
105 opp-1209000000 {
106 opp-hz = /bits/ 64 <12
107 opp-microvolt = <96800
108 };
109 opp-1404000000 {
110 opp-hz = /bits/ 64 <14
111 opp-microvolt = <10070
112 };
113 opp-1612000000 {
114 opp-hz = /bits/ 64 <16
115 opp-microvolt = <10490
116 };
117 opp-1807000000 {
118 opp-hz = /bits/ 64 <18
119 opp-microvolt = <10890
120 };
121 opp-2106000000 {
122 opp-hz = /bits/ 64 <21
123 opp-microvolt = <11250
124 };
125 };
126
127 cpus {
128 #address-cells = <1>;
129 #size-cells = <0>;
130
131 cpu-map {
132 cluster0 {
133 core0 {
134 cpu =
135 };
136 core1 {
137 cpu =
138 };
139 };
140
141 cluster1 {
142 core0 {
143 cpu =
144 };
145 core1 {
146 cpu =
147 };
148 };
149 };
150
151 cpu0: cpu@0 {
152 device_type = "cpu";
153 compatible = "arm,cort
154 reg = <0x000>;
155 enable-method = "psci"
156 cpu-idle-states = <&CP
157 #cooling-cells = <2>;
158 dynamic-power-coeffici
159 clocks = <&infracfg CL
160 <&apmixedsys
161 clock-names = "cpu", "
162 operating-points-v2 =
163 capacity-dmips-mhz = <
164 };
165
166 cpu1: cpu@1 {
167 device_type = "cpu";
168 compatible = "arm,cort
169 reg = <0x001>;
170 enable-method = "psci"
171 cpu-idle-states = <&CP
172 #cooling-cells = <2>;
173 dynamic-power-coeffici
174 clocks = <&infracfg CL
175 <&apmixedsys
176 clock-names = "cpu", "
177 operating-points-v2 =
178 capacity-dmips-mhz = <
179 };
180
181 cpu2: cpu@100 {
182 device_type = "cpu";
183 compatible = "arm,cort
184 reg = <0x100>;
185 enable-method = "psci"
186 cpu-idle-states = <&CP
187 #cooling-cells = <2>;
188 dynamic-power-coeffici
189 clocks = <&infracfg CL
190 <&apmixedsys
191 clock-names = "cpu", "
192 operating-points-v2 =
193 capacity-dmips-mhz = <
194 };
195
196 cpu3: cpu@101 {
197 device_type = "cpu";
198 compatible = "arm,cort
199 reg = <0x101>;
200 enable-method = "psci"
201 cpu-idle-states = <&CP
202 #cooling-cells = <2>;
203 dynamic-power-coeffici
204 clocks = <&infracfg CL
205 <&apmixedsys
206 clock-names = "cpu", "
207 operating-points-v2 =
208 capacity-dmips-mhz = <
209 };
210
211 idle-states {
212 entry-method = "psci";
213
214 CPU_SLEEP_0: cpu-sleep
215 compatible = "
216 local-timer-st
217 entry-latency-
218 exit-latency-u
219 min-residency-
220 arm,psci-suspe
221 };
222 };
223 };
224
225 pmu-a53 {
226 compatible = "arm,cortex-a53-p
227 interrupts = <GIC_SPI 8 IRQ_TY
228 <GIC_SPI 9 IRQ_TY
229 interrupt-affinity = <&cpu0>,
230 };
231
232 pmu-a72 {
233 compatible = "arm,cortex-a72-p
234 interrupts = <GIC_SPI 12 IRQ_T
235 <GIC_SPI 13 IRQ_T
236 interrupt-affinity = <&cpu2>,
237 };
238
239 psci {
240 compatible = "arm,psci-1.0", "
241 method = "smc";
242 cpu_suspend = <0x84000001>;
243 cpu_off = <0x84000002>;
244 cpu_on = <0x84000003>;
245 };
246
247 clk26m: oscillator0 {
248 compatible = "fixed-clock";
249 #clock-cells = <0>;
250 clock-frequency = <26000000>;
251 clock-output-names = "clk26m";
252 };
253
254 clk32k: oscillator1 {
255 compatible = "fixed-clock";
256 #clock-cells = <0>;
257 clock-frequency = <32000>;
258 clock-output-names = "clk32k";
259 };
260
261 cpum_ck: oscillator2 {
262 compatible = "fixed-clock";
263 #clock-cells = <0>;
264 clock-frequency = <0>;
265 clock-output-names = "cpum_ck"
266 };
267
268 thermal-zones {
269 cpu_thermal: cpu-thermal {
270 polling-delay-passive
271 polling-delay = <1000>
272
273 thermal-sensors = <&th
274 sustainable-power = <1
275
276 trips {
277 threshold: tri
278 temper
279 hyster
280 type =
281 };
282
283 target: trip-p
284 temper
285 hyster
286 type =
287 };
288
289 cpu_crit: cpu-
290 temper
291 hyster
292 type =
293 };
294 };
295
296 cooling-maps {
297 map0 {
298 trip =
299 coolin
300
301
302
303 contri
304 };
305 map1 {
306 trip =
307 coolin
308
309
310
311 contri
312 };
313 };
314 };
315 };
316
317 reserved-memory {
318 #address-cells = <2>;
319 #size-cells = <2>;
320 ranges;
321 vpu_dma_reserved: vpu-dma-mem@
322 compatible = "shared-d
323 reg = <0 0xb7000000 0
324 alignment = <0x1000>;
325 no-map;
326 };
327 };
328
329 timer {
330 compatible = "arm,armv8-timer"
331 interrupt-parent = <&gic>;
332 interrupts = <GIC_PPI 13
333 (GIC_CPU_MASK_SI
334 <GIC_PPI 14
335 (GIC_CPU_MASK_SI
336 <GIC_PPI 11
337 (GIC_CPU_MASK_SI
338 <GIC_PPI 10
339 (GIC_CPU_MASK_SI
340 arm,no-tick-in-suspend;
341 };
342
343 soc {
344 #address-cells = <2>;
345 #size-cells = <2>;
346 compatible = "simple-bus";
347 ranges;
348
349 topckgen: clock-controller@100
350 compatible = "mediatek
351 reg = <0 0x10000000 0
352 #clock-cells = <1>;
353 };
354
355 infracfg: power-controller@100
356 compatible = "mediatek
357 reg = <0 0x10001000 0
358 #clock-cells = <1>;
359 #reset-cells = <1>;
360 };
361
362 pericfg: power-controller@1000
363 compatible = "mediatek
364 reg = <0 0x10003000 0
365 #clock-cells = <1>;
366 #reset-cells = <1>;
367 };
368
369 syscfg_pctl_a: syscon@10005000
370 compatible = "mediatek
371 reg = <0 0x10005000 0
372 };
373
374 pio: pinctrl@1000b000 {
375 compatible = "mediatek
376 reg = <0 0x1000b000 0
377 mediatek,pctl-regmap =
378 gpio-controller;
379 #gpio-cells = <2>;
380 interrupt-controller;
381 #interrupt-cells = <2>
382 interrupts = <GIC_SPI
383 <GIC_SPI
384 <GIC_SPI
385
386 hdmi_pin: xxx {
387
388 /*hdmi htplg p
389 pins1 {
390 pinmux
391 input-
392 bias-p
393 };
394 };
395
396 i2c0_pins_a: i2c0 {
397 pins1 {
398 pinmux
399
400 bias-d
401 };
402 };
403
404 i2c1_pins_a: i2c1 {
405 pins1 {
406 pinmux
407
408 bias-d
409 };
410 };
411
412 i2c2_pins_a: i2c2 {
413 pins1 {
414 pinmux
415
416 bias-d
417 };
418 };
419
420 i2c3_pins_a: i2c3 {
421 pins1 {
422 pinmux
423
424 bias-d
425 };
426 };
427
428 i2c4_pins_a: i2c4 {
429 pins1 {
430 pinmux
431
432 bias-d
433 };
434 };
435
436 i2c6_pins_a: i2c6 {
437 pins1 {
438 pinmux
439
440 bias-d
441 };
442 };
443 };
444
445 scpsys: syscon@10006000 {
446 compatible = "mediatek
447 reg = <0 0x10006000 0
448
449 /* System Power Manage
450 spm: power-controller
451 compatible = "
452 #address-cells
453 #size-cells =
454 #power-domain-
455
456 /* power domai
457 power-domain@M
458 reg =
459 clocks
460 clock-
461 #power
462 };
463 power-domain@M
464 reg =
465 clocks
466
467 clock-
468 #power
469 };
470 power-domain@M
471 reg =
472 clocks
473 clock-
474 #power
475 };
476 power-domain@M
477 reg =
478 clocks
479 clock-
480 #power
481 mediat
482 };
483 power-domain@M
484 reg =
485 clocks
486
487 clock-
488 #power
489 };
490 power-domain@M
491 reg =
492 #power
493 };
494 power-domain@M
495 reg =
496 #power
497 };
498 mfg_async: pow
499 reg =
500 clocks
501 clock-
502 #addre
503 #size-
504 #power
505
506 power-
507
508
509
510
511
512
513
514
515
516
517 };
518 };
519 };
520 };
521
522 watchdog: watchdog@10007000 {
523 compatible = "mediatek
524 "mediatek
525 reg = <0 0x10007000 0
526 };
527
528 timer: timer@10008000 {
529 compatible = "mediatek
530 "mediatek
531 reg = <0 0x10008000 0
532 interrupts = <GIC_SPI
533 clocks = <&infracfg CL
534 <&topckgen CL
535 };
536
537 pwrap: pwrap@1000d000 {
538 compatible = "mediatek
539 reg = <0 0x1000d000 0
540 reg-names = "pwrap";
541 interrupts = <GIC_SPI
542 resets = <&infracfg MT
543 reset-names = "pwrap";
544 clocks = <&infracfg CL
545 clock-names = "spi", "
546 };
547
548 cec: cec@10013000 {
549 compatible = "mediatek
550 reg = <0 0x10013000 0
551 interrupts = <GIC_SPI
552 clocks = <&infracfg CL
553 status = "disabled";
554 };
555
556 vpu: vpu@10020000 {
557 compatible = "mediatek
558 reg = <0 0x10020000 0
559 <0 0x10050000 0
560 reg-names = "tcm", "cf
561 interrupts = <GIC_SPI
562 clocks = <&topckgen CL
563 clock-names = "main";
564 memory-region = <&vpu_
565 };
566
567 sysirq: intpol-controller@1020
568 compatible = "mediatek
569 "mediatek
570 interrupt-controller;
571 #interrupt-cells = <3>
572 interrupt-parent = <&g
573 reg = <0 0x10200620 0
574 };
575
576 iommu: iommu@10205000 {
577 compatible = "mediatek
578 reg = <0 0x10205000 0
579 interrupts = <GIC_SPI
580 clocks = <&infracfg CL
581 clock-names = "bclk";
582 mediatek,infracfg = <&
583 mediatek,larbs = <&lar
584 <&lar
585 #iommu-cells = <1>;
586 };
587
588 efuse: efuse@10206000 {
589 compatible = "mediatek
590 reg = <0 0x10206000 0
591 #address-cells = <1>;
592 #size-cells = <1>;
593
594 socinfo-data1@40 {
595 reg = <0x040 0
596 };
597
598 socinfo-data2@44 {
599 reg = <0x044 0
600 };
601
602 thermal_calibration: c
603 reg = <0x528 0
604 };
605 };
606
607 apmixedsys: clock-controller@1
608 compatible = "mediatek
609 reg = <0 0x10209000 0
610 #clock-cells = <1>;
611 };
612
613 hdmi_phy: hdmi-phy@10209100 {
614 compatible = "mediatek
615 reg = <0 0x10209100 0
616 clocks = <&apmixedsys
617 clock-names = "pll_ref
618 clock-output-names = "
619 mediatek,ibias = <0xa>
620 mediatek,ibias_up = <0
621 #clock-cells = <0>;
622 #phy-cells = <0>;
623 status = "disabled";
624 };
625
626 gce: mailbox@10212000 {
627 compatible = "mediatek
628 reg = <0 0x10212000 0
629 interrupts = <GIC_SPI
630 clocks = <&infracfg CL
631 clock-names = "gce";
632 #mbox-cells = <2>;
633 };
634
635 mipi_tx0: dsi-phy@10215000 {
636 compatible = "mediatek
637 reg = <0 0x10215000 0
638 clocks = <&clk26m>;
639 clock-output-names = "
640 #clock-cells = <0>;
641 #phy-cells = <0>;
642 status = "disabled";
643 };
644
645 mipi_tx1: dsi-phy@10216000 {
646 compatible = "mediatek
647 reg = <0 0x10216000 0
648 clocks = <&clk26m>;
649 clock-output-names = "
650 #clock-cells = <0>;
651 #phy-cells = <0>;
652 status = "disabled";
653 };
654
655 gic: interrupt-controller@1022
656 compatible = "arm,gic-
657 #interrupt-cells = <3>
658 interrupt-parent = <&g
659 interrupt-controller;
660 reg = <0 0x10221000 0
661 <0 0x10222000 0
662 <0 0x10224000 0
663 <0 0x10226000 0
664 interrupts = <GIC_PPI
665 (GIC_CPU_MASK_
666 };
667
668 auxadc: auxadc@11001000 {
669 compatible = "mediatek
670 reg = <0 0x11001000 0
671 clocks = <&pericfg CLK
672 clock-names = "main";
673 #io-channel-cells = <1
674 };
675
676 uart0: serial@11002000 {
677 compatible = "mediatek
678 "mediatek
679 reg = <0 0x11002000 0
680 interrupts = <GIC_SPI
681 clocks = <&pericfg CLK
682 clock-names = "baud",
683 status = "disabled";
684 };
685
686 uart1: serial@11003000 {
687 compatible = "mediatek
688 "mediatek
689 reg = <0 0x11003000 0
690 interrupts = <GIC_SPI
691 clocks = <&pericfg CLK
692 clock-names = "baud",
693 status = "disabled";
694 };
695
696 uart2: serial@11004000 {
697 compatible = "mediatek
698 "mediatek
699 reg = <0 0x11004000 0
700 interrupts = <GIC_SPI
701 clocks = <&pericfg CLK
702 clock-names = "baud",
703 status = "disabled";
704 };
705
706 uart3: serial@11005000 {
707 compatible = "mediatek
708 "mediatek
709 reg = <0 0x11005000 0
710 interrupts = <GIC_SPI
711 clocks = <&pericfg CLK
712 clock-names = "baud",
713 status = "disabled";
714 };
715
716 i2c0: i2c@11007000 {
717 compatible = "mediatek
718 reg = <0 0x11007000 0
719 <0 0x11000100 0
720 interrupts = <GIC_SPI
721 clock-div = <16>;
722 clocks = <&pericfg CLK
723 <&pericfg CLK
724 clock-names = "main",
725 pinctrl-names = "defau
726 pinctrl-0 = <&i2c0_pin
727 #address-cells = <1>;
728 #size-cells = <0>;
729 status = "disabled";
730 };
731
732 i2c1: i2c@11008000 {
733 compatible = "mediatek
734 reg = <0 0x11008000 0
735 <0 0x11000180 0
736 interrupts = <GIC_SPI
737 clock-div = <16>;
738 clocks = <&pericfg CLK
739 <&pericfg CLK
740 clock-names = "main",
741 pinctrl-names = "defau
742 pinctrl-0 = <&i2c1_pin
743 #address-cells = <1>;
744 #size-cells = <0>;
745 status = "disabled";
746 };
747
748 i2c2: i2c@11009000 {
749 compatible = "mediatek
750 reg = <0 0x11009000 0
751 <0 0x11000200 0
752 interrupts = <GIC_SPI
753 clock-div = <16>;
754 clocks = <&pericfg CLK
755 <&pericfg CLK
756 clock-names = "main",
757 pinctrl-names = "defau
758 pinctrl-0 = <&i2c2_pin
759 #address-cells = <1>;
760 #size-cells = <0>;
761 status = "disabled";
762 };
763
764 spi: spi@1100a000 {
765 compatible = "mediatek
766 #address-cells = <1>;
767 #size-cells = <0>;
768 reg = <0 0x1100a000 0
769 interrupts = <GIC_SPI
770 clocks = <&topckgen CL
771 <&topckgen CL
772 <&pericfg CLK
773 clock-names = "parent-
774 status = "disabled";
775 };
776
777 thermal: thermal@1100b000 {
778 #thermal-sensor-cells
779 compatible = "mediatek
780 reg = <0 0x1100b000 0
781 interrupts = <0 70 IRQ
782 clocks = <&pericfg CLK
783 clock-names = "therm",
784 resets = <&pericfg MT8
785 mediatek,auxadc = <&au
786 mediatek,apmixedsys =
787 nvmem-cells = <&therma
788 nvmem-cell-names = "ca
789 };
790
791 nor_flash: spi@1100d000 {
792 compatible = "mediatek
793 reg = <0 0x1100d000 0
794 assigned-clocks = <&to
795 assigned-clock-parents
796 clocks = <&pericfg CLK
797 <&topckgen CL
798 <&pericfg CLK
799 clock-names = "spi", "
800 #address-cells = <1>;
801 #size-cells = <0>;
802 status = "disabled";
803 };
804
805 i2c3: i2c@11010000 {
806 compatible = "mediatek
807 reg = <0 0x11010000 0
808 <0 0x11000280 0
809 interrupts = <GIC_SPI
810 clock-div = <16>;
811 clocks = <&pericfg CLK
812 <&pericfg CLK
813 clock-names = "main",
814 pinctrl-names = "defau
815 pinctrl-0 = <&i2c3_pin
816 #address-cells = <1>;
817 #size-cells = <0>;
818 status = "disabled";
819 };
820
821 i2c4: i2c@11011000 {
822 compatible = "mediatek
823 reg = <0 0x11011000 0
824 <0 0x11000300 0
825 interrupts = <GIC_SPI
826 clock-div = <16>;
827 clocks = <&pericfg CLK
828 <&pericfg CLK
829 clock-names = "main",
830 pinctrl-names = "defau
831 pinctrl-0 = <&i2c4_pin
832 #address-cells = <1>;
833 #size-cells = <0>;
834 status = "disabled";
835 };
836
837 hdmiddc0: i2c@11012000 {
838 compatible = "mediatek
839 interrupts = <GIC_SPI
840 reg = <0 0x11012000 0
841 clocks = <&pericfg CLK
842 clock-names = "ddc-i2c
843 };
844
845 i2c6: i2c@11013000 {
846 compatible = "mediatek
847 reg = <0 0x11013000 0
848 <0 0x11000080 0
849 interrupts = <GIC_SPI
850 clock-div = <16>;
851 clocks = <&pericfg CLK
852 <&pericfg CLK
853 clock-names = "main",
854 pinctrl-names = "defau
855 pinctrl-0 = <&i2c6_pin
856 #address-cells = <1>;
857 #size-cells = <0>;
858 status = "disabled";
859 };
860
861 afe: audio-controller@11220000
862 compatible = "mediatek
863 reg = <0 0x11220000 0
864 interrupts = <GIC_SPI
865 power-domains = <&spm
866 clocks = <&infracfg CL
867 <&topckgen CL
868 <&topckgen CL
869 <&topckgen CL
870 <&topckgen CL
871 <&topckgen CL
872 <&topckgen CL
873 <&topckgen CL
874 <&topckgen CL
875 <&topckgen CL
876 clock-names = "infra_s
877 "top_pdn
878 "top_pdn
879 "bck0",
880 "bck1",
881 "i2s0_m"
882 "i2s1_m"
883 "i2s2_m"
884 "i2s3_m"
885 "i2s3_b"
886 assigned-clocks = <&to
887 <&to
888 assigned-clock-parents
889
890 };
891
892 mmc0: mmc@11230000 {
893 compatible = "mediatek
894 reg = <0 0x11230000 0
895 interrupts = <GIC_SPI
896 clocks = <&pericfg CLK
897 <&topckgen CL
898 clock-names = "source"
899 status = "disabled";
900 };
901
902 mmc1: mmc@11240000 {
903 compatible = "mediatek
904 reg = <0 0x11240000 0
905 interrupts = <GIC_SPI
906 clocks = <&pericfg CLK
907 <&topckgen CL
908 clock-names = "source"
909 status = "disabled";
910 };
911
912 mmc2: mmc@11250000 {
913 compatible = "mediatek
914 reg = <0 0x11250000 0
915 interrupts = <GIC_SPI
916 clocks = <&pericfg CLK
917 <&topckgen CL
918 clock-names = "source"
919 status = "disabled";
920 };
921
922 mmc3: mmc@11260000 {
923 compatible = "mediatek
924 reg = <0 0x11260000 0
925 interrupts = <GIC_SPI
926 clocks = <&pericfg CLK
927 <&topckgen CL
928 clock-names = "source"
929 status = "disabled";
930 };
931
932 ssusb: usb@11271000 {
933 compatible = "mediatek
934 reg = <0 0x11271000 0
935 <0 0x11280700 0
936 reg-names = "mac", "ip
937 interrupts = <GIC_SPI
938 phys = <&u2port0 PHY_T
939 <&u3port0 PHY_T
940 <&u2port1 PHY_T
941 power-domains = <&spm
942 clocks = <&topckgen CL
943 clock-names = "sys_ck"
944 mediatek,syscon-wakeup
945 #address-cells = <2>;
946 #size-cells = <2>;
947 ranges;
948 status = "disabled";
949
950 usb_host: usb@11270000
951 compatible = "
952 "
953 reg = <0 0x112
954 reg-names = "m
955 interrupts = <
956 power-domains
957 clocks = <&top
958 clock-names =
959 status = "disa
960 };
961 };
962
963 u3phy: t-phy@11290000 {
964 compatible = "mediatek
965 reg = <0 0x11290000 0
966 #address-cells = <2>;
967 #size-cells = <2>;
968 ranges;
969 status = "okay";
970
971 u2port0: usb-phy@11290
972 reg = <0 0x112
973 clocks = <&apm
974 clock-names =
975 #phy-cells = <
976 status = "okay
977 };
978
979 u3port0: usb-phy@11290
980 reg = <0 0x112
981 clocks = <&clk
982 clock-names =
983 #phy-cells = <
984 status = "okay
985 };
986
987 u2port1: usb-phy@11291
988 reg = <0 0x112
989 clocks = <&apm
990 clock-names =
991 #phy-cells = <
992 status = "okay
993 };
994 };
995
996 mmsys: syscon@14000000 {
997 compatible = "mediatek
998 reg = <0 0x14000000 0
999 power-domains = <&spm
1000 assigned-clocks = <&t
1001 assigned-clock-rates
1002 #clock-cells = <1>;
1003 #reset-cells = <1>;
1004 mboxes = <&gce 0 CMDQ
1005 <&gce 1 CMDQ
1006 mediatek,gce-client-r
1007 };
1008
1009 mdp_rdma0: rdma@14001000 {
1010 compatible = "mediate
1011 "mediate
1012 reg = <0 0x14001000 0
1013 clocks = <&mmsys CLK_
1014 <&mmsys CLK_
1015 power-domains = <&spm
1016 iommus = <&iommu M4U_
1017 mediatek,vpu = <&vpu>
1018 };
1019
1020 mdp_rdma1: rdma@14002000 {
1021 compatible = "mediate
1022 reg = <0 0x14002000 0
1023 clocks = <&mmsys CLK_
1024 <&mmsys CLK_
1025 power-domains = <&spm
1026 iommus = <&iommu M4U_
1027 };
1028
1029 mdp_rsz0: rsz@14003000 {
1030 compatible = "mediate
1031 reg = <0 0x14003000 0
1032 clocks = <&mmsys CLK_
1033 power-domains = <&spm
1034 };
1035
1036 mdp_rsz1: rsz@14004000 {
1037 compatible = "mediate
1038 reg = <0 0x14004000 0
1039 clocks = <&mmsys CLK_
1040 power-domains = <&spm
1041 };
1042
1043 mdp_rsz2: rsz@14005000 {
1044 compatible = "mediate
1045 reg = <0 0x14005000 0
1046 clocks = <&mmsys CLK_
1047 power-domains = <&spm
1048 };
1049
1050 mdp_wdma0: wdma@14006000 {
1051 compatible = "mediate
1052 reg = <0 0x14006000 0
1053 clocks = <&mmsys CLK_
1054 power-domains = <&spm
1055 iommus = <&iommu M4U_
1056 };
1057
1058 mdp_wrot0: wrot@14007000 {
1059 compatible = "mediate
1060 reg = <0 0x14007000 0
1061 clocks = <&mmsys CLK_
1062 power-domains = <&spm
1063 iommus = <&iommu M4U_
1064 };
1065
1066 mdp_wrot1: wrot@14008000 {
1067 compatible = "mediate
1068 reg = <0 0x14008000 0
1069 clocks = <&mmsys CLK_
1070 power-domains = <&spm
1071 iommus = <&iommu M4U_
1072 };
1073
1074 ovl0: ovl@1400c000 {
1075 compatible = "mediate
1076 reg = <0 0x1400c000 0
1077 interrupts = <GIC_SPI
1078 power-domains = <&spm
1079 clocks = <&mmsys CLK_
1080 iommus = <&iommu M4U_
1081 mediatek,gce-client-r
1082 };
1083
1084 ovl1: ovl@1400d000 {
1085 compatible = "mediate
1086 reg = <0 0x1400d000 0
1087 interrupts = <GIC_SPI
1088 power-domains = <&spm
1089 clocks = <&mmsys CLK_
1090 iommus = <&iommu M4U_
1091 mediatek,gce-client-r
1092 };
1093
1094 rdma0: rdma@1400e000 {
1095 compatible = "mediate
1096 reg = <0 0x1400e000 0
1097 interrupts = <GIC_SPI
1098 power-domains = <&spm
1099 clocks = <&mmsys CLK_
1100 iommus = <&iommu M4U_
1101 mediatek,gce-client-r
1102 };
1103
1104 rdma1: rdma@1400f000 {
1105 compatible = "mediate
1106 reg = <0 0x1400f000 0
1107 interrupts = <GIC_SPI
1108 power-domains = <&spm
1109 clocks = <&mmsys CLK_
1110 iommus = <&iommu M4U_
1111 mediatek,gce-client-r
1112 };
1113
1114 rdma2: rdma@14010000 {
1115 compatible = "mediate
1116 reg = <0 0x14010000 0
1117 interrupts = <GIC_SPI
1118 power-domains = <&spm
1119 clocks = <&mmsys CLK_
1120 iommus = <&iommu M4U_
1121 mediatek,gce-client-r
1122 };
1123
1124 wdma0: wdma@14011000 {
1125 compatible = "mediate
1126 reg = <0 0x14011000 0
1127 interrupts = <GIC_SPI
1128 power-domains = <&spm
1129 clocks = <&mmsys CLK_
1130 iommus = <&iommu M4U_
1131 mediatek,gce-client-r
1132 };
1133
1134 wdma1: wdma@14012000 {
1135 compatible = "mediate
1136 reg = <0 0x14012000 0
1137 interrupts = <GIC_SPI
1138 power-domains = <&spm
1139 clocks = <&mmsys CLK_
1140 iommus = <&iommu M4U_
1141 mediatek,gce-client-r
1142 };
1143
1144 color0: color@14013000 {
1145 compatible = "mediate
1146 reg = <0 0x14013000 0
1147 interrupts = <GIC_SPI
1148 power-domains = <&spm
1149 clocks = <&mmsys CLK_
1150 mediatek,gce-client-r
1151 };
1152
1153 color1: color@14014000 {
1154 compatible = "mediate
1155 reg = <0 0x14014000 0
1156 interrupts = <GIC_SPI
1157 power-domains = <&spm
1158 clocks = <&mmsys CLK_
1159 mediatek,gce-client-r
1160 };
1161
1162 aal@14015000 {
1163 compatible = "mediate
1164 reg = <0 0x14015000 0
1165 interrupts = <GIC_SPI
1166 power-domains = <&spm
1167 clocks = <&mmsys CLK_
1168 mediatek,gce-client-r
1169 };
1170
1171 gamma@14016000 {
1172 compatible = "mediate
1173 reg = <0 0x14016000 0
1174 interrupts = <GIC_SPI
1175 power-domains = <&spm
1176 clocks = <&mmsys CLK_
1177 mediatek,gce-client-r
1178 };
1179
1180 merge@14017000 {
1181 compatible = "mediate
1182 reg = <0 0x14017000 0
1183 power-domains = <&spm
1184 clocks = <&mmsys CLK_
1185 };
1186
1187 split0: split@14018000 {
1188 compatible = "mediate
1189 reg = <0 0x14018000 0
1190 power-domains = <&spm
1191 clocks = <&mmsys CLK_
1192 };
1193
1194 split1: split@14019000 {
1195 compatible = "mediate
1196 reg = <0 0x14019000 0
1197 power-domains = <&spm
1198 clocks = <&mmsys CLK_
1199 };
1200
1201 ufoe@1401a000 {
1202 compatible = "mediate
1203 reg = <0 0x1401a000 0
1204 interrupts = <GIC_SPI
1205 power-domains = <&spm
1206 clocks = <&mmsys CLK_
1207 mediatek,gce-client-r
1208 };
1209
1210 dsi0: dsi@1401b000 {
1211 compatible = "mediate
1212 reg = <0 0x1401b000 0
1213 interrupts = <GIC_SPI
1214 power-domains = <&spm
1215 clocks = <&mmsys CLK_
1216 <&mmsys CLK_
1217 <&mipi_tx0>;
1218 clock-names = "engine
1219 resets = <&mmsys MT81
1220 phys = <&mipi_tx0>;
1221 phy-names = "dphy";
1222 status = "disabled";
1223 };
1224
1225 dsi1: dsi@1401c000 {
1226 compatible = "mediate
1227 reg = <0 0x1401c000 0
1228 interrupts = <GIC_SPI
1229 power-domains = <&spm
1230 clocks = <&mmsys CLK_
1231 <&mmsys CLK_
1232 <&mipi_tx1>;
1233 clock-names = "engine
1234 phys = <&mipi_tx1>;
1235 phy-names = "dphy";
1236 status = "disabled";
1237 };
1238
1239 dpi0: dpi@1401d000 {
1240 compatible = "mediate
1241 reg = <0 0x1401d000 0
1242 interrupts = <GIC_SPI
1243 power-domains = <&spm
1244 clocks = <&mmsys CLK_
1245 <&mmsys CLK_
1246 <&apmixedsys
1247 clock-names = "pixel"
1248 status = "disabled";
1249
1250 port {
1251 dpi0_out: end
1252 remot
1253 };
1254 };
1255 };
1256
1257 pwm0: pwm@1401e000 {
1258 compatible = "mediate
1259 "mediate
1260 reg = <0 0x1401e000 0
1261 #pwm-cells = <2>;
1262 clocks = <&mmsys CLK_
1263 <&mmsys CLK_
1264 clock-names = "main",
1265 status = "disabled";
1266 };
1267
1268 pwm1: pwm@1401f000 {
1269 compatible = "mediate
1270 "mediate
1271 reg = <0 0x1401f000 0
1272 #pwm-cells = <2>;
1273 clocks = <&mmsys CLK_
1274 <&mmsys CLK_
1275 clock-names = "main",
1276 status = "disabled";
1277 };
1278
1279 mutex: mutex@14020000 {
1280 compatible = "mediate
1281 reg = <0 0x14020000 0
1282 interrupts = <GIC_SPI
1283 power-domains = <&spm
1284 clocks = <&mmsys CLK_
1285 mediatek,gce-client-r
1286 mediatek,gce-events =
1287
1288 };
1289
1290 larb0: larb@14021000 {
1291 compatible = "mediate
1292 reg = <0 0x14021000 0
1293 mediatek,smi = <&smi_
1294 power-domains = <&spm
1295 clocks = <&mmsys CLK_
1296 <&mmsys CLK_
1297 clock-names = "apb",
1298 };
1299
1300 smi_common: smi@14022000 {
1301 compatible = "mediate
1302 reg = <0 0x14022000 0
1303 power-domains = <&spm
1304 clocks = <&mmsys CLK_
1305 <&mmsys CLK_
1306 clock-names = "apb",
1307 };
1308
1309 od@14023000 {
1310 compatible = "mediate
1311 reg = <0 0x14023000 0
1312 clocks = <&mmsys CLK_
1313 mediatek,gce-client-r
1314 };
1315
1316 hdmi0: hdmi@14025000 {
1317 compatible = "mediate
1318 reg = <0 0x14025000 0
1319 interrupts = <GIC_SPI
1320 clocks = <&mmsys CLK_
1321 <&mmsys CLK_
1322 <&mmsys CLK_
1323 <&mmsys CLK_
1324 clock-names = "pixel"
1325 pinctrl-names = "defa
1326 pinctrl-0 = <&hdmi_pi
1327 phys = <&hdmi_phy>;
1328 phy-names = "hdmi";
1329 mediatek,syscon-hdmi
1330 assigned-clocks = <&t
1331 assigned-clock-parent
1332 status = "disabled";
1333
1334 ports {
1335 #address-cell
1336 #size-cells =
1337
1338 port@0 {
1339 reg =
1340
1341 hdmi0
1342
1343 };
1344 };
1345 };
1346 };
1347
1348 larb4: larb@14027000 {
1349 compatible = "mediate
1350 reg = <0 0x14027000 0
1351 mediatek,smi = <&smi_
1352 power-domains = <&spm
1353 clocks = <&mmsys CLK_
1354 <&mmsys CLK_
1355 clock-names = "apb",
1356 };
1357
1358 imgsys: clock-controller@1500
1359 compatible = "mediate
1360 reg = <0 0x15000000 0
1361 #clock-cells = <1>;
1362 };
1363
1364 larb2: larb@15001000 {
1365 compatible = "mediate
1366 reg = <0 0x15001000 0
1367 mediatek,smi = <&smi_
1368 power-domains = <&spm
1369 clocks = <&imgsys CLK
1370 <&imgsys CLK
1371 clock-names = "apb",
1372 };
1373
1374 vdecsys: clock-controller@160
1375 compatible = "mediate
1376 reg = <0 0x16000000 0
1377 #clock-cells = <1>;
1378 };
1379
1380 vcodec_dec: vcodec@16020000 {
1381 compatible = "mediate
1382 reg = <0 0x16020000 0
1383 <0 0x16021000 0
1384 <0 0x16021800 0
1385 <0 0x16022000 0
1386 <0 0x16023000 0
1387 <0 0x16024000 0
1388 <0 0x16025000 0
1389 <0 0x16026800 0
1390 <0 0x16027000 0
1391 <0 0x16027800 0
1392 <0 0x16028400 0
1393 reg-names = "misc", "
1394 "hwd", "h
1395 interrupts = <GIC_SPI
1396 iommus = <&iommu M4U_
1397 <&iommu M4U_
1398 <&iommu M4U_
1399 <&iommu M4U_
1400 <&iommu M4U_
1401 <&iommu M4U_
1402 <&iommu M4U_
1403 <&iommu M4U_
1404 mediatek,vpu = <&vpu>
1405 mediatek,vdecsys = <&
1406 power-domains = <&spm
1407 clocks = <&apmixedsys
1408 <&topckgen C
1409 <&topckgen C
1410 <&topckgen C
1411 <&topckgen C
1412 <&apmixedsys
1413 <&topckgen C
1414 <&topckgen C
1415 clock-names = "vcodec
1416 "univpl
1417 "clk_cc
1418 "vdec_s
1419 "vdecpl
1420 "vencpl
1421 "venc_l
1422 "vdec_b
1423 assigned-clocks = <&t
1424 <&t
1425 <&t
1426 <&a
1427 <&a
1428 assigned-clock-parent
1429
1430
1431 assigned-clock-rates
1432 };
1433
1434 larb1: larb@16010000 {
1435 compatible = "mediate
1436 reg = <0 0x16010000 0
1437 mediatek,smi = <&smi_
1438 power-domains = <&spm
1439 clocks = <&vdecsys CL
1440 <&vdecsys CL
1441 clock-names = "apb",
1442 };
1443
1444 vencsys: clock-controller@180
1445 compatible = "mediate
1446 reg = <0 0x18000000 0
1447 #clock-cells = <1>;
1448 };
1449
1450 larb3: larb@18001000 {
1451 compatible = "mediate
1452 reg = <0 0x18001000 0
1453 mediatek,smi = <&smi_
1454 power-domains = <&spm
1455 clocks = <&vencsys CL
1456 <&vencsys CL
1457 clock-names = "apb",
1458 };
1459
1460 vcodec_enc_avc: vcodec@180020
1461 compatible = "mediate
1462 reg = <0 0x18002000 0
1463 interrupts = <GIC_SPI
1464 iommus = <&iommu M4U_
1465 <&iommu M4U_
1466 <&iommu M4U_
1467 <&iommu M4U_
1468 <&iommu M4U_
1469 <&iommu M4U_
1470 <&iommu M4U_
1471 <&iommu M4U_
1472 <&iommu M4U_
1473 <&iommu M4U_
1474 <&iommu M4U_
1475 mediatek,vpu = <&vpu>
1476 clocks = <&topckgen C
1477 clock-names = "venc_s
1478 assigned-clocks = <&t
1479 assigned-clock-parent
1480 power-domains = <&spm
1481 };
1482
1483 jpegdec: jpegdec@18004000 {
1484 compatible = "mediate
1485 reg = <0 0x18004000 0
1486 interrupts = <GIC_SPI
1487 clocks = <&vencsys CL
1488 <&vencsys CL
1489 clock-names = "jpgdec
1490 "jpgdec
1491 power-domains = <&spm
1492 iommus = <&iommu M4U_
1493 <&iommu M4U_
1494 };
1495
1496 vencltsys: clock-controller@1
1497 compatible = "mediate
1498 reg = <0 0x19000000 0
1499 #clock-cells = <1>;
1500 };
1501
1502 larb5: larb@19001000 {
1503 compatible = "mediate
1504 reg = <0 0x19001000 0
1505 mediatek,smi = <&smi_
1506 power-domains = <&spm
1507 clocks = <&vencltsys
1508 <&vencltsys
1509 clock-names = "apb",
1510 };
1511
1512 vcodec_enc_vp8: vcodec@190020
1513 compatible = "mediate
1514 reg = <0 0x19002000 0
1515 interrupts = <GIC_SPI
1516 iommus = <&iommu M4U_
1517 <&iommu M4U_
1518 <&iommu M4U_
1519 <&iommu M4U_
1520 <&iommu M4U_
1521 <&iommu M4U_
1522 <&iommu M4U_
1523 <&iommu M4U_
1524 <&iommu M4U_
1525 mediatek,vpu = <&vpu>
1526 clocks = <&topckgen C
1527 clock-names = "venc_l
1528 assigned-clocks = <&t
1529 assigned-clock-parent
1530 <&topckgen C
1531 power-domains = <&spm
1532 };
1533 };
1534 };
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