1 // SPDX-License-Identifier: (GPL-2.0-only OR B
2 /*
3 * Copyright (C) 2022 MediaTek Inc.
4 * Author: Allen-KH Cheng <allen-kh.cheng@media
5 */
6 /dts-v1/;
7 #include <dt-bindings/clock/mt8186-clk.h>
8 #include <dt-bindings/gce/mt8186-gce.h>
9 #include <dt-bindings/interrupt-controller/arm
10 #include <dt-bindings/interrupt-controller/irq
11 #include <dt-bindings/memory/mt8186-memory-por
12 #include <dt-bindings/pinctrl/mt8186-pinfunc.h
13 #include <dt-bindings/power/mt8186-power.h>
14 #include <dt-bindings/phy/phy.h>
15 #include <dt-bindings/reset/mt8186-resets.h>
16 #include <dt-bindings/thermal/thermal.h>
17 #include <dt-bindings/thermal/mediatek,lvts-th
18
19 / {
20 compatible = "mediatek,mt8186";
21 interrupt-parent = <&gic>;
22 #address-cells = <2>;
23 #size-cells = <2>;
24
25 aliases {
26 ovl0 = &ovl0;
27 ovl-2l0 = &ovl_2l0;
28 rdma0 = &rdma0;
29 rdma1 = &rdma1;
30 };
31
32 cci: cci {
33 compatible = "mediatek,mt8186-
34 clocks = <&mcusys CLK_MCU_ARMP
35 <&apmixedsys CLK_APMI
36 clock-names = "cci", "intermed
37 operating-points-v2 = <&cci_op
38 };
39
40 cci_opp: opp-table-cci {
41 compatible = "operating-points
42 opp-shared;
43
44 cci_opp_0: opp-500000000 {
45 opp-hz = /bits/ 64 <50
46 opp-microvolt = <60000
47 };
48
49 cci_opp_1: opp-560000000 {
50 opp-hz = /bits/ 64 <56
51 opp-microvolt = <67500
52 };
53
54 cci_opp_2: opp-612000000 {
55 opp-hz = /bits/ 64 <61
56 opp-microvolt = <69375
57 };
58
59 cci_opp_3: opp-682000000 {
60 opp-hz = /bits/ 64 <68
61 opp-microvolt = <71875
62 };
63
64 cci_opp_4: opp-752000000 {
65 opp-hz = /bits/ 64 <75
66 opp-microvolt = <74375
67 };
68
69 cci_opp_5: opp-822000000 {
70 opp-hz = /bits/ 64 <82
71 opp-microvolt = <76875
72 };
73
74 cci_opp_6: opp-875000000 {
75 opp-hz = /bits/ 64 <87
76 opp-microvolt = <78125
77 };
78
79 cci_opp_7: opp-927000000 {
80 opp-hz = /bits/ 64 <92
81 opp-microvolt = <80000
82 };
83
84 cci_opp_8: opp-980000000 {
85 opp-hz = /bits/ 64 <98
86 opp-microvolt = <81875
87 };
88
89 cci_opp_9: opp-1050000000 {
90 opp-hz = /bits/ 64 <10
91 opp-microvolt = <84375
92 };
93
94 cci_opp_10: opp-1120000000 {
95 opp-hz = /bits/ 64 <11
96 opp-microvolt = <86250
97 };
98
99 cci_opp_11: opp-1155000000 {
100 opp-hz = /bits/ 64 <11
101 opp-microvolt = <88750
102 };
103
104 cci_opp_12: opp-1190000000 {
105 opp-hz = /bits/ 64 <11
106 opp-microvolt = <90625
107 };
108
109 cci_opp_13: opp-1260000000 {
110 opp-hz = /bits/ 64 <12
111 opp-microvolt = <95000
112 };
113
114 cci_opp_14: opp-1330000000 {
115 opp-hz = /bits/ 64 <13
116 opp-microvolt = <99375
117 };
118
119 cci_opp_15: opp-1400000000 {
120 opp-hz = /bits/ 64 <14
121 opp-microvolt = <10312
122 };
123 };
124
125 cluster0_opp: opp-table-cluster0 {
126 compatible = "operating-points
127 opp-shared;
128
129 opp-500000000 {
130 opp-hz = /bits/ 64 <50
131 opp-microvolt = <60000
132 required-opps = <&cci_
133 };
134
135 opp-774000000 {
136 opp-hz = /bits/ 64 <77
137 opp-microvolt = <67500
138 required-opps = <&cci_
139 };
140
141 opp-875000000 {
142 opp-hz = /bits/ 64 <87
143 opp-microvolt = <70000
144 required-opps = <&cci_
145 };
146
147 opp-975000000 {
148 opp-hz = /bits/ 64 <97
149 opp-microvolt = <72500
150 required-opps = <&cci_
151 };
152
153 opp-1075000000 {
154 opp-hz = /bits/ 64 <10
155 opp-microvolt = <75000
156 required-opps = <&cci_
157 };
158
159 opp-1175000000 {
160 opp-hz = /bits/ 64 <11
161 opp-microvolt = <77500
162 required-opps = <&cci_
163 };
164
165 opp-1275000000 {
166 opp-hz = /bits/ 64 <12
167 opp-microvolt = <80000
168 required-opps = <&cci_
169 };
170
171 opp-1375000000 {
172 opp-hz = /bits/ 64 <13
173 opp-microvolt = <82500
174 required-opps = <&cci_
175 };
176
177 opp-1500000000 {
178 opp-hz = /bits/ 64 <15
179 opp-microvolt = <85625
180 required-opps = <&cci_
181 };
182
183 opp-1618000000 {
184 opp-hz = /bits/ 64 <16
185 opp-microvolt = <87500
186 required-opps = <&cci_
187 };
188
189 opp-1666000000 {
190 opp-hz = /bits/ 64 <16
191 opp-microvolt = <90000
192 required-opps = <&cci_
193 };
194
195 opp-1733000000 {
196 opp-hz = /bits/ 64 <17
197 opp-microvolt = <92500
198 required-opps = <&cci_
199 };
200
201 opp-1800000000 {
202 opp-hz = /bits/ 64 <18
203 opp-microvolt = <95000
204 required-opps = <&cci_
205 };
206
207 opp-1866000000 {
208 opp-hz = /bits/ 64 <18
209 opp-microvolt = <98125
210 required-opps = <&cci_
211 };
212
213 opp-1933000000 {
214 opp-hz = /bits/ 64 <19
215 opp-microvolt = <10062
216 required-opps = <&cci_
217 };
218
219 opp-2000000000 {
220 opp-hz = /bits/ 64 <20
221 opp-microvolt = <10312
222 required-opps = <&cci_
223 };
224 };
225
226 cluster1_opp: opp-table-cluster1 {
227 compatible = "operating-points
228 opp-shared;
229
230 opp-774000000 {
231 opp-hz = /bits/ 64 <77
232 opp-microvolt = <67500
233 required-opps = <&cci_
234 };
235
236 opp-835000000 {
237 opp-hz = /bits/ 64 <83
238 opp-microvolt = <69375
239 required-opps = <&cci_
240 };
241
242 opp-919000000 {
243 opp-hz = /bits/ 64 <91
244 opp-microvolt = <71875
245 required-opps = <&cci_
246 };
247
248 opp-1002000000 {
249 opp-hz = /bits/ 64 <10
250 opp-microvolt = <74375
251 required-opps = <&cci_
252 };
253
254 opp-1085000000 {
255 opp-hz = /bits/ 64 <10
256 opp-microvolt = <77500
257 required-opps = <&cci_
258 };
259
260 opp-1169000000 {
261 opp-hz = /bits/ 64 <11
262 opp-microvolt = <80000
263 required-opps = <&cci_
264 };
265
266 opp-1308000000 {
267 opp-hz = /bits/ 64 <13
268 opp-microvolt = <84375
269 required-opps = <&cci_
270 };
271
272 opp-1419000000 {
273 opp-hz = /bits/ 64 <14
274 opp-microvolt = <87500
275 required-opps = <&cci_
276 };
277
278 opp-1530000000 {
279 opp-hz = /bits/ 64 <15
280 opp-microvolt = <91250
281 required-opps = <&cci_
282 };
283
284 opp-1670000000 {
285 opp-hz = /bits/ 64 <16
286 opp-microvolt = <95625
287 required-opps = <&cci_
288 };
289
290 opp-1733000000 {
291 opp-hz = /bits/ 64 <17
292 opp-microvolt = <98125
293 required-opps = <&cci_
294 };
295
296 opp-1796000000 {
297 opp-hz = /bits/ 64 <17
298 opp-microvolt = <10125
299 required-opps = <&cci_
300 };
301
302 opp-1860000000 {
303 opp-hz = /bits/ 64 <18
304 opp-microvolt = <10375
305 required-opps = <&cci_
306 };
307
308 opp-1923000000 {
309 opp-hz = /bits/ 64 <19
310 opp-microvolt = <10625
311 required-opps = <&cci_
312 };
313
314 cluster1_opp_14: opp-198600000
315 opp-hz = /bits/ 64 <19
316 opp-microvolt = <10937
317 required-opps = <&cci_
318 };
319
320 cluster1_opp_15: opp-205000000
321 opp-hz = /bits/ 64 <20
322 opp-microvolt = <11187
323 required-opps = <&cci_
324 };
325 };
326
327 cpus {
328 #address-cells = <1>;
329 #size-cells = <0>;
330
331 cpu-map {
332 cluster0 {
333 core0 {
334 cpu =
335 };
336
337 core1 {
338 cpu =
339 };
340
341 core2 {
342 cpu =
343 };
344
345 core3 {
346 cpu =
347 };
348
349 core4 {
350 cpu =
351 };
352
353 core5 {
354 cpu =
355 };
356
357 core6 {
358 cpu =
359 };
360
361 core7 {
362 cpu =
363 };
364 };
365 };
366
367 cpu0: cpu@0 {
368 device_type = "cpu";
369 compatible = "arm,cort
370 reg = <0x000>;
371 enable-method = "psci"
372 clock-frequency = <200
373 clocks = <&mcusys CLK_
374 <&apmixedsys
375 clock-names = "cpu", "
376 operating-points-v2 =
377 dynamic-power-coeffici
378 capacity-dmips-mhz = <
379 cpu-idle-states = <&cp
380 i-cache-size = <32768>
381 i-cache-line-size = <6
382 i-cache-sets = <128>;
383 d-cache-size = <32768>
384 d-cache-line-size = <6
385 d-cache-sets = <128>;
386 next-level-cache = <&l
387 #cooling-cells = <2>;
388 mediatek,cci = <&cci>;
389 };
390
391 cpu1: cpu@100 {
392 device_type = "cpu";
393 compatible = "arm,cort
394 reg = <0x100>;
395 enable-method = "psci"
396 clock-frequency = <200
397 clocks = <&mcusys CLK_
398 <&apmixedsys
399 clock-names = "cpu", "
400 operating-points-v2 =
401 dynamic-power-coeffici
402 capacity-dmips-mhz = <
403 cpu-idle-states = <&cp
404 i-cache-size = <32768>
405 i-cache-line-size = <6
406 i-cache-sets = <128>;
407 d-cache-size = <32768>
408 d-cache-line-size = <6
409 d-cache-sets = <128>;
410 next-level-cache = <&l
411 #cooling-cells = <2>;
412 mediatek,cci = <&cci>;
413 };
414
415 cpu2: cpu@200 {
416 device_type = "cpu";
417 compatible = "arm,cort
418 reg = <0x200>;
419 enable-method = "psci"
420 clock-frequency = <200
421 clocks = <&mcusys CLK_
422 <&apmixedsys
423 clock-names = "cpu", "
424 operating-points-v2 =
425 dynamic-power-coeffici
426 capacity-dmips-mhz = <
427 cpu-idle-states = <&cp
428 i-cache-size = <32768>
429 i-cache-line-size = <6
430 i-cache-sets = <128>;
431 d-cache-size = <32768>
432 d-cache-line-size = <6
433 d-cache-sets = <128>;
434 next-level-cache = <&l
435 #cooling-cells = <2>;
436 mediatek,cci = <&cci>;
437 };
438
439 cpu3: cpu@300 {
440 device_type = "cpu";
441 compatible = "arm,cort
442 reg = <0x300>;
443 enable-method = "psci"
444 clock-frequency = <200
445 clocks = <&mcusys CLK_
446 <&apmixedsys
447 clock-names = "cpu", "
448 operating-points-v2 =
449 dynamic-power-coeffici
450 capacity-dmips-mhz = <
451 cpu-idle-states = <&cp
452 i-cache-size = <32768>
453 i-cache-line-size = <6
454 i-cache-sets = <128>;
455 d-cache-size = <32768>
456 d-cache-line-size = <6
457 d-cache-sets = <128>;
458 next-level-cache = <&l
459 #cooling-cells = <2>;
460 mediatek,cci = <&cci>;
461 };
462
463 cpu4: cpu@400 {
464 device_type = "cpu";
465 compatible = "arm,cort
466 reg = <0x400>;
467 enable-method = "psci"
468 clock-frequency = <200
469 clocks = <&mcusys CLK_
470 <&apmixedsys
471 clock-names = "cpu", "
472 operating-points-v2 =
473 dynamic-power-coeffici
474 capacity-dmips-mhz = <
475 cpu-idle-states = <&cp
476 i-cache-size = <32768>
477 i-cache-line-size = <6
478 i-cache-sets = <128>;
479 d-cache-size = <32768>
480 d-cache-line-size = <6
481 d-cache-sets = <128>;
482 next-level-cache = <&l
483 #cooling-cells = <2>;
484 mediatek,cci = <&cci>;
485 };
486
487 cpu5: cpu@500 {
488 device_type = "cpu";
489 compatible = "arm,cort
490 reg = <0x500>;
491 enable-method = "psci"
492 clock-frequency = <200
493 clocks = <&mcusys CLK_
494 <&apmixedsys
495 clock-names = "cpu", "
496 operating-points-v2 =
497 dynamic-power-coeffici
498 capacity-dmips-mhz = <
499 cpu-idle-states = <&cp
500 i-cache-size = <32768>
501 i-cache-line-size = <6
502 i-cache-sets = <128>;
503 d-cache-size = <32768>
504 d-cache-line-size = <6
505 d-cache-sets = <128>;
506 next-level-cache = <&l
507 #cooling-cells = <2>;
508 mediatek,cci = <&cci>;
509 };
510
511 cpu6: cpu@600 {
512 device_type = "cpu";
513 compatible = "arm,cort
514 reg = <0x600>;
515 enable-method = "psci"
516 clock-frequency = <205
517 clocks = <&mcusys CLK_
518 <&apmixedsys
519 clock-names = "cpu", "
520 operating-points-v2 =
521 dynamic-power-coeffici
522 capacity-dmips-mhz = <
523 cpu-idle-states = <&cp
524 i-cache-size = <65536>
525 i-cache-line-size = <6
526 i-cache-sets = <256>;
527 d-cache-size = <65536>
528 d-cache-line-size = <6
529 d-cache-sets = <256>;
530 next-level-cache = <&l
531 #cooling-cells = <2>;
532 mediatek,cci = <&cci>;
533 };
534
535 cpu7: cpu@700 {
536 device_type = "cpu";
537 compatible = "arm,cort
538 reg = <0x700>;
539 enable-method = "psci"
540 clock-frequency = <205
541 clocks = <&mcusys CLK_
542 <&apmixedsys
543 clock-names = "cpu", "
544 operating-points-v2 =
545 dynamic-power-coeffici
546 capacity-dmips-mhz = <
547 cpu-idle-states = <&cp
548 i-cache-size = <65536>
549 i-cache-line-size = <6
550 i-cache-sets = <256>;
551 d-cache-size = <65536>
552 d-cache-line-size = <6
553 d-cache-sets = <256>;
554 next-level-cache = <&l
555 #cooling-cells = <2>;
556 mediatek,cci = <&cci>;
557 };
558
559 idle-states {
560 entry-method = "psci";
561
562 cpu_ret_l: cpu-retenti
563 compatible = "
564 arm,psci-suspe
565 local-timer-st
566 entry-latency-
567 exit-latency-u
568 min-residency-
569 };
570
571 cpu_ret_b: cpu-retenti
572 compatible = "
573 arm,psci-suspe
574 local-timer-st
575 entry-latency-
576 exit-latency-u
577 min-residency-
578 };
579
580 cpu_off_l: cpu-off-l {
581 compatible = "
582 arm,psci-suspe
583 local-timer-st
584 entry-latency-
585 exit-latency-u
586 min-residency-
587 };
588
589 cpu_off_b: cpu-off-b {
590 compatible = "
591 arm,psci-suspe
592 local-timer-st
593 entry-latency-
594 exit-latency-u
595 min-residency-
596 };
597 };
598
599 l2_0: l2-cache0 {
600 compatible = "cache";
601 cache-level = <2>;
602 cache-size = <131072>;
603 cache-line-size = <64>
604 cache-sets = <512>;
605 next-level-cache = <&l
606 cache-unified;
607 };
608
609 l2_1: l2-cache1 {
610 compatible = "cache";
611 cache-level = <2>;
612 cache-size = <262144>;
613 cache-line-size = <64>
614 cache-sets = <512>;
615 next-level-cache = <&l
616 cache-unified;
617 };
618
619 l3_0: l3-cache {
620 compatible = "cache";
621 cache-level = <3>;
622 cache-size = <1048576>
623 cache-line-size = <64>
624 cache-sets = <1024>;
625 cache-unified;
626 };
627 };
628
629 clk13m: fixed-factor-clock-13m {
630 compatible = "fixed-factor-clo
631 #clock-cells = <0>;
632 clocks = <&clk26m>;
633 clock-div = <2>;
634 clock-mult = <1>;
635 clock-output-names = "clk13m";
636 };
637
638 clk26m: oscillator-26m {
639 compatible = "fixed-clock";
640 #clock-cells = <0>;
641 clock-frequency = <26000000>;
642 clock-output-names = "clk26m";
643 };
644
645 clk32k: oscillator-32k {
646 compatible = "fixed-clock";
647 #clock-cells = <0>;
648 clock-frequency = <32768>;
649 clock-output-names = "clk32k";
650 };
651
652 gpu_opp_table: opp-table-gpu {
653 compatible = "operating-points
654
655 opp-299000000 {
656 opp-hz = /bits/ 64 <29
657 opp-microvolt = <61250
658 opp-supported-hw = <0x
659 };
660
661 opp-332000000 {
662 opp-hz = /bits/ 64 <33
663 opp-microvolt = <62500
664 opp-supported-hw = <0x
665 };
666
667 opp-366000000 {
668 opp-hz = /bits/ 64 <36
669 opp-microvolt = <63750
670 opp-supported-hw = <0x
671 };
672
673 opp-400000000 {
674 opp-hz = /bits/ 64 <40
675 opp-microvolt = <64375
676 opp-supported-hw = <0x
677 };
678
679 opp-434000000 {
680 opp-hz = /bits/ 64 <43
681 opp-microvolt = <65625
682 opp-supported-hw = <0x
683 };
684
685 opp-484000000 {
686 opp-hz = /bits/ 64 <48
687 opp-microvolt = <66875
688 opp-supported-hw = <0x
689 };
690
691 opp-535000000 {
692 opp-hz = /bits/ 64 <53
693 opp-microvolt = <68750
694 opp-supported-hw = <0x
695 };
696
697 opp-586000000 {
698 opp-hz = /bits/ 64 <58
699 opp-microvolt = <70000
700 opp-supported-hw = <0x
701 };
702
703 opp-637000000 {
704 opp-hz = /bits/ 64 <63
705 opp-microvolt = <71250
706 opp-supported-hw = <0x
707 };
708
709 opp-690000000 {
710 opp-hz = /bits/ 64 <69
711 opp-microvolt = <73750
712 opp-supported-hw = <0x
713 };
714
715 opp-743000000 {
716 opp-hz = /bits/ 64 <74
717 opp-microvolt = <75625
718 opp-supported-hw = <0x
719 };
720
721 opp-796000000 {
722 opp-hz = /bits/ 64 <79
723 opp-microvolt = <78125
724 opp-supported-hw = <0x
725 };
726
727 opp-850000000 {
728 opp-hz = /bits/ 64 <85
729 opp-microvolt = <80000
730 opp-supported-hw = <0x
731 };
732
733 opp-900000000-3 {
734 opp-hz = /bits/ 64 <90
735 opp-microvolt = <85000
736 opp-supported-hw = <0x
737 };
738
739 opp-900000000-4 {
740 opp-hz = /bits/ 64 <90
741 opp-microvolt = <83750
742 opp-supported-hw = <0x
743 };
744
745 opp-900000000-5 {
746 opp-hz = /bits/ 64 <90
747 opp-microvolt = <82500
748 opp-supported-hw = <0x
749 };
750
751 opp-950000000-3 {
752 opp-hz = /bits/ 64 <95
753 opp-microvolt = <90000
754 opp-supported-hw = <0x
755 };
756
757 opp-950000000-4 {
758 opp-hz = /bits/ 64 <95
759 opp-microvolt = <87500
760 opp-supported-hw = <0x
761 };
762
763 opp-950000000-5 {
764 opp-hz = /bits/ 64 <95
765 opp-microvolt = <85000
766 opp-supported-hw = <0x
767 };
768
769 opp-1000000000-3 {
770 opp-hz = /bits/ 64 <10
771 opp-microvolt = <95000
772 opp-supported-hw = <0x
773 };
774
775 opp-1000000000-4 {
776 opp-hz = /bits/ 64 <10
777 opp-microvolt = <91250
778 opp-supported-hw = <0x
779 };
780
781 opp-1000000000-5 {
782 opp-hz = /bits/ 64 <10
783 opp-microvolt = <87500
784 opp-supported-hw = <0x
785 };
786 };
787
788 pmu-a55 {
789 compatible = "arm,cortex-a55-p
790 interrupt-parent = <&gic>;
791 interrupts = <GIC_PPI 7 IRQ_TY
792 };
793
794 pmu-a76 {
795 compatible = "arm,cortex-a76-p
796 interrupt-parent = <&gic>;
797 interrupts = <GIC_PPI 7 IRQ_TY
798 };
799
800 psci {
801 compatible = "arm,psci-1.0";
802 method = "smc";
803 };
804
805 timer {
806 compatible = "arm,armv8-timer"
807 interrupt-parent = <&gic>;
808 interrupts = <GIC_PPI 13 IRQ_T
809 <GIC_PPI 14 IRQ_T
810 <GIC_PPI 11 IRQ_T
811 <GIC_PPI 10 IRQ_T
812 };
813
814 soc {
815 #address-cells = <2>;
816 #size-cells = <2>;
817 compatible = "simple-bus";
818 dma-ranges = <0x0 0x0 0x0 0x0
819 ranges;
820
821 gic: interrupt-controller@c000
822 compatible = "arm,gic-
823 #interrupt-cells = <4>
824 #redistributor-regions
825 interrupt-parent = <&g
826 interrupt-controller;
827 reg = <0 0x0c000000 0
828 <0 0x0c040000 0
829 interrupts = <GIC_PPI
830
831 ppi-partitions {
832 ppi_cluster0:
833 affini
834 };
835
836 ppi_cluster1:
837 affini
838 };
839 };
840 };
841
842 mcusys: syscon@c53a000 {
843 compatible = "mediatek
844 reg = <0 0xc53a000 0 0
845 #clock-cells = <1>;
846 };
847
848 topckgen: syscon@10000000 {
849 compatible = "mediatek
850 reg = <0 0x10000000 0
851 #clock-cells = <1>;
852 };
853
854 infracfg_ao: syscon@10001000 {
855 compatible = "mediatek
856 reg = <0 0x10001000 0
857 #clock-cells = <1>;
858 #reset-cells = <1>;
859 };
860
861 pericfg: syscon@10003000 {
862 compatible = "mediatek
863 reg = <0 0x10003000 0
864 };
865
866 pio: pinctrl@10005000 {
867 compatible = "mediatek
868 reg = <0 0x10005000 0
869 <0 0x10002000 0
870 <0 0x10002200 0
871 <0 0x10002400 0
872 <0 0x10002600 0
873 <0 0x10002a00 0
874 <0 0x10002c00 0
875 <0 0x1000b000 0
876 reg-names = "iocfg0",
877 "iocfg_bl"
878 gpio-controller;
879 #gpio-cells = <2>;
880 gpio-ranges = <&pio 0
881 interrupt-controller;
882 interrupts = <GIC_SPI
883 #interrupt-cells = <2>
884 };
885
886 scpsys: syscon@10006000 {
887 compatible = "mediatek
888 reg = <0 0x10006000 0
889
890 /* System Power Manage
891 spm: power-controller
892 compatible = "
893 #address-cells
894 #size-cells =
895 #power-domain-
896
897 /* power domai
898 mfg0: power-do
899 reg =
900 clocks
901 clock-
902 #addre
903 #size-
904 #power
905
906 mfg1:
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922 };
923 };
924
925 power-domain@M
926 reg =
927 clocks
928
929 clock-
930
931 #power
932 };
933
934 power-domain@M
935 reg =
936 clocks
937
938 clock-
939 #power
940 };
941
942 power-domain@M
943 reg =
944 clocks
945
946 clock-
947 #power
948 };
949
950 power-domain@M
951 reg =
952 clocks
953
954 clock-
955
956 #addre
957 #size-
958 #power
959
960 power-
961
962
963
964
965
966
967
968
969
970
971 };
972 };
973
974 power-domain@M
975 reg =
976 mediat
977 #power
978 };
979
980 power-domain@M
981 reg =
982 clocks
983
984
985
986
987
988 clock-
989
990
991
992
993 mediat
994 #addre
995 #size-
996 #power
997
998 power-
999
1000
1001
1002
1003
1004
1005 };
1006
1007 power
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034 };
1035
1036 power
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050 };
1051
1052 power
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066 };
1067
1068 power
1069
1070
1071
1072
1073
1074
1075 };
1076
1077 power
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087 };
1088 };
1089 };
1090 };
1091
1092 watchdog: watchdog@10007000 {
1093 compatible = "mediate
1094 mediatek,disable-extr
1095 reg = <0 0x10007000 0
1096 #reset-cells = <1>;
1097 };
1098
1099 apmixedsys: syscon@1000c000 {
1100 compatible = "mediate
1101 reg = <0 0x1000c000 0
1102 #clock-cells = <1>;
1103 };
1104
1105 pwrap: pwrap@1000d000 {
1106 compatible = "mediate
1107 reg = <0 0x1000d000 0
1108 reg-names = "pwrap";
1109 interrupts = <GIC_SPI
1110 clocks = <&infracfg_a
1111 <&infracfg_a
1112 clock-names = "spi",
1113 };
1114
1115 spmi: spmi@10015000 {
1116 compatible = "mediate
1117 reg = <0 0x10015000 0
1118 reg-names = "pmif", "
1119 clocks = <&infracfg_a
1120 <&infracfg_a
1121 <&topckgen C
1122 clock-names = "pmif_s
1123 assigned-clocks = <&t
1124 assigned-clock-parent
1125 interrupts = <GIC_SPI
1126 <GIC_SPI
1127 status = "disabled";
1128 };
1129
1130 systimer: timer@10017000 {
1131 compatible = "mediate
1132 "mediate
1133 reg = <0 0x10017000 0
1134 interrupts = <GIC_SPI
1135 clocks = <&clk13m>;
1136 };
1137
1138 gce: mailbox@1022c000 {
1139 compatible = "mediate
1140 reg = <0 0X1022c000 0
1141 clocks = <&infracfg_a
1142 clock-names = "gce";
1143 interrupts = <GIC_SPI
1144 #mbox-cells = <2>;
1145 };
1146
1147 scp: scp@10500000 {
1148 compatible = "mediate
1149 reg = <0 0x10500000 0
1150 <0 0x105c0000 0
1151 reg-names = "sram", "
1152 interrupts = <GIC_SPI
1153 };
1154
1155 adsp: adsp@10680000 {
1156 compatible = "mediate
1157 reg = <0 0x10680000 0
1158 <0 0x1068b000 0
1159 reg-names = "cfg", "s
1160 clocks = <&topckgen C
1161 clock-names = "audiod
1162 assigned-clocks = <&t
1163 <&t
1164 assigned-clock-parent
1165 mbox-names = "rx", "t
1166 mboxes = <&adsp_mailb
1167 power-domains = <&spm
1168 status = "disabled";
1169 };
1170
1171 adsp_mailbox0: mailbox@106861
1172 compatible = "mediate
1173 #mbox-cells = <0>;
1174 reg = <0 0x10686100 0
1175 interrupts = <GIC_SPI
1176 };
1177
1178 adsp_mailbox1: mailbox@106871
1179 compatible = "mediate
1180 #mbox-cells = <0>;
1181 reg = <0 0x10687100 0
1182 interrupts = <GIC_SPI
1183 };
1184
1185 nor_flash: spi@11000000 {
1186 compatible = "mediate
1187 reg = <0 0x11000000 0
1188 clocks = <&topckgen C
1189 <&infracfg_a
1190 <&infracfg_a
1191 <&infracfg_a
1192 clock-names = "spi",
1193 assigned-clocks = <&t
1194 assigned-clock-parent
1195 interrupts = <GIC_SPI
1196 status = "disabled";
1197 };
1198
1199 auxadc: adc@11001000 {
1200 compatible = "mediate
1201 reg = <0 0x11001000 0
1202 #io-channel-cells = <
1203 clocks = <&infracfg_a
1204 clock-names = "main";
1205 };
1206
1207 uart0: serial@11002000 {
1208 compatible = "mediate
1209 "mediate
1210 reg = <0 0x11002000 0
1211 interrupts = <GIC_SPI
1212 clocks = <&clk26m>, <
1213 clock-names = "baud",
1214 status = "disabled";
1215 };
1216
1217 uart1: serial@11003000 {
1218 compatible = "mediate
1219 "mediate
1220 reg = <0 0x11003000 0
1221 interrupts = <GIC_SPI
1222 clocks = <&clk26m>, <
1223 clock-names = "baud",
1224 status = "disabled";
1225 };
1226
1227 i2c0: i2c@11007000 {
1228 compatible = "mediate
1229 reg = <0 0x11007000 0
1230 <0 0x10200100 0
1231 interrupts = <GIC_SPI
1232 clocks = <&imp_iic_wr
1233 <&infracfg_a
1234 clock-names = "main",
1235 clock-div = <1>;
1236 #address-cells = <1>;
1237 #size-cells = <0>;
1238 status = "disabled";
1239 };
1240
1241 i2c1: i2c@11008000 {
1242 compatible = "mediate
1243 reg = <0 0x11008000 0
1244 <0 0x10200200 0
1245 interrupts = <GIC_SPI
1246 clocks = <&imp_iic_wr
1247 <&infracfg_a
1248 clock-names = "main",
1249 clock-div = <1>;
1250 #address-cells = <1>;
1251 #size-cells = <0>;
1252 status = "disabled";
1253 };
1254
1255 i2c2: i2c@11009000 {
1256 compatible = "mediate
1257 reg = <0 0x11009000 0
1258 <0 0x10200300 0
1259 interrupts = <GIC_SPI
1260 clocks = <&imp_iic_wr
1261 <&infracfg_a
1262 clock-names = "main",
1263 clock-div = <1>;
1264 #address-cells = <1>;
1265 #size-cells = <0>;
1266 status = "disabled";
1267 };
1268
1269 i2c3: i2c@1100f000 {
1270 compatible = "mediate
1271 reg = <0 0x1100f000 0
1272 <0 0x10200480 0
1273 interrupts = <GIC_SPI
1274 clocks = <&imp_iic_wr
1275 <&infracfg_a
1276 clock-names = "main",
1277 clock-div = <1>;
1278 #address-cells = <1>;
1279 #size-cells = <0>;
1280 status = "disabled";
1281 };
1282
1283 i2c4: i2c@11011000 {
1284 compatible = "mediate
1285 reg = <0 0x11011000 0
1286 <0 0x10200580 0
1287 interrupts = <GIC_SPI
1288 clocks = <&imp_iic_wr
1289 <&infracfg_a
1290 clock-names = "main",
1291 clock-div = <1>;
1292 #address-cells = <1>;
1293 #size-cells = <0>;
1294 status = "disabled";
1295 };
1296
1297 i2c5: i2c@11016000 {
1298 compatible = "mediate
1299 reg = <0 0x11016000 0
1300 <0 0x10200700 0
1301 interrupts = <GIC_SPI
1302 clocks = <&imp_iic_wr
1303 <&infracfg_a
1304 clock-names = "main",
1305 clock-div = <1>;
1306 #address-cells = <1>;
1307 #size-cells = <0>;
1308 status = "disabled";
1309 };
1310
1311 i2c6: i2c@1100d000 {
1312 compatible = "mediate
1313 reg = <0 0x1100d000 0
1314 <0 0x10200800 0
1315 interrupts = <GIC_SPI
1316 clocks = <&imp_iic_wr
1317 <&infracfg_a
1318 clock-names = "main",
1319 clock-div = <1>;
1320 #address-cells = <1>;
1321 #size-cells = <0>;
1322 status = "disabled";
1323 };
1324
1325 i2c7: i2c@11004000 {
1326 compatible = "mediate
1327 reg = <0 0x11004000 0
1328 <0 0x10200900 0
1329 interrupts = <GIC_SPI
1330 clocks = <&imp_iic_wr
1331 <&infracfg_a
1332 clock-names = "main",
1333 clock-div = <1>;
1334 #address-cells = <1>;
1335 #size-cells = <0>;
1336 status = "disabled";
1337 };
1338
1339 i2c8: i2c@11005000 {
1340 compatible = "mediate
1341 reg = <0 0x11005000 0
1342 <0 0x10200A80 0
1343 interrupts = <GIC_SPI
1344 clocks = <&imp_iic_wr
1345 <&infracfg_a
1346 clock-names = "main",
1347 clock-div = <1>;
1348 #address-cells = <1>;
1349 #size-cells = <0>;
1350 status = "disabled";
1351 };
1352
1353 spi0: spi@1100a000 {
1354 compatible = "mediate
1355 #address-cells = <1>;
1356 #size-cells = <0>;
1357 reg = <0 0x1100a000 0
1358 interrupts = <GIC_SPI
1359 clocks = <&topckgen C
1360 <&topckgen C
1361 <&infracfg_a
1362 clock-names = "parent
1363 status = "disabled";
1364 };
1365
1366 lvts: thermal-sensor@1100b000
1367 compatible = "mediate
1368 reg = <0 0x1100b000 0
1369 interrupts = <GIC_SPI
1370 clocks = <&infracfg_a
1371 resets = <&infracfg_a
1372 nvmem-cells = <&lvts_
1373 nvmem-cell-names = "l
1374 #thermal-sensor-cells
1375 };
1376
1377 svs: svs@1100bc00 {
1378 compatible = "mediate
1379 reg = <0 0x1100bc00 0
1380 interrupts = <GIC_SPI
1381 clocks = <&infracfg_a
1382 clock-names = "main";
1383 nvmem-cells = <&svs_c
1384 nvmem-cell-names = "s
1385 resets = <&infracfg_a
1386 reset-names = "svs_rs
1387 };
1388
1389 pwm0: pwm@1100e000 {
1390 compatible = "mediate
1391 reg = <0 0x1100e000 0
1392 interrupts = <GIC_SPI
1393 #pwm-cells = <2>;
1394 clocks = <&topckgen C
1395 <&infracfg_a
1396 clock-names = "main",
1397 status = "disabled";
1398 };
1399
1400 spi1: spi@11010000 {
1401 compatible = "mediate
1402 #address-cells = <1>;
1403 #size-cells = <0>;
1404 reg = <0 0x11010000 0
1405 interrupts = <GIC_SPI
1406 clocks = <&topckgen C
1407 <&topckgen C
1408 <&infracfg_a
1409 clock-names = "parent
1410 status = "disabled";
1411 };
1412
1413 spi2: spi@11012000 {
1414 compatible = "mediate
1415 #address-cells = <1>;
1416 #size-cells = <0>;
1417 reg = <0 0x11012000 0
1418 interrupts = <GIC_SPI
1419 clocks = <&topckgen C
1420 <&topckgen C
1421 <&infracfg_a
1422 clock-names = "parent
1423 status = "disabled";
1424 };
1425
1426 spi3: spi@11013000 {
1427 compatible = "mediate
1428 #address-cells = <1>;
1429 #size-cells = <0>;
1430 reg = <0 0x11013000 0
1431 interrupts = <GIC_SPI
1432 clocks = <&topckgen C
1433 <&topckgen C
1434 <&infracfg_a
1435 clock-names = "parent
1436 status = "disabled";
1437 };
1438
1439 spi4: spi@11014000 {
1440 compatible = "mediate
1441 #address-cells = <1>;
1442 #size-cells = <0>;
1443 reg = <0 0x11014000 0
1444 interrupts = <GIC_SPI
1445 clocks = <&topckgen C
1446 <&topckgen C
1447 <&infracfg_a
1448 clock-names = "parent
1449 status = "disabled";
1450 };
1451
1452 spi5: spi@11015000 {
1453 compatible = "mediate
1454 #address-cells = <1>;
1455 #size-cells = <0>;
1456 reg = <0 0x11015000 0
1457 interrupts = <GIC_SPI
1458 clocks = <&topckgen C
1459 <&topckgen C
1460 <&infracfg_a
1461 clock-names = "parent
1462 status = "disabled";
1463 };
1464
1465 imp_iic_wrap: clock-controlle
1466 compatible = "mediate
1467 reg = <0 0x11017000 0
1468 #clock-cells = <1>;
1469 };
1470
1471 uart2: serial@11018000 {
1472 compatible = "mediate
1473 "mediate
1474 reg = <0 0x11018000 0
1475 interrupts = <GIC_SPI
1476 clocks = <&clk26m>, <
1477 clock-names = "baud",
1478 status = "disabled";
1479 };
1480
1481 i2c9: i2c@11019000 {
1482 compatible = "mediate
1483 reg = <0 0x11019000 0
1484 <0 0x10200c00 0
1485 interrupts = <GIC_SPI
1486 clocks = <&imp_iic_wr
1487 <&infracfg_a
1488 clock-names = "main",
1489 clock-div = <1>;
1490 #address-cells = <1>;
1491 #size-cells = <0>;
1492 status = "disabled";
1493 };
1494
1495 afe: audio-controller@1121000
1496 compatible = "mediate
1497 reg = <0 0x11210000 0
1498 clocks = <&infracfg_a
1499 <&infracfg_a
1500 <&topckgen C
1501 <&topckgen C
1502 <&topckgen C
1503 <&topckgen C
1504 <&apmixedsys
1505 <&topckgen C
1506 <&apmixedsys
1507 <&topckgen C
1508 <&topckgen C
1509 <&topckgen C
1510 <&topckgen C
1511 <&topckgen C
1512 <&topckgen C
1513 <&topckgen C
1514 <&topckgen C
1515 <&topckgen C
1516 <&topckgen C
1517 <&topckgen C
1518 <&topckgen C
1519 <&topckgen C
1520 <&topckgen C
1521 <&topckgen C
1522 <&clk26m>;
1523 clock-names = "aud_in
1524 "mtkaif
1525 "top_mu
1526 "top_mu
1527 "top_ma
1528 "top_mu
1529 "top_ap
1530 "top_mu
1531 "top_ap
1532 "top_mu
1533 "top_ap
1534 "top_mu
1535 "top_ap
1536 "top_i2
1537 "top_i2
1538 "top_i2
1539 "top_i2
1540 "top_td
1541 "top_ap
1542 "top_ap
1543 "top_ap
1544 "top_ap
1545 "top_ap
1546 "top_mu
1547 "top_cl
1548 interrupts = <GIC_SPI
1549 mediatek,apmixedsys =
1550 mediatek,infracfg = <
1551 mediatek,topckgen = <
1552 resets = <&watchdog M
1553 reset-names = "audios
1554 status = "disabled";
1555 };
1556
1557 ssusb0: usb@11201000 {
1558 compatible = "mediate
1559 reg = <0 0x11201000 0
1560 reg-names = "mac", "i
1561 clocks = <&topckgen C
1562 <&infracfg_a
1563 <&infracfg_a
1564 <&infracfg_a
1565 <&infracfg_a
1566 clock-names = "sys_ck
1567 interrupts = <GIC_SPI
1568 phys = <&u2port0 PHY_
1569 power-domains = <&spm
1570 #address-cells = <2>;
1571 #size-cells = <2>;
1572 ranges;
1573 status = "disabled";
1574
1575 usb_host0: usb@112000
1576 compatible =
1577 reg = <0 0x11
1578 reg-names = "
1579 clocks = <&to
1580 <&in
1581 <&in
1582 <&in
1583 <&in
1584 clock-names =
1585 interrupts =
1586 mediatek,sysc
1587 wakeup-source
1588 status = "dis
1589 };
1590 };
1591
1592 mmc0: mmc@11230000 {
1593 compatible = "mediate
1594 "mediate
1595 reg = <0 0x11230000 0
1596 <0 0x11cd0000 0
1597 clocks = <&topckgen C
1598 <&infracfg_a
1599 <&infracfg_a
1600 <&infracfg_a
1601 clock-names = "source
1602 interrupts = <GIC_SPI
1603 assigned-clocks = <&t
1604 assigned-clock-parent
1605 status = "disabled";
1606 };
1607
1608 mmc1: mmc@11240000 {
1609 compatible = "mediate
1610 "mediate
1611 reg = <0 0x11240000 0
1612 <0 0x11c90000 0
1613 clocks = <&topckgen C
1614 <&infracfg_a
1615 <&infracfg_a
1616 clock-names = "source
1617 interrupts = <GIC_SPI
1618 assigned-clocks = <&t
1619 assigned-clock-parent
1620 status = "disabled";
1621 };
1622
1623 ssusb1: usb@11281000 {
1624 compatible = "mediate
1625 reg = <0 0x11281000 0
1626 reg-names = "mac", "i
1627 clocks = <&infracfg_a
1628 <&infracfg_a
1629 <&infracfg_a
1630 <&clk26m>,
1631 <&infracfg_a
1632 clock-names = "sys_ck
1633 interrupts = <GIC_SPI
1634 phys = <&u2port1 PHY_
1635 power-domains = <&spm
1636 #address-cells = <2>;
1637 #size-cells = <2>;
1638 ranges;
1639 status = "disabled";
1640
1641 usb_host1: usb@112800
1642 compatible =
1643 reg = <0 0x11
1644 reg-names = "
1645 clocks = <&in
1646 <&in
1647 <&in
1648 <&cl
1649 <&in
1650 clock-names =
1651 interrupts =
1652 mediatek,sysc
1653 wakeup-source
1654 status = "dis
1655 };
1656 };
1657
1658 u3phy0: t-phy@11c80000 {
1659 compatible = "mediate
1660 "mediate
1661 #address-cells = <1>;
1662 #size-cells = <1>;
1663 ranges = <0x0 0x0 0x1
1664 status = "disabled";
1665
1666 u2port1: usb-phy@0 {
1667 reg = <0x0 0x
1668 clocks = <&cl
1669 clock-names =
1670 #phy-cells =
1671 };
1672
1673 u3port1: usb-phy@700
1674 reg = <0x700
1675 clocks = <&cl
1676 clock-names =
1677 #phy-cells =
1678 };
1679 };
1680
1681 u3phy1: t-phy@11ca0000 {
1682 compatible = "mediate
1683 "mediate
1684 #address-cells = <1>;
1685 #size-cells = <1>;
1686 ranges = <0x0 0x0 0x1
1687 status = "disabled";
1688
1689 u2port0: usb-phy@0 {
1690 reg = <0x0 0x
1691 clocks = <&cl
1692 clock-names =
1693 #phy-cells =
1694 mediatek,disc
1695 };
1696 };
1697
1698 efuse: efuse@11cb0000 {
1699 compatible = "mediate
1700 reg = <0 0x11cb0000 0
1701 #address-cells = <1>;
1702 #size-cells = <1>;
1703
1704 lvts_efuse_data1: lvt
1705 reg = <0x1cc
1706 };
1707
1708 lvts_efuse_data2: lvt
1709 reg = <0x2f8
1710 };
1711
1712 svs_calibration: cali
1713 reg = <0x550
1714 };
1715
1716 gpu_speedbin: gpu-spe
1717 reg = <0x59c
1718 bits = <0 3>;
1719 };
1720
1721 socinfo-data1@7a0 {
1722 reg = <0x7a0
1723 };
1724 };
1725
1726 mipi_tx0: dsi-phy@11cc0000 {
1727 compatible = "mediate
1728 reg = <0 0x11cc0000 0
1729 clocks = <&clk26m>;
1730 #clock-cells = <0>;
1731 #phy-cells = <0>;
1732 clock-output-names =
1733 status = "disabled";
1734 };
1735
1736 mfgsys: clock-controller@1300
1737 compatible = "mediate
1738 reg = <0 0x13000000 0
1739 #clock-cells = <1>;
1740 };
1741
1742 gpu: gpu@13040000 {
1743 compatible = "mediate
1744 "arm,mal
1745 reg = <0 0x13040000 0
1746
1747 clocks = <&mfgsys CLK
1748 interrupts = <GIC_SPI
1749 <GIC_SPI
1750 <GIC_SPI
1751 interrupt-names = "jo
1752 power-domains = <&spm
1753 <&spm
1754 power-domain-names =
1755 #cooling-cells = <2>;
1756 nvmem-cells = <&gpu_s
1757 nvmem-cell-names = "s
1758 operating-points-v2 =
1759 dynamic-power-coeffic
1760 status = "disabled";
1761 };
1762
1763 mmsys: syscon@14000000 {
1764 compatible = "mediate
1765 reg = <0 0x14000000 0
1766 #clock-cells = <1>;
1767 #reset-cells = <1>;
1768 mboxes = <&gce 0 CMDQ
1769 <&gce 1 CMDQ
1770 mediatek,gce-client-r
1771 };
1772
1773 mutex: mutex@14001000 {
1774 compatible = "mediate
1775 reg = <0 0x14001000 0
1776 clocks = <&mmsys CLK_
1777 interrupts = <GIC_SPI
1778 mediatek,gce-client-r
1779 mediatek,gce-events =
1780
1781 power-domains = <&spm
1782 };
1783
1784 smi_common: smi@14002000 {
1785 compatible = "mediate
1786 reg = <0 0x14002000 0
1787 clocks = <&mmsys CLK_
1788 <&mmsys CLK_
1789 clock-names = "apb",
1790 power-domains = <&spm
1791 };
1792
1793 larb0: smi@14003000 {
1794 compatible = "mediate
1795 reg = <0 0x14003000 0
1796 clocks = <&mmsys CLK_
1797 <&mmsys CLK_
1798 clock-names = "apb",
1799 mediatek,larb-id = <0
1800 mediatek,smi = <&smi_
1801 power-domains = <&spm
1802 };
1803
1804 larb1: smi@14004000 {
1805 compatible = "mediate
1806 reg = <0 0x14004000 0
1807 clocks = <&mmsys CLK_
1808 <&mmsys CLK_
1809 clock-names = "apb",
1810 mediatek,larb-id = <1
1811 mediatek,smi = <&smi_
1812 power-domains = <&spm
1813 };
1814
1815 ovl0: ovl@14005000 {
1816 compatible = "mediate
1817 reg = <0 0x14005000 0
1818 clocks = <&mmsys CLK_
1819 interrupts = <GIC_SPI
1820 iommus = <&iommu_mm I
1821 mediatek,gce-client-r
1822 power-domains = <&spm
1823 };
1824
1825 ovl_2l0: ovl@14006000 {
1826 compatible = "mediate
1827 reg = <0 0x14006000 0
1828 clocks = <&mmsys CLK_
1829 interrupts = <GIC_SPI
1830 iommus = <&iommu_mm I
1831 mediatek,gce-client-r
1832 power-domains = <&spm
1833 };
1834
1835 rdma0: rdma@14007000 {
1836 compatible = "mediate
1837 reg = <0 0x14007000 0
1838 clocks = <&mmsys CLK_
1839 interrupts = <GIC_SPI
1840 iommus = <&iommu_mm I
1841 mediatek,gce-client-r
1842 power-domains = <&spm
1843 };
1844
1845 color: color@14009000 {
1846 compatible = "mediate
1847 reg = <0 0x14009000 0
1848 clocks = <&mmsys CLK_
1849 interrupts = <GIC_SPI
1850 mediatek,gce-client-r
1851 power-domains = <&spm
1852 };
1853
1854 dpi: dpi@1400a000 {
1855 compatible = "mediate
1856 reg = <0 0x1400a000 0
1857 clocks = <&topckgen C
1858 <&mmsys CLK_
1859 <&apmixedsys
1860 clock-names = "pixel"
1861 assigned-clocks = <&t
1862 assigned-clock-parent
1863 interrupts = <GIC_SPI
1864 power-domains = <&spm
1865 status = "disabled";
1866
1867 port {
1868 dpi_out: endp
1869 };
1870 };
1871
1872 ccorr: ccorr@1400b000 {
1873 compatible = "mediate
1874 reg = <0 0x1400b000 0
1875 clocks = <&mmsys CLK_
1876 interrupts = <GIC_SPI
1877 mediatek,gce-client-r
1878 power-domains = <&spm
1879 };
1880
1881 aal: aal@1400c000 {
1882 compatible = "mediate
1883 reg = <0 0x1400c000 0
1884 clocks = <&mmsys CLK_
1885 interrupts = <GIC_SPI
1886 mediatek,gce-client-r
1887 power-domains = <&spm
1888 };
1889
1890 gamma: gamma@1400d000 {
1891 compatible = "mediate
1892 reg = <0 0x1400d000 0
1893 clocks = <&mmsys CLK_
1894 interrupts = <GIC_SPI
1895 mediatek,gce-client-r
1896 power-domains = <&spm
1897 };
1898
1899 postmask: postmask@1400e000 {
1900 compatible = "mediate
1901 "mediate
1902 reg = <0 0x1400e000 0
1903 clocks = <&mmsys CLK_
1904 interrupts = <GIC_SPI
1905 mediatek,gce-client-r
1906 power-domains = <&spm
1907 };
1908
1909 dither: dither@1400f000 {
1910 compatible = "mediate
1911 reg = <0 0x1400f000 0
1912 clocks = <&mmsys CLK_
1913 interrupts = <GIC_SPI
1914 mediatek,gce-client-r
1915 power-domains = <&spm
1916 };
1917
1918 dsi0: dsi@14013000 {
1919 compatible = "mediate
1920 reg = <0 0x14013000 0
1921 clocks = <&mmsys CLK_
1922 <&mmsys CLK_
1923 <&mipi_tx0>;
1924 clock-names = "engine
1925 interrupts = <GIC_SPI
1926 power-domains = <&spm
1927 resets = <&mmsys MT81
1928 phys = <&mipi_tx0>;
1929 phy-names = "dphy";
1930 status = "disabled";
1931
1932 port {
1933 dsi_out: endp
1934 };
1935 };
1936
1937 iommu_mm: iommu@14016000 {
1938 compatible = "mediate
1939 reg = <0 0x14016000 0
1940 clocks = <&mmsys CLK_
1941 clock-names = "bclk";
1942 interrupts = <GIC_SPI
1943 mediatek,larbs = <&la
1944 &la
1945 &la
1946 &la
1947 power-domains = <&spm
1948 #iommu-cells = <1>;
1949 };
1950
1951 rdma1: rdma@1401f000 {
1952 compatible = "mediate
1953 reg = <0 0x1401f000 0
1954 clocks = <&mmsys CLK_
1955 interrupts = <GIC_SPI
1956 iommus = <&iommu_mm I
1957 mediatek,gce-client-r
1958 power-domains = <&spm
1959 };
1960
1961 wpesys: clock-controller@1402
1962 compatible = "mediate
1963 reg = <0 0x14020000 0
1964 #clock-cells = <1>;
1965 };
1966
1967 larb8: smi@14023000 {
1968 compatible = "mediate
1969 reg = <0 0x14023000 0
1970 clocks = <&wpesys CLK
1971 <&wpesys CLK
1972 clock-names = "apb",
1973 mediatek,larb-id = <8
1974 mediatek,smi = <&smi_
1975 power-domains = <&spm
1976 };
1977
1978 imgsys1: clock-controller@150
1979 compatible = "mediate
1980 reg = <0 0x15020000 0
1981 #clock-cells = <1>;
1982 };
1983
1984 larb9: smi@1502e000 {
1985 compatible = "mediate
1986 reg = <0 0x1502e000 0
1987 clocks = <&imgsys1 CL
1988 <&imgsys1 CL
1989 clock-names = "apb",
1990 mediatek,larb-id = <9
1991 mediatek,smi = <&smi_
1992 power-domains = <&spm
1993 };
1994
1995 imgsys2: clock-controller@158
1996 compatible = "mediate
1997 reg = <0 0x15820000 0
1998 #clock-cells = <1>;
1999 };
2000
2001 larb11: smi@1582e000 {
2002 compatible = "mediate
2003 reg = <0 0x1582e000 0
2004 clocks = <&imgsys1 CL
2005 <&imgsys2 CL
2006 clock-names = "apb",
2007 mediatek,larb-id = <1
2008 mediatek,smi = <&smi_
2009 power-domains = <&spm
2010 };
2011
2012 video_decoder: video-decoder@
2013 compatible = "mediate
2014 reg = <0 0x16000000 0
2015 ranges;
2016 #address-cells = <2>;
2017 #size-cells = <2>;
2018 dma-ranges = <0x1 0x0
2019 iommus = <&iommu_mm I
2020 mediatek,scp = <&scp>
2021
2022 vcodec_core: video-co
2023 compatible =
2024 reg = <0 0x16
2025 interrupts =
2026 iommus = <&io
2027 <&io
2028 <&io
2029 <&io
2030 <&io
2031 <&io
2032 <&io
2033 <&io
2034 <&io
2035 <&io
2036 <&io
2037 <&io
2038 clocks = <&to
2039 <&vd
2040 <&vd
2041 <&to
2042 clock-names =
2043 assigned-cloc
2044 assigned-cloc
2045 power-domains
2046 };
2047 };
2048
2049 larb4: smi@1602e000 {
2050 compatible = "mediate
2051 reg = <0 0x1602e000 0
2052 clocks = <&vdecsys CL
2053 <&vdecsys CL
2054 clock-names = "apb",
2055 mediatek,larb-id = <4
2056 mediatek,smi = <&smi_
2057 power-domains = <&spm
2058 };
2059
2060 vdecsys: clock-controller@160
2061 compatible = "mediate
2062 reg = <0 0x1602f000 0
2063 #clock-cells = <1>;
2064 };
2065
2066 vencsys: clock-controller@170
2067 compatible = "mediate
2068 reg = <0 0x17000000 0
2069 #clock-cells = <1>;
2070 };
2071
2072 larb7: smi@17010000 {
2073 compatible = "mediate
2074 reg = <0 0x17010000 0
2075 clocks = <&vencsys CL
2076 <&vencsys CL
2077 clock-names = "apb",
2078 mediatek,larb-id = <7
2079 mediatek,smi = <&smi_
2080 power-domains = <&spm
2081 };
2082
2083 venc: video-encoder@17020000
2084 compatible = "mediate
2085 reg = <0 0x17020000 0
2086 interrupts = <GIC_SPI
2087 iommus = <&iommu_mm I
2088 <&iommu_mm I
2089 <&iommu_mm I
2090 <&iommu_mm I
2091 <&iommu_mm I
2092 <&iommu_mm I
2093 <&iommu_mm I
2094 <&iommu_mm I
2095 <&iommu_mm I
2096 clocks = <&vencsys CL
2097 clock-names = "venc_s
2098 assigned-clocks = <&t
2099 assigned-clock-parent
2100 power-domains = <&spm
2101 mediatek,scp = <&scp>
2102 };
2103
2104 jpgenc: jpeg-encoder@17030000
2105 compatible = "mediate
2106 reg = <0 0x17030000 0
2107 interrupts = <GIC_SPI
2108 clocks = <&vencsys CL
2109 clock-names = "jpgenc
2110 iommus = <&iommu_mm I
2111 <&iommu_mm I
2112 <&iommu_mm I
2113 <&iommu_mm I
2114 power-domains = <&spm
2115 };
2116
2117 camsys: clock-controller@1a00
2118 compatible = "mediate
2119 reg = <0 0x1a000000 0
2120 #clock-cells = <1>;
2121 };
2122
2123 larb13: smi@1a001000 {
2124 compatible = "mediate
2125 reg = <0 0x1a001000 0
2126 clocks = <&camsys CLK
2127 clock-names = "apb",
2128 mediatek,larb-id = <1
2129 mediatek,smi = <&smi_
2130 power-domains = <&spm
2131 };
2132
2133 larb14: smi@1a002000 {
2134 compatible = "mediate
2135 reg = <0 0x1a002000 0
2136 clocks = <&camsys CLK
2137 clock-names = "apb",
2138 mediatek,larb-id = <1
2139 mediatek,smi = <&smi_
2140 power-domains = <&spm
2141 };
2142
2143 larb16: smi@1a00f000 {
2144 compatible = "mediate
2145 reg = <0 0x1a00f000 0
2146 clocks = <&camsys CLK
2147 <&camsys_raw
2148 clock-names = "apb",
2149 mediatek,larb-id = <1
2150 mediatek,smi = <&smi_
2151 power-domains = <&spm
2152 };
2153
2154 larb17: smi@1a010000 {
2155 compatible = "mediate
2156 reg = <0 0x1a010000 0
2157 clocks = <&camsys CLK
2158 <&camsys_raw
2159 clock-names = "apb",
2160 mediatek,larb-id = <1
2161 mediatek,smi = <&smi_
2162 power-domains = <&spm
2163 };
2164
2165 camsys_rawa: clock-controller
2166 compatible = "mediate
2167 reg = <0 0x1a04f000 0
2168 #clock-cells = <1>;
2169 };
2170
2171 camsys_rawb: clock-controller
2172 compatible = "mediate
2173 reg = <0 0x1a06f000 0
2174 #clock-cells = <1>;
2175 };
2176
2177 mdpsys: clock-controller@1b00
2178 compatible = "mediate
2179 reg = <0 0x1b000000 0
2180 #clock-cells = <1>;
2181 };
2182
2183 larb2: smi@1b002000 {
2184 compatible = "mediate
2185 reg = <0 0x1b002000 0
2186 clocks = <&mdpsys CLK
2187 clock-names = "apb",
2188 mediatek,larb-id = <2
2189 mediatek,smi = <&smi_
2190 power-domains = <&spm
2191 };
2192
2193 ipesys: clock-controller@1c00
2194 compatible = "mediate
2195 reg = <0 0x1c000000 0
2196 #clock-cells = <1>;
2197 };
2198
2199 larb20: smi@1c00f000 {
2200 compatible = "mediate
2201 reg = <0 0x1c00f000 0
2202 clocks = <&ipesys CLK
2203 clock-names = "apb",
2204 mediatek,larb-id = <2
2205 mediatek,smi = <&smi_
2206 power-domains = <&spm
2207 };
2208
2209 larb19: smi@1c10f000 {
2210 compatible = "mediate
2211 reg = <0 0x1c10f000 0
2212 clocks = <&ipesys CLK
2213 clock-names = "apb",
2214 mediatek,larb-id = <1
2215 mediatek,smi = <&smi_
2216 power-domains = <&spm
2217 };
2218 };
2219
2220 thermal_zones: thermal-zones {
2221 cpu-little0-thermal {
2222 polling-delay = <1000
2223 polling-delay-passive
2224 thermal-sensors = <&l
2225
2226 trips {
2227 cpu_little0_a
2228 tempe
2229 hyste
2230 type
2231 };
2232
2233 cpu_little0_a
2234 tempe
2235 hyste
2236 type
2237 };
2238
2239 cpu_little0_c
2240 tempe
2241 hyste
2242 type
2243 };
2244 };
2245
2246 cooling-maps {
2247 map0 {
2248 trip
2249 cooli
2250
2251
2252
2253
2254
2255 };
2256 };
2257 };
2258
2259 cpu-little1-thermal {
2260 polling-delay = <1000
2261 polling-delay-passive
2262 thermal-sensors = <&l
2263
2264 trips {
2265 cpu_little1_a
2266 tempe
2267 hyste
2268 type
2269 };
2270
2271 cpu_little1_a
2272 tempe
2273 hyste
2274 type
2275 };
2276
2277 cpu_little1_c
2278 tempe
2279 hyste
2280 type
2281 };
2282 };
2283
2284 cooling-maps {
2285 map0 {
2286 trip
2287 cooli
2288
2289
2290
2291
2292
2293 };
2294 };
2295 };
2296
2297 cpu-little2-thermal {
2298 polling-delay = <1000
2299 polling-delay-passive
2300 thermal-sensors = <&l
2301
2302 trips {
2303 cpu_little2_a
2304 tempe
2305 hyste
2306 type
2307 };
2308
2309 cpu_little2_a
2310 tempe
2311 hyste
2312 type
2313 };
2314
2315 cpu_little2_c
2316 tempe
2317 hyste
2318 type
2319 };
2320 };
2321
2322 cooling-maps {
2323 map0 {
2324 trip
2325 cooli
2326
2327
2328
2329
2330
2331 };
2332 };
2333 };
2334
2335 cam-thermal {
2336 polling-delay = <1000
2337 polling-delay-passive
2338 thermal-sensors = <&l
2339
2340 trips {
2341 cam_alert0: t
2342 tempe
2343 hyste
2344 type
2345 };
2346
2347 cam_alert1: t
2348 tempe
2349 hyste
2350 type
2351 };
2352
2353 cam_crit: tri
2354 tempe
2355 hyste
2356 type
2357 };
2358 };
2359 };
2360
2361 nna-thermal {
2362 polling-delay = <1000
2363 polling-delay-passive
2364 thermal-sensors = <&l
2365
2366 trips {
2367 nna_alert0: t
2368 tempe
2369 hyste
2370 type
2371 };
2372
2373 nna_alert1: t
2374 tempe
2375 hyste
2376 type
2377 };
2378
2379 nna_crit: tri
2380 tempe
2381 hyste
2382 type
2383 };
2384 };
2385 };
2386
2387 adsp-thermal {
2388 polling-delay = <1000
2389 polling-delay-passive
2390 thermal-sensors = <&l
2391
2392 trips {
2393 adsp_alert0:
2394 tempe
2395 hyste
2396 type
2397 };
2398
2399 adsp_alert1:
2400 tempe
2401 hyste
2402 type
2403 };
2404
2405 adsp_crit: tr
2406 tempe
2407 hyste
2408 type
2409 };
2410 };
2411 };
2412
2413 gpu-thermal {
2414 polling-delay = <1000
2415 polling-delay-passive
2416 thermal-sensors = <&l
2417
2418 trips {
2419 gpu_alert0: t
2420 tempe
2421 hyste
2422 type
2423 };
2424
2425 gpu_alert1: t
2426 tempe
2427 hyste
2428 type
2429 };
2430
2431 gpu_crit: tri
2432 tempe
2433 hyste
2434 type
2435 };
2436 };
2437
2438 cooling-maps {
2439 map0 {
2440 trip
2441 cooli
2442 };
2443 };
2444 };
2445
2446 cpu-big0-thermal {
2447 polling-delay = <1000
2448 polling-delay-passive
2449 thermal-sensors = <&l
2450
2451 trips {
2452 cpu_big0_aler
2453 tempe
2454 hyste
2455 type
2456 };
2457
2458 cpu_big0_aler
2459 tempe
2460 hyste
2461 type
2462 };
2463
2464 cpu_big0_crit
2465 tempe
2466 hyste
2467 type
2468 };
2469 };
2470
2471 cooling-maps {
2472 map0 {
2473 trip
2474 cooli
2475
2476 };
2477 };
2478 };
2479
2480 cpu-big1-thermal {
2481 polling-delay = <1000
2482 polling-delay-passive
2483 thermal-sensors = <&l
2484
2485 trips {
2486 cpu_big1_aler
2487 tempe
2488 hyste
2489 type
2490 };
2491
2492 cpu_big1_aler
2493 tempe
2494 hyste
2495 type
2496 };
2497
2498 cpu_big1_crit
2499 tempe
2500 hyste
2501 type
2502 };
2503 };
2504
2505 cooling-maps {
2506 map0 {
2507 trip
2508 cooli
2509
2510 };
2511 };
2512 };
2513 };
2514 };
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