1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /*
3 * Copyright (C) 2020 MediaTek Inc.
4 * Author: Seiya Wang <seiya.wang@mediatek.com>
5 */
6 /dts-v1/;
7 #include "mt8192.dtsi"
8 #include "mt6359.dtsi"
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/spmi/spmi.h>
11
12 / {
13 aliases {
14 i2c0 = &i2c0;
15 i2c1 = &i2c1;
16 i2c2 = &i2c2;
17 i2c3 = &i2c3;
18 i2c7 = &i2c7;
19 mmc0 = &mmc0;
20 mmc1 = &mmc1;
21 serial0 = &uart0;
22 };
23
24 chosen {
25 stdout-path = "serial0:115200n
26 };
27
28 memory@40000000 {
29 device_type = "memory";
30 reg = <0 0x40000000 0 0x800000
31 };
32
33 backlight_lcd0: backlight-lcd0 {
34 compatible = "pwm-backlight";
35 pwms = <&pwm0 0 500000>;
36 power-supply = <&ppvar_sys>;
37 enable-gpios = <&pio 152 0>;
38 brightness-levels = <0 1023>;
39 num-interpolated-steps = <1023
40 default-brightness-level = <57
41 };
42
43 dmic_codec: dmic-codec {
44 compatible = "dmic-codec";
45 num-channels = <2>;
46 wakeup-delay-ms = <50>;
47 };
48
49 pp1000_dpbrdg: regulator-1v0-dpbrdg {
50 compatible = "regulator-fixed"
51 regulator-name = "pp1000_dpbrd
52 pinctrl-names = "default";
53 pinctrl-0 = <&pp1000_dpbrdg_en
54 regulator-min-microvolt = <100
55 regulator-max-microvolt = <100
56 enable-active-high;
57 regulator-boot-on;
58 gpio = <&pio 19 GPIO_ACTIVE_HI
59 vin-supply = <&mt6359_vs2_buck
60 };
61
62 pp1000_mipibrdg: regulator-1v0-mipibrd
63 compatible = "regulator-fixed"
64 regulator-name = "pp1000_mipib
65 pinctrl-names = "default";
66 pinctrl-0 = <&pp1000_mipibrdg_
67 regulator-min-microvolt = <100
68 regulator-max-microvolt = <100
69 enable-active-high;
70 regulator-boot-on;
71 gpio = <&pio 129 GPIO_ACTIVE_H
72 vin-supply = <&mt6359_vs2_buck
73 };
74
75 pp1800_dpbrdg: regulator-1v8-dpbrdg {
76 compatible = "regulator-fixed"
77 regulator-name = "pp1800_dpbrd
78 pinctrl-names = "default";
79 pinctrl-0 = <&pp1800_dpbrdg_en
80 enable-active-high;
81 regulator-boot-on;
82 gpio = <&pio 126 GPIO_ACTIVE_H
83 vin-supply = <&mt6359_vio18_ld
84 };
85
86 /* system wide LDO 1.8V power rail */
87 pp1800_ldo_g: regulator-1v8-g {
88 compatible = "regulator-fixed"
89 regulator-name = "pp1800_ldo_g
90 regulator-always-on;
91 regulator-boot-on;
92 regulator-min-microvolt = <180
93 regulator-max-microvolt = <180
94 vin-supply = <&pp3300_g>;
95 };
96
97 pp1800_mipibrdg: regulator-1v8-mipibrd
98 compatible = "regulator-fixed"
99 regulator-name = "pp1800_mipib
100 pinctrl-names = "default";
101 pinctrl-0 = <&pp1800_mipibrdg_
102 enable-active-high;
103 regulator-boot-on;
104 gpio = <&pio 128 GPIO_ACTIVE_H
105 vin-supply = <&mt6359_vio18_ld
106 };
107
108 pp3300_dpbrdg: regulator-3v3-dpbrdg {
109 compatible = "regulator-fixed"
110 regulator-name = "pp3300_dpbrd
111 pinctrl-names = "default";
112 pinctrl-0 = <&pp3300_dpbrdg_en
113 enable-active-high;
114 regulator-boot-on;
115 gpio = <&pio 26 GPIO_ACTIVE_HI
116 vin-supply = <&pp3300_g>;
117 };
118
119 /* system wide switching 3.3V power ra
120 pp3300_g: regulator-3v3-g {
121 compatible = "regulator-fixed"
122 regulator-name = "pp3300_g";
123 regulator-always-on;
124 regulator-boot-on;
125 regulator-min-microvolt = <330
126 regulator-max-microvolt = <330
127 vin-supply = <&ppvar_sys>;
128 };
129
130 /* system wide LDO 3.3V power rail */
131 pp3300_ldo_z: regulator-3v3-z {
132 compatible = "regulator-fixed"
133 regulator-name = "pp3300_ldo_z
134 regulator-always-on;
135 regulator-boot-on;
136 regulator-min-microvolt = <330
137 regulator-max-microvolt = <330
138 vin-supply = <&ppvar_sys>;
139 };
140
141 pp3300_mipibrdg: regulator-3v3-mipibrd
142 compatible = "regulator-fixed"
143 regulator-name = "pp3300_mipib
144 pinctrl-names = "default";
145 pinctrl-0 = <&pp3300_mipibrdg_
146 enable-active-high;
147 regulator-boot-on;
148 gpio = <&pio 127 GPIO_ACTIVE_H
149 vin-supply = <&pp3300_g>;
150 off-on-delay-us = <500000>;
151 };
152
153 /* separately switched 3.3V power rail
154 pp3300_u: regulator-3v3-u {
155 compatible = "regulator-fixed"
156 regulator-name = "pp3300_u";
157 regulator-always-on;
158 regulator-boot-on;
159 regulator-min-microvolt = <330
160 regulator-max-microvolt = <330
161 /* enable pin wired to GPIO co
162 vin-supply = <&pp3300_g>;
163 };
164
165 pp3300_wlan: regulator-3v3-wlan {
166 compatible = "regulator-fixed"
167 regulator-name = "pp3300_wlan"
168 regulator-always-on;
169 regulator-boot-on;
170 regulator-min-microvolt = <330
171 regulator-max-microvolt = <330
172 pinctrl-names = "default";
173 pinctrl-0 = <&pp3300_wlan_pins
174 enable-active-high;
175 gpio = <&pio 143 GPIO_ACTIVE_H
176 };
177
178 /* system wide switching 5.0V power ra
179 pp5000_a: regulator-5v0-a {
180 compatible = "regulator-fixed"
181 regulator-name = "pp5000_a";
182 regulator-always-on;
183 regulator-boot-on;
184 regulator-min-microvolt = <500
185 regulator-max-microvolt = <500
186 vin-supply = <&ppvar_sys>;
187 };
188
189 /* system wide semi-regulated power ra
190 ppvar_sys: regulator-var-sys {
191 compatible = "regulator-fixed"
192 regulator-name = "ppvar_sys";
193 regulator-always-on;
194 regulator-boot-on;
195 };
196
197 reserved_memory: reserved-memory {
198 #address-cells = <2>;
199 #size-cells = <2>;
200 ranges;
201
202 scp_mem_reserved: scp@50000000
203 compatible = "shared-d
204 reg = <0 0x50000000 0
205 no-map;
206 };
207
208 wifi_restricted_dma_region: wi
209 compatible = "restrict
210 reg = <0 0xc0000000 0
211 };
212 };
213
214 rt1015p: audio-codec {
215 compatible = "realtek,rt1015p"
216 pinctrl-names = "default";
217 pinctrl-0 = <&rt1015p_pins>;
218 sdb-gpios = <&pio 147 GPIO_ACT
219 #sound-dai-cells = <0>;
220 };
221
222 sound: sound {
223 mediatek,platform = <&afe>;
224 pinctrl-names = "aud_clk_mosi_
225 "aud_clk_mosi_
226 "aud_dat_mosi_
227 "aud_dat_mosi_
228 "aud_dat_miso_
229 "aud_dat_miso_
230 "vow_dat_miso_
231 "vow_dat_miso_
232 "vow_clk_miso_
233 "vow_clk_miso_
234 "aud_nle_mosi_
235 "aud_nle_mosi_
236 "aud_dat_miso2
237 "aud_dat_miso2
238 "aud_gpio_i2s3
239 "aud_gpio_i2s3
240 "aud_gpio_i2s8
241 "aud_gpio_i2s8
242 "aud_gpio_i2s9
243 "aud_gpio_i2s9
244 "aud_dat_mosi_
245 "aud_dat_mosi_
246 "aud_dat_miso_
247 "aud_dat_miso_
248 "aud_gpio_tdm_
249 "aud_gpio_tdm_
250 pinctrl-0 = <&aud_clk_mosi_off
251 pinctrl-1 = <&aud_clk_mosi_on_
252 pinctrl-2 = <&aud_dat_mosi_off
253 pinctrl-3 = <&aud_dat_mosi_on_
254 pinctrl-4 = <&aud_dat_miso_off
255 pinctrl-5 = <&aud_dat_miso_on_
256 pinctrl-6 = <&vow_dat_miso_off
257 pinctrl-7 = <&vow_dat_miso_on_
258 pinctrl-8 = <&vow_clk_miso_off
259 pinctrl-9 = <&vow_clk_miso_on_
260 pinctrl-10 = <&aud_nle_mosi_of
261 pinctrl-11 = <&aud_nle_mosi_on
262 pinctrl-12 = <&aud_dat_miso2_o
263 pinctrl-13 = <&aud_dat_miso2_o
264 pinctrl-14 = <&aud_gpio_i2s3_o
265 pinctrl-15 = <&aud_gpio_i2s3_o
266 pinctrl-16 = <&aud_gpio_i2s8_o
267 pinctrl-17 = <&aud_gpio_i2s8_o
268 pinctrl-18 = <&aud_gpio_i2s9_o
269 pinctrl-19 = <&aud_gpio_i2s9_o
270 pinctrl-20 = <&aud_dat_mosi_ch
271 pinctrl-21 = <&aud_dat_mosi_ch
272 pinctrl-22 = <&aud_dat_miso_ch
273 pinctrl-23 = <&aud_dat_miso_ch
274 pinctrl-24 = <&aud_gpio_tdm_of
275 pinctrl-25 = <&aud_gpio_tdm_on
276 };
277 };
278
279 &dsi0 {
280 status = "okay";
281 };
282
283 &dsi_out {
284 remote-endpoint = <&anx7625_in>;
285 };
286
287 &gic {
288 mediatek,broken-save-restore-fw;
289 };
290
291 &gpu {
292 mali-supply = <&mt6315_7_vbuck1>;
293 status = "okay";
294 };
295
296 &i2c0 {
297 status = "okay";
298
299 clock-frequency = <400000>;
300 pinctrl-names = "default";
301 pinctrl-0 = <&i2c0_pins>;
302
303 touchscreen: touchscreen@10 {
304 reg = <0x10>;
305 interrupts-extended = <&pio 21
306 pinctrl-names = "default";
307 pinctrl-0 = <&touchscreen_pins
308 };
309 };
310
311 &i2c1 {
312 status = "okay";
313
314 clock-frequency = <400000>;
315 pinctrl-names = "default";
316 pinctrl-0 = <&i2c1_pins>;
317
318 rt5682: audio-codec@1a {
319 /* Realtek RT5682i or RT5682s,
320 reg = <0x1a>;
321 interrupts-extended = <&pio 18
322 realtek,jd-src = <1>;
323 #sound-dai-cells = <1>;
324
325 AVDD-supply = <&mt6359_vio18_l
326 DBVDD-supply = <&mt6359_vio18_
327 LDO1-IN-supply = <&mt6359_vio1
328 MICVDD-supply = <&pp3300_g>;
329 };
330 };
331
332 &i2c2 {
333 status = "okay";
334
335 clock-frequency = <400000>;
336 clock-stretch-ns = <12600>;
337 pinctrl-names = "default";
338 pinctrl-0 = <&i2c2_pins>;
339
340 trackpad@15 {
341 compatible = "elan,ekth3000";
342 reg = <0x15>;
343 interrupts-extended = <&pio 15
344 pinctrl-names = "default";
345 pinctrl-0 = <&trackpad_pins>;
346 vcc-supply = <&pp3300_u>;
347 wakeup-source;
348 };
349 };
350
351 &i2c3 {
352 status = "okay";
353
354 clock-frequency = <400000>;
355 pinctrl-names = "default";
356 pinctrl-0 = <&i2c3_pins>;
357
358 anx_bridge: anx7625@58 {
359 compatible = "analogix,anx7625
360 reg = <0x58>;
361 pinctrl-names = "default";
362 pinctrl-0 = <&anx7625_pins>;
363 enable-gpios = <&pio 41 GPIO_A
364 reset-gpios = <&pio 42 GPIO_AC
365 vdd10-supply = <&pp1000_mipibr
366 vdd18-supply = <&pp1800_mipibr
367 vdd33-supply = <&pp3300_mipibr
368
369 ports {
370 #address-cells = <1>;
371 #size-cells = <0>;
372
373 port@0 {
374 reg = <0>;
375
376 anx7625_in: en
377 remote
378 };
379 };
380
381 port@1 {
382 reg = <1>;
383
384 anx7625_out: e
385 remote
386 };
387 };
388 };
389
390 aux-bus {
391 panel: panel {
392 compatible = "
393 power-supply =
394 backlight = <&
395
396 port {
397 panel_
398
399 };
400 };
401 };
402 };
403 };
404 };
405
406 &i2c7 {
407 status = "okay";
408
409 clock-frequency = <400000>;
410 pinctrl-names = "default";
411 pinctrl-0 = <&i2c7_pins>;
412 };
413
414 &mfg0 {
415 domain-supply = <&mt6315_7_vbuck1>;
416 };
417
418 &mfg1 {
419 domain-supply = <&mt6359_vsram_others_
420 };
421
422 &mipi_tx0 {
423 status = "okay";
424 };
425
426 &mmc0 {
427 status = "okay";
428
429 pinctrl-names = "default", "state_uhs"
430 pinctrl-0 = <&mmc0_default_pins>;
431 pinctrl-1 = <&mmc0_uhs_pins>;
432 bus-width = <8>;
433 max-frequency = <200000000>;
434 vmmc-supply = <&mt6359_vemc_1_ldo_reg>
435 vqmmc-supply = <&mt6359_vufs_ldo_reg>;
436 cap-mmc-highspeed;
437 mmc-hs200-1_8v;
438 mmc-hs400-1_8v;
439 supports-cqe;
440 cap-mmc-hw-reset;
441 mmc-hs400-enhanced-strobe;
442 hs400-ds-delay = <0x12814>;
443 no-sdio;
444 no-sd;
445 non-removable;
446 };
447
448 &mmc1 {
449 status = "okay";
450
451 pinctrl-names = "default", "state_uhs"
452 pinctrl-0 = <&mmc1_default_pins>;
453 pinctrl-1 = <&mmc1_uhs_pins>;
454 bus-width = <4>;
455 max-frequency = <200000000>;
456 cd-gpios = <&pio 17 GPIO_ACTIVE_LOW>;
457 vmmc-supply = <&mt6360_ldo5_reg>;
458 vqmmc-supply = <&mt6360_ldo3_reg>;
459 cap-sd-highspeed;
460 sd-uhs-sdr50;
461 sd-uhs-sdr104;
462 no-sdio;
463 no-mmc;
464 };
465
466 /* for CORE */
467 &mt6359_vgpu11_buck_reg {
468 regulator-always-on;
469 };
470
471 &mt6359_vgpu11_sshub_buck_reg {
472 regulator-always-on;
473 regulator-min-microvolt = <575000>;
474 regulator-max-microvolt = <575000>;
475 };
476
477 &mt6359_vrf12_ldo_reg {
478 regulator-always-on;
479 };
480
481 &mt6359_vsram_others_ldo_reg {
482 regulator-min-microvolt = <750000>;
483 regulator-max-microvolt = <800000>;
484 regulator-coupled-with = <&mt6315_7_vb
485 regulator-coupled-max-spread = <10000>
486 };
487
488 &mt6359_vufs_ldo_reg {
489 regulator-always-on;
490 };
491
492 &mt6359codec {
493 mediatek,dmic-mode = <1>; /* one-wire
494 mediatek,mic-type-0 = <2>; /* DMIC */
495 mediatek,mic-type-2 = <2>; /* DMIC */
496 };
497
498 &nor_flash {
499 status = "okay";
500
501 pinctrl-names = "default";
502 pinctrl-0 = <&nor_flash_pins>;
503 assigned-clocks = <&topckgen CLK_TOP_S
504 assigned-clock-parents = <&topckgen CL
505
506 flash@0 {
507 compatible = "winbond,w25q64jw
508 reg = <0>;
509 spi-max-frequency = <52000000>
510 spi-rx-bus-width = <2>;
511 spi-tx-bus-width = <2>;
512 };
513 };
514
515 &pcie {
516 pinctrl-names = "default";
517 pinctrl-0 = <&pcie_pins>;
518
519 pcie0: pcie@0,0 {
520 device_type = "pci";
521 reg = <0x0000 0 0 0 0>;
522 num-lanes = <1>;
523 bus-range = <0x1 0x1>;
524
525 #address-cells = <3>;
526 #size-cells = <2>;
527 ranges;
528
529 wifi: wifi@0,0 {
530 reg = <0x10000 0 0 0 0
531 <0x10000 0 0x100
532 memory-region = <&wifi
533 };
534 };
535 };
536
537 &pio {
538 /* 220 lines */
539 gpio-line-names = "I2S_DP_LRCK",
540 "IS_DP_BCLK",
541 "I2S_DP_MCLK",
542 "I2S_DP_DATAOUT",
543 "SAR0_INT_ODL",
544 "EC_AP_INT_ODL",
545 "EDPBRDG_INT_ODL",
546 "DPBRDG_INT_ODL",
547 "DPBRDG_PWREN",
548 "DPBRDG_RST_ODL",
549 "I2S_HP_MCLK",
550 "I2S_HP_BCK",
551 "I2S_HP_LRCK",
552 "I2S_HP_DATAIN",
553 /*
554 * AP_FLASH_WP_L is
555 * call it AP_FLASH_
556 */
557 "AP_FLASH_WP_L",
558 "TRACKPAD_INT_ODL",
559 "EC_AP_HPD_OD",
560 "SD_CD_ODL",
561 "HP_INT_ODL_ALC",
562 "EN_PP1000_DPBRDG",
563 "AP_GPIO20",
564 "TOUCH_INT_L_1V8",
565 "UART_BT_WAKE_ODL",
566 "AP_GPIO23",
567 "AP_SPI_FLASH_CS_L",
568 "AP_SPI_FLASH_CLK",
569 "EN_PP3300_DPBRDG_DX
570 "AP_SPI_FLASH_MOSI",
571 "AP_SPI_FLASH_MISO",
572 "I2S_HP_DATAOUT",
573 "AP_GPIO30",
574 "I2S_SPKR_MCLK",
575 "I2S_SPKR_BCLK",
576 "I2S_SPKR_LRCK",
577 "I2S_SPKR_DATAIN",
578 "I2S_SPKR_DATAOUT",
579 "AP_SPI_H1_TPM_CLK",
580 "AP_SPI_H1_TPM_CS_L"
581 "AP_SPI_H1_TPM_MISO"
582 "AP_SPI_H1_TPM_MOSI"
583 "BL_PWM",
584 "EDPBRDG_PWREN",
585 "EDPBRDG_RST_ODL",
586 "EN_PP3300_HUB",
587 "HUB_RST_L",
588 "",
589 "",
590 "",
591 "",
592 "",
593 "",
594 "SD_CLK",
595 "SD_CMD",
596 "SD_DATA3",
597 "SD_DATA0",
598 "SD_DATA2",
599 "SD_DATA1",
600 "",
601 "",
602 "",
603 "",
604 "",
605 "",
606 "PCIE_WAKE_ODL",
607 "PCIE_RST_L",
608 "PCIE_CLKREQ_ODL",
609 "",
610 "",
611 "",
612 "",
613 "",
614 "",
615 "",
616 "",
617 "",
618 "",
619 "",
620 "",
621 "",
622 "",
623 "",
624 "",
625 "",
626 "",
627 "",
628 "",
629 "",
630 "",
631 "",
632 "SPMI_SCL",
633 "SPMI_SDA",
634 "AP_GOOD",
635 "UART_DBG_TX_AP_RX",
636 "UART_AP_TX_DBG_RX",
637 "UART_AP_TX_BT_RX",
638 "UART_BT_TX_AP_RX",
639 "MIPI_DPI_D0_R",
640 "MIPI_DPI_D1_R",
641 "MIPI_DPI_D2_R",
642 "MIPI_DPI_D3_R",
643 "MIPI_DPI_D4_R",
644 "MIPI_DPI_D5_R",
645 "MIPI_DPI_D6_R",
646 "MIPI_DPI_D7_R",
647 "MIPI_DPI_D8_R",
648 "MIPI_DPI_D9_R",
649 "MIPI_DPI_D10_R",
650 "",
651 "",
652 "MIPI_DPI_DE_R",
653 "MIPI_DPI_D11_R",
654 "MIPI_DPI_VSYNC_R",
655 "MIPI_DPI_CLK_R",
656 "MIPI_DPI_HSYNC_R",
657 "PCM_BT_DATAIN",
658 "PCM_BT_SYNC",
659 "PCM_BT_DATAOUT",
660 "PCM_BT_CLK",
661 "AP_I2C_AUDIO_SCL",
662 "AP_I2C_AUDIO_SDA",
663 "SCP_I2C_SCL",
664 "SCP_I2C_SDA",
665 "AP_I2C_WLAN_SCL",
666 "AP_I2C_WLAN_SDA",
667 "AP_I2C_DPBRDG_SCL",
668 "AP_I2C_DPBRDG_SDA",
669 "EN_PP1800_DPBRDG_DX
670 "EN_PP3300_EDP_DX",
671 "EN_PP1800_EDPBRDG_D
672 "EN_PP1000_EDPBRDG",
673 "SCP_JTAG0_TDO",
674 "SCP_JTAG0_TDI",
675 "SCP_JTAG0_TMS",
676 "SCP_JTAG0_TCK",
677 "SCP_JTAG0_TRSTN",
678 "EN_PP3000_VMC_PMU",
679 "EN_PP3300_DISPLAY_D
680 "TOUCH_RST_L_1V8",
681 "TOUCH_REPORT_DISABL
682 "",
683 "",
684 "AP_I2C_TRACKPAD_SCL
685 "AP_I2C_TRACKPAD_SDA
686 "EN_PP3300_WLAN",
687 "BT_KILL_L",
688 "WIFI_KILL_L",
689 "SET_VMC_VOLT_AT_1V8
690 "EN_SPK",
691 "AP_WARM_RST_REQ",
692 "",
693 "",
694 "EN_PP3000_SD_S3",
695 "AP_EDP_BKLTEN",
696 "",
697 "",
698 "",
699 "AP_SPI_EC_CLK",
700 "AP_SPI_EC_CS_L",
701 "AP_SPI_EC_MISO",
702 "AP_SPI_EC_MOSI",
703 "AP_I2C_EDPBRDG_SCL"
704 "AP_I2C_EDPBRDG_SDA"
705 "MT6315_PROC_INT",
706 "MT6315_GPU_INT",
707 "UART_SERVO_TX_SCP_R
708 "UART_SCP_TX_SERVO_R
709 "BT_RTS_AP_CTS",
710 "AP_RTS_BT_CTS",
711 "UART_AP_WAKE_BT_ODL
712 "WLAN_ALERT_ODL",
713 "EC_IN_RW_ODL",
714 "H1_AP_INT_ODL",
715 "",
716 "",
717 "",
718 "",
719 "",
720 "",
721 "",
722 "",
723 "",
724 "",
725 "",
726 "MSDC0_CMD",
727 "MSDC0_DAT0",
728 "MSDC0_DAT2",
729 "MSDC0_DAT4",
730 "MSDC0_DAT6",
731 "MSDC0_DAT1",
732 "MSDC0_DAT5",
733 "MSDC0_DAT7",
734 "MSDC0_DSL",
735 "MSDC0_CLK",
736 "MSDC0_DAT3",
737 "MSDC0_RST_L",
738 "SCP_VREQ_VAO",
739 "AUD_DAT_MOSI2",
740 "AUD_NLE_MOSI1",
741 "AUD_NLE_MOSI0",
742 "AUD_DAT_MISO2",
743 "AP_I2C_SAR_SDA",
744 "AP_I2C_SAR_SCL",
745 "AP_I2C_PWR_SCL",
746 "AP_I2C_PWR_SDA",
747 "AP_I2C_TS_SCL_1V8",
748 "AP_I2C_TS_SDA_1V8",
749 "SRCLKENA0",
750 "SRCLKENA1",
751 "AP_EC_WATCHDOG_L",
752 "PWRAP_SPI0_MI",
753 "PWRAP_SPI0_CSN",
754 "PWRAP_SPI0_MO",
755 "PWRAP_SPI0_CK",
756 "AP_RTC_CLK32K",
757 "AUD_CLK_MOSI",
758 "AUD_SYNC_MOSI",
759 "AUD_DAT_MOSI0",
760 "AUD_DAT_MOSI1",
761 "AUD_DAT_MISO0",
762 "AUD_DAT_MISO1";
763
764 anx7625_pins: anx7625-default-pins {
765 pins-out {
766 pinmux = <PINMUX_GPIO4
767 <PINMUX_GPIO4
768 output-low;
769 };
770
771 pins-in {
772 pinmux = <PINMUX_GPIO6
773 input-enable;
774 bias-pull-up;
775 };
776 };
777
778 aud_clk_mosi_off_pins: aud-clk-mosi-of
779 pins-mosi-off {
780 pinmux = <PINMUX_GPIO2
781 <PINMUX_GPIO2
782 };
783 };
784
785 aud_clk_mosi_on_pins: aud-clk-mosi-on-
786 pins-mosi-on {
787 pinmux = <PINMUX_GPIO2
788 <PINMUX_GPIO2
789 drive-strength = <10>;
790 };
791 };
792
793 aud_dat_miso_ch34_off_pins: aud-dat-mi
794 pins-miso-off {
795 pinmux = <PINMUX_GPIO1
796 };
797 };
798
799 aud_dat_miso_ch34_on_pins: aud-dat-mis
800 pins-miso-on {
801 pinmux = <PINMUX_GPIO1
802 };
803 };
804
805 aud_dat_miso_off_pins: aud-dat-miso-of
806 pins-miso-off {
807 pinmux = <PINMUX_GPIO2
808 <PINMUX_GPIO2
809 };
810 };
811
812 aud_dat_miso_on_pins: aud-dat-miso-on-
813 pins-miso-on {
814 pinmux = <PINMUX_GPIO2
815 <PINMUX_GPIO2
816 drive-strength = <10>;
817 };
818 };
819
820 aud_dat_miso2_off_pins: aud-dat-miso2-
821 pins-miso-off {
822 pinmux = <PINMUX_GPIO1
823 };
824 };
825
826 aud_dat_miso2_on_pins: aud-dat-miso2-o
827 pins-miso-on {
828 pinmux = <PINMUX_GPIO1
829 };
830 };
831
832 aud_dat_mosi_ch34_off_pins: aud-dat-mo
833 pins-mosi-off {
834 pinmux = <PINMUX_GPIO1
835 };
836 };
837
838 aud_dat_mosi_ch34_on_pins: aud-dat-mos
839 pins-mosi-on {
840 pinmux = <PINMUX_GPIO1
841 };
842 };
843
844 aud_dat_mosi_off_pins: aud-dat-mosi-of
845 pins-mosi-off {
846 pinmux = <PINMUX_GPIO2
847 <PINMUX_GPIO2
848 };
849 };
850
851 aud_dat_mosi_on_pins: aud-dat-mosi-on-
852 pins-mosi-on {
853 pinmux = <PINMUX_GPIO2
854 <PINMUX_GPIO2
855 drive-strength = <10>;
856 };
857 };
858
859 aud_gpio_i2s3_off_pins: aud-gpio-i2s3-
860 pins-i2s3-off {
861 pinmux = <PINMUX_GPIO3
862 <PINMUX_GPIO3
863 <PINMUX_GPIO3
864 };
865 };
866
867 aud_gpio_i2s3_on_pins: aud-gpio-i2s3-o
868 pins-i2s3-on {
869 pinmux = <PINMUX_GPIO3
870 <PINMUX_GPIO3
871 <PINMUX_GPIO3
872 };
873 };
874
875 aud_gpio_i2s8_off_pins: aud-gpio-i2s8-
876 pins-i2s8-off {
877 pinmux = <PINMUX_GPIO1
878 <PINMUX_GPIO1
879 <PINMUX_GPIO1
880 <PINMUX_GPIO1
881 };
882 };
883
884 aud_gpio_i2s8_on_pins: aud-gpio-i2s8-o
885 pins-i2s8-on {
886 pinmux = <PINMUX_GPIO1
887 <PINMUX_GPIO1
888 <PINMUX_GPIO1
889 <PINMUX_GPIO1
890 };
891 };
892
893 aud_gpio_i2s9_off_pins: aud-gpio-i2s9-
894 pins-i2s9-off {
895 pinmux = <PINMUX_GPIO2
896 };
897 };
898
899 aud_gpio_i2s9_on_pins: aud-gpio-i2s9-o
900 pins-i2s9-on {
901 pinmux = <PINMUX_GPIO2
902 };
903 };
904
905 aud_gpio_tdm_off_pins: aud-gpio-tdm-of
906 pins-tdm-off {
907 pinmux = <PINMUX_GPIO0
908 <PINMUX_GPIO1
909 <PINMUX_GPIO2
910 <PINMUX_GPIO3
911 };
912 };
913
914 aud_gpio_tdm_on_pins: aud-gpio-tdm-on-
915 pins-tdm-on {
916 pinmux = <PINMUX_GPIO0
917 <PINMUX_GPIO1
918 <PINMUX_GPIO2
919 <PINMUX_GPIO3
920 };
921 };
922
923 aud_nle_mosi_off_pins: aud-nle-mosi-of
924 pins-nle-mosi-off {
925 pinmux = <PINMUX_GPIO1
926 <PINMUX_GPIO1
927 };
928 };
929
930 aud_nle_mosi_on_pins: aud-nle-mosi-on-
931 pins-nle-mosi-on {
932 pinmux = <PINMUX_GPIO1
933 <PINMUX_GPIO1
934 };
935 };
936
937 cr50_int: cr50-irq-default-pins {
938 pins-gsc-ap-int-odl {
939 pinmux = <PINMUX_GPIO1
940 input-enable;
941 };
942 };
943
944 cros_ec_int: cros-ec-irq-default-pins
945 pins-ec-ap-int-odl {
946 pinmux = <PINMUX_GPIO5
947 input-enable;
948 bias-pull-up;
949 };
950 };
951
952 i2c0_pins: i2c0-default-pins {
953 pins-bus {
954 pinmux = <PINMUX_GPIO2
955 <PINMUX_GPIO2
956 bias-pull-up = <MTK_PU
957 drive-strength-microam
958 };
959 };
960
961 i2c1_pins: i2c1-default-pins {
962 pins-bus {
963 pinmux = <PINMUX_GPIO1
964 <PINMUX_GPIO1
965 bias-pull-up = <MTK_PU
966 drive-strength-microam
967 };
968 };
969
970 i2c2_pins: i2c2-default-pins {
971 pins-bus {
972 pinmux = <PINMUX_GPIO1
973 <PINMUX_GPIO1
974 bias-pull-up = <MTK_PU
975 };
976 };
977
978 i2c3_pins: i2c3-default-pins {
979 pins-bus {
980 pinmux = <PINMUX_GPIO1
981 <PINMUX_GPIO1
982 bias-disable;
983 drive-strength-microam
984 };
985 };
986
987 i2c7_pins: i2c7-default-pins {
988 pins-bus {
989 pinmux = <PINMUX_GPIO1
990 <PINMUX_GPIO1
991 bias-disable;
992 drive-strength-microam
993 };
994 };
995
996 mmc0_default_pins: mmc0-default-pins {
997 pins-cmd-dat {
998 pinmux = <PINMUX_GPIO1
999 <PINMUX_GPIO1
1000 <PINMUX_GPIO
1001 <PINMUX_GPIO
1002 <PINMUX_GPIO
1003 <PINMUX_GPIO
1004 <PINMUX_GPIO
1005 <PINMUX_GPIO
1006 <PINMUX_GPIO
1007 input-enable;
1008 drive-strength = <8>;
1009 bias-pull-up = <MTK_P
1010 };
1011
1012 pins-clk {
1013 pinmux = <PINMUX_GPIO
1014 drive-strength = <8>;
1015 bias-pull-down = <MTK
1016 };
1017
1018 pins-rst {
1019 pinmux = <PINMUX_GPIO
1020 drive-strength = <8>;
1021 bias-pull-down = <MTK
1022 };
1023 };
1024
1025 mmc0_uhs_pins: mmc0-uhs-pins {
1026 pins-cmd-dat {
1027 pinmux = <PINMUX_GPIO
1028 <PINMUX_GPIO
1029 <PINMUX_GPIO
1030 <PINMUX_GPIO
1031 <PINMUX_GPIO
1032 <PINMUX_GPIO
1033 <PINMUX_GPIO
1034 <PINMUX_GPIO
1035 <PINMUX_GPIO
1036 input-enable;
1037 drive-strength = <10>
1038 bias-pull-up = <MTK_P
1039 };
1040
1041 pins-clk {
1042 pinmux = <PINMUX_GPIO
1043 drive-strength = <10>
1044 bias-pull-down = <MTK
1045 };
1046
1047 pins-rst {
1048 pinmux = <PINMUX_GPIO
1049 drive-strength = <8>;
1050 bias-pull-down = <MTK
1051 };
1052
1053 pins-ds {
1054 pinmux = <PINMUX_GPIO
1055 drive-strength = <10>
1056 bias-pull-down = <MTK
1057 };
1058 };
1059
1060 mmc1_default_pins: mmc1-default-pins
1061 pins-cmd-dat {
1062 pinmux = <PINMUX_GPIO
1063 <PINMUX_GPIO
1064 <PINMUX_GPIO
1065 <PINMUX_GPIO
1066 <PINMUX_GPIO
1067 input-enable;
1068 drive-strength = <8>;
1069 bias-pull-up = <MTK_P
1070 };
1071
1072 pins-clk {
1073 pinmux = <PINMUX_GPIO
1074 drive-strength = <8>;
1075 bias-pull-down = <MTK
1076 };
1077
1078 pins-insert {
1079 pinmux = <PINMUX_GPIO
1080 input-enable;
1081 bias-pull-up;
1082 };
1083 };
1084
1085 mmc1_uhs_pins: mmc1-uhs-pins {
1086 pins-cmd-dat {
1087 pinmux = <PINMUX_GPIO
1088 <PINMUX_GPIO
1089 <PINMUX_GPIO
1090 <PINMUX_GPIO
1091 <PINMUX_GPIO
1092 input-enable;
1093 drive-strength = <8>;
1094 bias-pull-up = <MTK_P
1095 };
1096
1097 pins-clk {
1098 pinmux = <PINMUX_GPIO
1099 input-enable;
1100 drive-strength = <8>;
1101 bias-pull-down = <MTK
1102 };
1103 };
1104
1105 nor_flash_pins: nor-flash-default-pin
1106 pins-cs-io1 {
1107 pinmux = <PINMUX_GPIO
1108 <PINMUX_GPIO
1109 input-enable;
1110 bias-pull-up;
1111 drive-strength = <10>
1112 };
1113
1114 pins-io0 {
1115 pinmux = <PINMUX_GPIO
1116 bias-pull-up;
1117 drive-strength = <10>
1118 };
1119
1120 pins-clk {
1121 pinmux = <PINMUX_GPIO
1122 input-enable;
1123 bias-pull-up;
1124 drive-strength = <10>
1125 };
1126 };
1127
1128 pcie_pins: pcie-default-pins {
1129 pins-pcie-wake {
1130 pinmux = <PINMUX_GPIO
1131 bias-pull-up;
1132 };
1133
1134 pins-pcie-pereset {
1135 pinmux = <PINMUX_GPIO
1136 };
1137
1138 pins-pcie-clkreq {
1139 pinmux = <PINMUX_GPIO
1140 bias-pull-up;
1141 };
1142
1143 pins-wifi-kill {
1144 pinmux = <PINMUX_GPIO
1145 output-high;
1146 };
1147 };
1148
1149 pp1000_dpbrdg_en_pins: pp1000-dpbrdg-
1150 pins-en {
1151 pinmux = <PINMUX_GPIO
1152 output-low;
1153 };
1154 };
1155
1156 pp1000_mipibrdg_en_pins: pp1000-mipib
1157 pins-en {
1158 pinmux = <PINMUX_GPIO
1159 output-low;
1160 };
1161 };
1162
1163 pp1800_dpbrdg_en_pins: pp1800-dpbrdg-
1164 pins-en {
1165 pinmux = <PINMUX_GPIO
1166 output-low;
1167 };
1168 };
1169
1170 pp1800_mipibrdg_en_pins: pp1800-mipib
1171 pins-en {
1172 pinmux = <PINMUX_GPIO
1173 output-low;
1174 };
1175 };
1176
1177 pp3300_dpbrdg_en_pins: pp3300-dpbrdg-
1178 pins-en {
1179 pinmux = <PINMUX_GPIO
1180 output-low;
1181 };
1182 };
1183
1184 pp3300_mipibrdg_en_pins: pp3300-mipib
1185 pins-en {
1186 pinmux = <PINMUX_GPIO
1187 output-low;
1188 };
1189 };
1190
1191 pp3300_wlan_pins: pp3300-wlan-pins {
1192 pins-pcie-en-pp3300-wlan {
1193 pinmux = <PINMUX_GPIO
1194 output-high;
1195 };
1196 };
1197
1198 pwm0_pins: pwm0-default-pins {
1199 pins-pwm {
1200 pinmux = <PINMUX_GPIO
1201 };
1202
1203 pins-inhibit {
1204 pinmux = <PINMUX_GPIO
1205 output-high;
1206 };
1207 };
1208
1209 rt1015p_pins: rt1015p-default-pins {
1210 pins {
1211 pinmux = <PINMUX_GPIO
1212 output-low;
1213 };
1214 };
1215
1216 scp_pins: scp-pins {
1217 pins-vreq-vao {
1218 pinmux = <PINMUX_GPIO
1219 };
1220 };
1221
1222 spi1_pins: spi1-default-pins {
1223 pins-cs-mosi-clk {
1224 pinmux = <PINMUX_GPIO
1225 <PINMUX_GPIO
1226 <PINMUX_GPIO
1227 bias-disable;
1228 };
1229
1230 pins-miso {
1231 pinmux = <PINMUX_GPIO
1232 bias-pull-down;
1233 };
1234 };
1235
1236 spi5_pins: spi5-default-pins {
1237 pins-bus {
1238 pinmux = <PINMUX_GPIO
1239 <PINMUX_GPIO
1240 <PINMUX_GPIO
1241 <PINMUX_GPIO
1242 bias-disable;
1243 };
1244 };
1245
1246 trackpad_pins: trackpad-default-pins
1247 pins-int-n {
1248 pinmux = <PINMUX_GPIO
1249 input-enable;
1250 bias-pull-up = <MTK_P
1251 };
1252 };
1253
1254 touchscreen_pins: touchscreen-default
1255 pins-irq {
1256 pinmux = <PINMUX_GPIO
1257 input-enable;
1258 bias-pull-up;
1259 };
1260
1261 pins-reset {
1262 pinmux = <PINMUX_GPIO
1263 output-high;
1264 };
1265
1266 pins-report-sw {
1267 pinmux = <PINMUX_GPIO
1268 output-low;
1269 };
1270 };
1271
1272 vow_clk_miso_off_pins: vow-clk-miso-o
1273 pins-miso-off {
1274 pinmux = <PINMUX_GPIO
1275 };
1276 };
1277
1278 vow_clk_miso_on_pins: vow-clk-miso-on
1279 pins-miso-on {
1280 pinmux = <PINMUX_GPIO
1281 };
1282 };
1283
1284 vow_dat_miso_off_pins: vow-dat-miso-o
1285 pins-miso-off {
1286 pinmux = <PINMUX_GPIO
1287 };
1288 };
1289
1290 vow_dat_miso_on_pins: vow-dat-miso-on
1291 pins-miso-on {
1292 pinmux = <PINMUX_GPIO
1293 };
1294 };
1295 };
1296
1297 &pmic {
1298 interrupts-extended = <&pio 214 IRQ_T
1299 };
1300
1301 &pwm0 {
1302 status = "okay";
1303
1304 pinctrl-names = "default";
1305 pinctrl-0 = <&pwm0_pins>;
1306 };
1307
1308 &scp {
1309 status = "okay";
1310
1311 firmware-name = "mediatek/mt8192/scp.
1312 memory-region = <&scp_mem_reserved>;
1313 pinctrl-names = "default";
1314 pinctrl-0 = <&scp_pins>;
1315
1316 cros-ec-rpmsg {
1317 compatible = "google,cros-ec-
1318 mediatek,rpmsg-name = "cros-e
1319 };
1320 };
1321
1322 &spi1 {
1323 status = "okay";
1324
1325 mediatek,pad-select = <0>;
1326 pinctrl-names = "default";
1327 pinctrl-0 = <&spi1_pins>;
1328
1329 cros_ec: ec@0 {
1330 compatible = "google,cros-ec-
1331 reg = <0>;
1332 interrupts-extended = <&pio 5
1333 spi-max-frequency = <3000000>
1334 pinctrl-names = "default";
1335 pinctrl-0 = <&cros_ec_int>;
1336 wakeup-source;
1337
1338 #address-cells = <1>;
1339 #size-cells = <0>;
1340
1341 cros_ec_pwm: pwm {
1342 compatible = "google,
1343 #pwm-cells = <1>;
1344
1345 status = "disabled";
1346 };
1347
1348 i2c_tunnel: i2c-tunnel {
1349 compatible = "google,
1350 google,remote-bus = <
1351 #address-cells = <1>;
1352 #size-cells = <0>;
1353 };
1354
1355 mt6360_ldo3_reg: regulator@0
1356 compatible = "google,
1357 reg = <0>;
1358 regulator-min-microvo
1359 regulator-max-microvo
1360 };
1361
1362 mt6360_ldo5_reg: regulator@1
1363 compatible = "google,
1364 reg = <1>;
1365 regulator-min-microvo
1366 regulator-max-microvo
1367 };
1368
1369 typec {
1370 compatible = "google,
1371 #address-cells = <1>;
1372 #size-cells = <0>;
1373
1374 usb_c0: connector@0 {
1375 compatible =
1376 reg = <0>;
1377 label = "left
1378 power-role =
1379 data-role = "
1380 try-power-rol
1381 };
1382
1383 usb_c1: connector@1 {
1384 compatible =
1385 reg = <1>;
1386 label = "righ
1387 power-role =
1388 data-role = "
1389 try-power-rol
1390 };
1391 };
1392 };
1393 };
1394
1395 &spi5 {
1396 status = "okay";
1397
1398 cs-gpios = <&pio 37 GPIO_ACTIVE_LOW>;
1399 mediatek,pad-select = <0>;
1400 pinctrl-names = "default";
1401 pinctrl-0 = <&spi5_pins>;
1402
1403 tpm@0 {
1404 compatible = "google,cr50";
1405 reg = <0>;
1406 interrupts-extended = <&pio 1
1407 spi-max-frequency = <1000000>
1408 pinctrl-names = "default";
1409 pinctrl-0 = <&cr50_int>;
1410 };
1411 };
1412
1413 &spmi {
1414 #address-cells = <2>;
1415 #size-cells = <0>;
1416
1417 mt6315_6: pmic@6 {
1418 compatible = "mediatek,mt6315
1419 reg = <0x6 SPMI_USID>;
1420
1421 regulators {
1422 mt6315_6_vbuck1: vbuc
1423 regulator-com
1424 regulator-nam
1425 regulator-min
1426 regulator-max
1427 regulator-ena
1428 regulator-all
1429 regulator-alw
1430 };
1431
1432 mt6315_6_vbuck3: vbuc
1433 regulator-com
1434 regulator-nam
1435 regulator-min
1436 regulator-max
1437 regulator-ena
1438 regulator-all
1439 regulator-alw
1440 };
1441 };
1442 };
1443
1444 mt6315_7: pmic@7 {
1445 compatible = "mediatek,mt6315
1446 reg = <0x7 SPMI_USID>;
1447
1448 regulators {
1449 mt6315_7_vbuck1: vbuc
1450 regulator-com
1451 regulator-nam
1452 regulator-min
1453 regulator-max
1454 regulator-ena
1455 regulator-all
1456 regulator-cou
1457 regulator-cou
1458 };
1459 };
1460 };
1461 };
1462
1463 &uart0 {
1464 status = "okay";
1465 };
1466
1467 &xhci {
1468 status = "okay";
1469
1470 wakeup-source;
1471 vusb33-supply = <&pp3300_g>;
1472 vbus-supply = <&pp5000_a>;
1473 };
1474
1475 #include <arm/cros-ec-keyboard.dtsi>
1476 #include <arm/cros-ec-sbs.dtsi>
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