1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /*
3 * Copyright (C) 2020 MediaTek Inc.
4 * Author: Seiya Wang <seiya.wang@mediatek.com>
5 */
6
7 /dts-v1/;
8 #include <dt-bindings/clock/mt8192-clk.h>
9 #include <dt-bindings/gce/mt8192-gce.h>
10 #include <dt-bindings/interrupt-controller/arm
11 #include <dt-bindings/interrupt-controller/irq
12 #include <dt-bindings/memory/mt8192-larb-port.
13 #include <dt-bindings/pinctrl/mt8192-pinfunc.h
14 #include <dt-bindings/phy/phy.h>
15 #include <dt-bindings/power/mt8192-power.h>
16 #include <dt-bindings/reset/mt8192-resets.h>
17 #include <dt-bindings/thermal/thermal.h>
18 #include <dt-bindings/thermal/mediatek,lvts-th
19
20 / {
21 compatible = "mediatek,mt8192";
22 interrupt-parent = <&gic>;
23 #address-cells = <2>;
24 #size-cells = <2>;
25
26 aliases {
27 ovl0 = &ovl0;
28 ovl-2l0 = &ovl_2l0;
29 ovl-2l2 = &ovl_2l2;
30 rdma0 = &rdma0;
31 rdma4 = &rdma4;
32 };
33
34 clk13m: fixed-factor-clock-13m {
35 compatible = "fixed-factor-clo
36 #clock-cells = <0>;
37 clocks = <&clk26m>;
38 clock-div = <2>;
39 clock-mult = <1>;
40 clock-output-names = "clk13m";
41 };
42
43 clk26m: oscillator0 {
44 compatible = "fixed-clock";
45 #clock-cells = <0>;
46 clock-frequency = <26000000>;
47 clock-output-names = "clk26m";
48 };
49
50 clk32k: oscillator1 {
51 compatible = "fixed-clock";
52 #clock-cells = <0>;
53 clock-frequency = <32768>;
54 clock-output-names = "clk32k";
55 };
56
57 cpus {
58 #address-cells = <1>;
59 #size-cells = <0>;
60
61 cpu0: cpu@0 {
62 device_type = "cpu";
63 compatible = "arm,cort
64 reg = <0x000>;
65 enable-method = "psci"
66 clock-frequency = <170
67 cpu-idle-states = <&cp
68 i-cache-size = <32768>
69 i-cache-line-size = <6
70 i-cache-sets = <128>;
71 d-cache-size = <32768>
72 d-cache-line-size = <6
73 d-cache-sets = <128>;
74 next-level-cache = <&l
75 performance-domains =
76 capacity-dmips-mhz = <
77 #cooling-cells = <2>;
78 };
79
80 cpu1: cpu@100 {
81 device_type = "cpu";
82 compatible = "arm,cort
83 reg = <0x100>;
84 enable-method = "psci"
85 clock-frequency = <170
86 cpu-idle-states = <&cp
87 i-cache-size = <32768>
88 i-cache-line-size = <6
89 i-cache-sets = <128>;
90 d-cache-size = <32768>
91 d-cache-line-size = <6
92 d-cache-sets = <128>;
93 next-level-cache = <&l
94 performance-domains =
95 capacity-dmips-mhz = <
96 #cooling-cells = <2>;
97 };
98
99 cpu2: cpu@200 {
100 device_type = "cpu";
101 compatible = "arm,cort
102 reg = <0x200>;
103 enable-method = "psci"
104 clock-frequency = <170
105 cpu-idle-states = <&cp
106 i-cache-size = <32768>
107 i-cache-line-size = <6
108 i-cache-sets = <128>;
109 d-cache-size = <32768>
110 d-cache-line-size = <6
111 d-cache-sets = <128>;
112 next-level-cache = <&l
113 performance-domains =
114 capacity-dmips-mhz = <
115 #cooling-cells = <2>;
116 };
117
118 cpu3: cpu@300 {
119 device_type = "cpu";
120 compatible = "arm,cort
121 reg = <0x300>;
122 enable-method = "psci"
123 clock-frequency = <170
124 cpu-idle-states = <&cp
125 i-cache-size = <32768>
126 i-cache-line-size = <6
127 i-cache-sets = <128>;
128 d-cache-size = <32768>
129 d-cache-line-size = <6
130 d-cache-sets = <128>;
131 next-level-cache = <&l
132 performance-domains =
133 capacity-dmips-mhz = <
134 #cooling-cells = <2>;
135 };
136
137 cpu4: cpu@400 {
138 device_type = "cpu";
139 compatible = "arm,cort
140 reg = <0x400>;
141 enable-method = "psci"
142 clock-frequency = <217
143 cpu-idle-states = <&cp
144 i-cache-size = <65536>
145 i-cache-line-size = <6
146 i-cache-sets = <256>;
147 d-cache-size = <65536>
148 d-cache-line-size = <6
149 d-cache-sets = <256>;
150 next-level-cache = <&l
151 performance-domains =
152 capacity-dmips-mhz = <
153 #cooling-cells = <2>;
154 };
155
156 cpu5: cpu@500 {
157 device_type = "cpu";
158 compatible = "arm,cort
159 reg = <0x500>;
160 enable-method = "psci"
161 clock-frequency = <217
162 cpu-idle-states = <&cp
163 i-cache-size = <65536>
164 i-cache-line-size = <6
165 i-cache-sets = <256>;
166 d-cache-size = <65536>
167 d-cache-line-size = <6
168 d-cache-sets = <256>;
169 next-level-cache = <&l
170 performance-domains =
171 capacity-dmips-mhz = <
172 #cooling-cells = <2>;
173 };
174
175 cpu6: cpu@600 {
176 device_type = "cpu";
177 compatible = "arm,cort
178 reg = <0x600>;
179 enable-method = "psci"
180 clock-frequency = <217
181 cpu-idle-states = <&cp
182 i-cache-size = <65536>
183 i-cache-line-size = <6
184 i-cache-sets = <256>;
185 d-cache-size = <65536>
186 d-cache-line-size = <6
187 d-cache-sets = <256>;
188 next-level-cache = <&l
189 performance-domains =
190 capacity-dmips-mhz = <
191 #cooling-cells = <2>;
192 };
193
194 cpu7: cpu@700 {
195 device_type = "cpu";
196 compatible = "arm,cort
197 reg = <0x700>;
198 enable-method = "psci"
199 clock-frequency = <217
200 cpu-idle-states = <&cp
201 i-cache-size = <65536>
202 i-cache-line-size = <6
203 i-cache-sets = <256>;
204 d-cache-size = <65536>
205 d-cache-line-size = <6
206 d-cache-sets = <256>;
207 next-level-cache = <&l
208 performance-domains =
209 capacity-dmips-mhz = <
210 #cooling-cells = <2>;
211 };
212
213 cpu-map {
214 cluster0 {
215 core0 {
216 cpu =
217 };
218 core1 {
219 cpu =
220 };
221 core2 {
222 cpu =
223 };
224 core3 {
225 cpu =
226 };
227 core4 {
228 cpu =
229 };
230 core5 {
231 cpu =
232 };
233 core6 {
234 cpu =
235 };
236 core7 {
237 cpu =
238 };
239 };
240 };
241
242 l2_0: l2-cache0 {
243 compatible = "cache";
244 cache-level = <2>;
245 cache-size = <131072>;
246 cache-line-size = <64>
247 cache-sets = <512>;
248 next-level-cache = <&l
249 cache-unified;
250 };
251
252 l2_1: l2-cache1 {
253 compatible = "cache";
254 cache-level = <2>;
255 cache-size = <262144>;
256 cache-line-size = <64>
257 cache-sets = <512>;
258 next-level-cache = <&l
259 cache-unified;
260 };
261
262 l3_0: l3-cache {
263 compatible = "cache";
264 cache-level = <3>;
265 cache-size = <2097152>
266 cache-line-size = <64>
267 cache-sets = <2048>;
268 cache-unified;
269 };
270
271 idle-states {
272 entry-method = "psci";
273 cpu_ret_l: cpu-retenti
274 compatible = "
275 arm,psci-suspe
276 local-timer-st
277 entry-latency-
278 exit-latency-u
279 min-residency-
280 };
281 cpu_ret_b: cpu-retenti
282 compatible = "
283 arm,psci-suspe
284 local-timer-st
285 entry-latency-
286 exit-latency-u
287 min-residency-
288 };
289 cpu_off_l: cpu-off-l {
290 compatible = "
291 arm,psci-suspe
292 local-timer-st
293 entry-latency-
294 exit-latency-u
295 min-residency-
296 };
297 cpu_off_b: cpu-off-b {
298 compatible = "
299 arm,psci-suspe
300 local-timer-st
301 entry-latency-
302 exit-latency-u
303 min-residency-
304 };
305 };
306 };
307
308 pmu-a55 {
309 compatible = "arm,cortex-a55-p
310 interrupt-parent = <&gic>;
311 interrupts = <GIC_PPI 7 IRQ_TY
312 };
313
314 pmu-a76 {
315 compatible = "arm,cortex-a76-p
316 interrupt-parent = <&gic>;
317 interrupts = <GIC_PPI 7 IRQ_TY
318 };
319
320 psci {
321 compatible = "arm,psci-1.0";
322 method = "smc";
323 };
324
325 timer: timer {
326 compatible = "arm,armv8-timer"
327 interrupt-parent = <&gic>;
328 interrupts = <GIC_PPI 13 IRQ_T
329 <GIC_PPI 14 IRQ_T
330 <GIC_PPI 11 IRQ_T
331 <GIC_PPI 10 IRQ_T
332 clock-frequency = <13000000>;
333 };
334
335 gpu_opp_table: opp-table-0 {
336 compatible = "operating-points
337 opp-shared;
338
339 opp-358000000 {
340 opp-hz = /bits/ 64 <35
341 opp-microvolt = <60625
342 };
343
344 opp-399000000 {
345 opp-hz = /bits/ 64 <39
346 opp-microvolt = <61875
347 };
348
349 opp-440000000 {
350 opp-hz = /bits/ 64 <44
351 opp-microvolt = <63125
352 };
353
354 opp-482000000 {
355 opp-hz = /bits/ 64 <48
356 opp-microvolt = <64375
357 };
358
359 opp-523000000 {
360 opp-hz = /bits/ 64 <52
361 opp-microvolt = <65625
362 };
363
364 opp-564000000 {
365 opp-hz = /bits/ 64 <56
366 opp-microvolt = <66875
367 };
368
369 opp-605000000 {
370 opp-hz = /bits/ 64 <60
371 opp-microvolt = <68125
372 };
373
374 opp-647000000 {
375 opp-hz = /bits/ 64 <64
376 opp-microvolt = <69375
377 };
378
379 opp-688000000 {
380 opp-hz = /bits/ 64 <68
381 opp-microvolt = <70625
382 };
383
384 opp-724000000 {
385 opp-hz = /bits/ 64 <72
386 opp-microvolt = <72500
387 };
388
389 opp-748000000 {
390 opp-hz = /bits/ 64 <74
391 opp-microvolt = <73750
392 };
393
394 opp-772000000 {
395 opp-hz = /bits/ 64 <77
396 opp-microvolt = <75000
397 };
398
399 opp-795000000 {
400 opp-hz = /bits/ 64 <79
401 opp-microvolt = <76250
402 };
403
404 opp-819000000 {
405 opp-hz = /bits/ 64 <81
406 opp-microvolt = <77500
407 };
408
409 opp-843000000 {
410 opp-hz = /bits/ 64 <84
411 opp-microvolt = <78750
412 };
413
414 opp-866000000 {
415 opp-hz = /bits/ 64 <86
416 opp-microvolt = <80000
417 };
418 };
419
420 soc {
421 #address-cells = <2>;
422 #size-cells = <2>;
423 compatible = "simple-bus";
424 dma-ranges = <0x0 0x0 0x0 0x0
425 ranges;
426
427 performance: performance-contr
428 compatible = "mediatek
429 reg = <0 0x0011bc10 0
430 #performance-domain-ce
431 };
432
433 gic: interrupt-controller@c000
434 compatible = "arm,gic-
435 #interrupt-cells = <4>
436 #redistributor-regions
437 interrupt-parent = <&g
438 interrupt-controller;
439 reg = <0 0x0c000000 0
440 <0 0x0c040000 0
441 interrupts = <GIC_PPI
442
443 ppi-partitions {
444 ppi_cluster0:
445 affini
446 };
447 ppi_cluster1:
448 affini
449 };
450 };
451 };
452
453 topckgen: syscon@10000000 {
454 compatible = "mediatek
455 reg = <0 0x10000000 0
456 #clock-cells = <1>;
457 };
458
459 infracfg: syscon@10001000 {
460 compatible = "mediatek
461 reg = <0 0x10001000 0
462 #clock-cells = <1>;
463 #reset-cells = <1>;
464 };
465
466 pericfg: syscon@10003000 {
467 compatible = "mediatek
468 reg = <0 0x10003000 0
469 #clock-cells = <1>;
470 };
471
472 pio: pinctrl@10005000 {
473 compatible = "mediatek
474 reg = <0 0x10005000 0
475 <0 0x11c20000 0
476 <0 0x11d10000 0
477 <0 0x11d30000 0
478 <0 0x11d40000 0
479 <0 0x11e20000 0
480 <0 0x11e70000 0
481 <0 0x11ea0000 0
482 <0 0x11f20000 0
483 <0 0x11f30000 0
484 <0 0x1000b000 0
485 reg-names = "iocfg0",
486 "iocfg_bl"
487 "iocfg_lb"
488 "iocfg_tl"
489 gpio-controller;
490 #gpio-cells = <2>;
491 gpio-ranges = <&pio 0
492 interrupt-controller;
493 interrupts = <GIC_SPI
494 #interrupt-cells = <2>
495 };
496
497 scpsys: syscon@10006000 {
498 compatible = "mediatek
499 reg = <0 0x10006000 0
500
501 /* System Power Manage
502 spm: power-controller
503 compatible = "
504 #address-cells
505 #size-cells =
506 #power-domain-
507
508 /* power domai
509 power-domain@M
510 reg =
511 clocks
512
513
514 clock-
515 mediat
516 #power
517 };
518
519 power-domain@M
520 reg =
521 clocks
522 clock-
523 mediat
524 #power
525 };
526
527 mfg0: power-do
528 reg =
529 clocks
530
531 clock-
532 #addre
533 #size-
534 #power
535
536 mfg1:
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567 };
568 };
569
570 power-domain@M
571 reg =
572 clocks
573
574
575
576
577 clock-
578
579 mediat
580 #addre
581 #size-
582 #power
583
584 power-
585
586
587
588
589
590
591
592
593
594
595 };
596
597 power-
598
599
600
601
602
603
604
605 };
606
607 power-
608
609
610
611
612
613
614
615 };
616
617 power-
618
619
620
621
622
623
624 };
625
626 power-
627
628
629
630
631
632
633 };
634
635 power-
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656 };
657
658 power-
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692 };
693 };
694 };
695 };
696
697 watchdog: watchdog@10007000 {
698 compatible = "mediatek
699 reg = <0 0x10007000 0
700 #reset-cells = <1>;
701 };
702
703 apmixedsys: syscon@1000c000 {
704 compatible = "mediatek
705 reg = <0 0x1000c000 0
706 #clock-cells = <1>;
707 };
708
709 systimer: timer@10017000 {
710 compatible = "mediatek
711 "mediatek
712 reg = <0 0x10017000 0
713 interrupts = <GIC_SPI
714 clocks = <&clk13m>;
715 };
716
717 pwrap: pwrap@10026000 {
718 compatible = "mediatek
719 reg = <0 0x10026000 0
720 reg-names = "pwrap";
721 interrupts = <GIC_SPI
722 clocks = <&infracfg CL
723 <&infracfg CL
724 clock-names = "spi", "
725 assigned-clocks = <&to
726 assigned-clock-parents
727 };
728
729 spmi: spmi@10027000 {
730 compatible = "mediatek
731 reg = <0 0x10027000 0
732 <0 0x10029000 0
733 reg-names = "pmif", "s
734 clocks = <&infracfg CL
735 <&infracfg CL
736 <&topckgen CL
737 clock-names = "pmif_sy
738 "pmif_tm
739 "spmimst
740 assigned-clocks = <&to
741 assigned-clock-parents
742 };
743
744 gce: mailbox@10228000 {
745 compatible = "mediatek
746 reg = <0 0x10228000 0
747 interrupts = <GIC_SPI
748 #mbox-cells = <2>;
749 clocks = <&infracfg CL
750 clock-names = "gce";
751 };
752
753 scp_adsp: clock-controller@107
754 compatible = "mediatek
755 reg = <0 0x10720000 0
756 #clock-cells = <1>;
757 /* power domain depend
758 status = "fail";
759 };
760
761 uart0: serial@11002000 {
762 compatible = "mediatek
763 "mediatek
764 reg = <0 0x11002000 0
765 interrupts = <GIC_SPI
766 clocks = <&clk26m>, <&
767 clock-names = "baud",
768 status = "disabled";
769 };
770
771 uart1: serial@11003000 {
772 compatible = "mediatek
773 "mediatek
774 reg = <0 0x11003000 0
775 interrupts = <GIC_SPI
776 clocks = <&clk26m>, <&
777 clock-names = "baud",
778 status = "disabled";
779 };
780
781 imp_iic_wrap_c: clock-controll
782 compatible = "mediatek
783 reg = <0 0x11007000 0
784 #clock-cells = <1>;
785 };
786
787 spi0: spi@1100a000 {
788 compatible = "mediatek
789 "mediatek
790 #address-cells = <1>;
791 #size-cells = <0>;
792 reg = <0 0x1100a000 0
793 interrupts = <GIC_SPI
794 clocks = <&topckgen CL
795 <&topckgen CL
796 <&infracfg CL
797 clock-names = "parent-
798 status = "disabled";
799 };
800
801 lvts_ap: thermal-sensor@1100b0
802 compatible = "mediatek
803 reg = <0 0x1100b000 0
804 interrupts = <GIC_SPI
805 clocks = <&infracfg CL
806 resets = <&infracfg MT
807 nvmem-cells = <&lvts_e
808 nvmem-cell-names = "lv
809 #thermal-sensor-cells
810 };
811
812 svs: svs@1100bc00 {
813 compatible = "mediatek
814 reg = <0 0x1100bc00 0
815 interrupts = <GIC_SPI
816 clocks = <&infracfg CL
817 clock-names = "main";
818 nvmem-cells = <&svs_ca
819 nvmem-cell-names = "sv
820 resets = <&infracfg MT
821 reset-names = "svs_rst
822 };
823
824 pwm0: pwm@1100e000 {
825 compatible = "mediatek
826 reg = <0 0x1100e000 0
827 interrupts = <GIC_SPI
828 #pwm-cells = <2>;
829 clocks = <&topckgen CL
830 <&infracfg CL
831 clock-names = "main",
832 status = "disabled";
833 };
834
835 spi1: spi@11010000 {
836 compatible = "mediatek
837 "mediatek
838 #address-cells = <1>;
839 #size-cells = <0>;
840 reg = <0 0x11010000 0
841 interrupts = <GIC_SPI
842 clocks = <&topckgen CL
843 <&topckgen CL
844 <&infracfg CL
845 clock-names = "parent-
846 status = "disabled";
847 };
848
849 spi2: spi@11012000 {
850 compatible = "mediatek
851 "mediatek
852 #address-cells = <1>;
853 #size-cells = <0>;
854 reg = <0 0x11012000 0
855 interrupts = <GIC_SPI
856 clocks = <&topckgen CL
857 <&topckgen CL
858 <&infracfg CL
859 clock-names = "parent-
860 status = "disabled";
861 };
862
863 spi3: spi@11013000 {
864 compatible = "mediatek
865 "mediatek
866 #address-cells = <1>;
867 #size-cells = <0>;
868 reg = <0 0x11013000 0
869 interrupts = <GIC_SPI
870 clocks = <&topckgen CL
871 <&topckgen CL
872 <&infracfg CL
873 clock-names = "parent-
874 status = "disabled";
875 };
876
877 spi4: spi@11018000 {
878 compatible = "mediatek
879 "mediatek
880 #address-cells = <1>;
881 #size-cells = <0>;
882 reg = <0 0x11018000 0
883 interrupts = <GIC_SPI
884 clocks = <&topckgen CL
885 <&topckgen CL
886 <&infracfg CL
887 clock-names = "parent-
888 status = "disabled";
889 };
890
891 spi5: spi@11019000 {
892 compatible = "mediatek
893 "mediatek
894 #address-cells = <1>;
895 #size-cells = <0>;
896 reg = <0 0x11019000 0
897 interrupts = <GIC_SPI
898 clocks = <&topckgen CL
899 <&topckgen CL
900 <&infracfg CL
901 clock-names = "parent-
902 status = "disabled";
903 };
904
905 spi6: spi@1101d000 {
906 compatible = "mediatek
907 "mediatek
908 #address-cells = <1>;
909 #size-cells = <0>;
910 reg = <0 0x1101d000 0
911 interrupts = <GIC_SPI
912 clocks = <&topckgen CL
913 <&topckgen CL
914 <&infracfg CL
915 clock-names = "parent-
916 status = "disabled";
917 };
918
919 spi7: spi@1101e000 {
920 compatible = "mediatek
921 "mediatek
922 #address-cells = <1>;
923 #size-cells = <0>;
924 reg = <0 0x1101e000 0
925 interrupts = <GIC_SPI
926 clocks = <&topckgen CL
927 <&topckgen CL
928 <&infracfg CL
929 clock-names = "parent-
930 status = "disabled";
931 };
932
933 scp: scp@10500000 {
934 compatible = "mediatek
935 reg = <0 0x10500000 0
936 <0 0x10720000 0
937 <0 0x10700000 0
938 reg-names = "sram", "c
939 interrupts = <GIC_SPI
940 clocks = <&infracfg CL
941 clock-names = "main";
942 status = "disabled";
943 };
944
945 xhci: usb@11200000 {
946 compatible = "mediatek
947 "mediatek
948 reg = <0 0x11200000 0
949 <0 0x11203e00 0
950 reg-names = "mac", "ip
951 interrupts-extended =
952 interrupt-names = "hos
953 phys = <&u2port0 PHY_T
954 <&u3port0 PHY_T
955 assigned-clocks = <&to
956 <&to
957 assigned-clock-parents
958
959 clocks = <&infracfg CL
960 <&apmixedsys
961 <&clk26m>,
962 <&clk26m>,
963 <&infracfg CL
964 clock-names = "sys_ck"
965 "xhci_ck
966 wakeup-source;
967 mediatek,syscon-wakeup
968 status = "disabled";
969 };
970
971 audsys: syscon@11210000 {
972 compatible = "mediatek
973 reg = <0 0x11210000 0
974 #clock-cells = <1>;
975
976 afe: mt8192-afe-pcm {
977 compatible = "
978 interrupts = <
979 resets = <&wat
980 reset-names =
981 mediatek,apmix
982 mediatek,infra
983 mediatek,topck
984 power-domains
985 clocks = <&aud
986 <&aud
987 <&aud
988 <&aud
989 <&aud
990 <&aud
991 <&aud
992 <&aud
993 <&aud
994 <&aud
995 <&aud
996 <&aud
997 <&aud
998 <&aud
999 <&aud
1000 <&au
1001 <&au
1002 <&au
1003 <&au
1004 <&au
1005 <&in
1006 <&in
1007 <&to
1008 <&to
1009 <&to
1010 <&to
1011 <&to
1012 <&to
1013 <&to
1014 <&to
1015 <&to
1016 <&to
1017 <&to
1018 <&to
1019 <&to
1020 <&to
1021 <&to
1022 <&to
1023 <&to
1024 <&to
1025 <&to
1026 <&to
1027 <&to
1028 <&to
1029 <&to
1030 <&to
1031 <&to
1032 <&to
1033 <&to
1034 <&to
1035 <&to
1036 <&to
1037 <&to
1038 <&to
1039 <&to
1040 <&cl
1041 clock-names =
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097 };
1098 };
1099
1100 pcie: pcie@11230000 {
1101 compatible = "mediate
1102 device_type = "pci";
1103 reg = <0 0x11230000 0
1104 reg-names = "pcie-mac
1105 #address-cells = <3>;
1106 #size-cells = <2>;
1107 clocks = <&infracfg C
1108 <&infracfg C
1109 <&infracfg C
1110 <&infracfg C
1111 <&infracfg C
1112 <&infracfg C
1113 clock-names = "pl_250
1114 "tl_32k
1115 assigned-clocks = <&t
1116 assigned-clock-parent
1117 interrupts = <GIC_SPI
1118 bus-range = <0x00 0xf
1119 ranges = <0x82000000
1120 <0x81000000
1121 #interrupt-cells = <1
1122 interrupt-map-mask =
1123 interrupt-map = <0 0
1124 <0 0
1125 <0 0
1126 <0 0
1127
1128 pcie_intc0: interrupt
1129 interrupt-con
1130 #address-cell
1131 #interrupt-ce
1132 };
1133 };
1134
1135 nor_flash: spi@11234000 {
1136 compatible = "mediate
1137 reg = <0 0x11234000 0
1138 interrupts = <GIC_SPI
1139 clocks = <&topckgen C
1140 <&infracfg C
1141 <&infracfg C
1142 clock-names = "spi",
1143 assigned-clocks = <&t
1144 assigned-clock-parent
1145 #address-cells = <1>;
1146 #size-cells = <0>;
1147 status = "disabled";
1148 };
1149
1150 lvts_mcu: thermal-sensor@1127
1151 compatible = "mediate
1152 reg = <0 0x11278000 0
1153 interrupts = <GIC_SPI
1154 clocks = <&infracfg C
1155 resets = <&infracfg M
1156 nvmem-cells = <&lvts_
1157 nvmem-cell-names = "l
1158 #thermal-sensor-cells
1159 };
1160
1161 efuse: efuse@11c10000 {
1162 compatible = "mediate
1163 reg = <0 0x11c10000 0
1164 #address-cells = <1>;
1165 #size-cells = <1>;
1166
1167 socinfo-data1@44 {
1168 reg = <0x044
1169 };
1170
1171 socinfo-data2@50 {
1172 reg = <0x050
1173 };
1174
1175 lvts_e_data1: data1@1
1176 reg = <0x1c0
1177 };
1178
1179 svs_calibration: cali
1180 reg = <0x580
1181 };
1182 };
1183
1184 i2c3: i2c@11cb0000 {
1185 compatible = "mediate
1186 reg = <0 0x11cb0000 0
1187 <0 0x10217300 0
1188 interrupts = <GIC_SPI
1189 clocks = <&imp_iic_wr
1190 <&infracfg C
1191 clock-names = "main",
1192 clock-div = <1>;
1193 #address-cells = <1>;
1194 #size-cells = <0>;
1195 status = "disabled";
1196 };
1197
1198 imp_iic_wrap_e: clock-control
1199 compatible = "mediate
1200 reg = <0 0x11cb1000 0
1201 #clock-cells = <1>;
1202 };
1203
1204 i2c7: i2c@11d00000 {
1205 compatible = "mediate
1206 reg = <0 0x11d00000 0
1207 <0 0x10217600 0
1208 interrupts = <GIC_SPI
1209 clocks = <&imp_iic_wr
1210 <&infracfg C
1211 clock-names = "main",
1212 clock-div = <1>;
1213 #address-cells = <1>;
1214 #size-cells = <0>;
1215 status = "disabled";
1216 };
1217
1218 i2c8: i2c@11d01000 {
1219 compatible = "mediate
1220 reg = <0 0x11d01000 0
1221 <0 0x10217780 0
1222 interrupts = <GIC_SPI
1223 clocks = <&imp_iic_wr
1224 <&infracfg C
1225 clock-names = "main",
1226 clock-div = <1>;
1227 #address-cells = <1>;
1228 #size-cells = <0>;
1229 status = "disabled";
1230 };
1231
1232 i2c9: i2c@11d02000 {
1233 compatible = "mediate
1234 reg = <0 0x11d02000 0
1235 <0 0x10217900 0
1236 interrupts = <GIC_SPI
1237 clocks = <&imp_iic_wr
1238 <&infracfg C
1239 clock-names = "main",
1240 clock-div = <1>;
1241 #address-cells = <1>;
1242 #size-cells = <0>;
1243 status = "disabled";
1244 };
1245
1246 imp_iic_wrap_s: clock-control
1247 compatible = "mediate
1248 reg = <0 0x11d03000 0
1249 #clock-cells = <1>;
1250 };
1251
1252 i2c1: i2c@11d20000 {
1253 compatible = "mediate
1254 reg = <0 0x11d20000 0
1255 <0 0x10217100 0
1256 interrupts = <GIC_SPI
1257 clocks = <&imp_iic_wr
1258 <&infracfg C
1259 clock-names = "main",
1260 clock-div = <1>;
1261 #address-cells = <1>;
1262 #size-cells = <0>;
1263 status = "disabled";
1264 };
1265
1266 i2c2: i2c@11d21000 {
1267 compatible = "mediate
1268 reg = <0 0x11d21000 0
1269 <0 0x10217180 0
1270 interrupts = <GIC_SPI
1271 clocks = <&imp_iic_wr
1272 <&infracfg C
1273 clock-names = "main",
1274 clock-div = <1>;
1275 #address-cells = <1>;
1276 #size-cells = <0>;
1277 status = "disabled";
1278 };
1279
1280 i2c4: i2c@11d22000 {
1281 compatible = "mediate
1282 reg = <0 0x11d22000 0
1283 <0 0x10217380 0
1284 interrupts = <GIC_SPI
1285 clocks = <&imp_iic_wr
1286 <&infracfg C
1287 clock-names = "main",
1288 clock-div = <1>;
1289 #address-cells = <1>;
1290 #size-cells = <0>;
1291 status = "disabled";
1292 };
1293
1294 imp_iic_wrap_ws: clock-contro
1295 compatible = "mediate
1296 reg = <0 0x11d23000 0
1297 #clock-cells = <1>;
1298 };
1299
1300 i2c5: i2c@11e00000 {
1301 compatible = "mediate
1302 reg = <0 0x11e00000 0
1303 <0 0x10217500 0
1304 interrupts = <GIC_SPI
1305 clocks = <&imp_iic_wr
1306 <&infracfg C
1307 clock-names = "main",
1308 clock-div = <1>;
1309 #address-cells = <1>;
1310 #size-cells = <0>;
1311 status = "disabled";
1312 };
1313
1314 imp_iic_wrap_w: clock-control
1315 compatible = "mediate
1316 reg = <0 0x11e01000 0
1317 #clock-cells = <1>;
1318 };
1319
1320 u3phy0: t-phy@11e40000 {
1321 compatible = "mediate
1322 "mediate
1323 #address-cells = <1>;
1324 #size-cells = <1>;
1325 ranges = <0x0 0x0 0x1
1326
1327 u2port0: usb-phy@0 {
1328 reg = <0x0 0x
1329 clocks = <&cl
1330 clock-names =
1331 #phy-cells =
1332 };
1333
1334 u3port0: usb-phy@700
1335 reg = <0x700
1336 clocks = <&cl
1337 clock-names =
1338 #phy-cells =
1339 };
1340 };
1341
1342 mipi_tx0: dsi-phy@11e50000 {
1343 compatible = "mediate
1344 reg = <0 0x11e50000 0
1345 clocks = <&apmixedsys
1346 #clock-cells = <0>;
1347 #phy-cells = <0>;
1348 clock-output-names =
1349 status = "disabled";
1350 };
1351
1352 i2c0: i2c@11f00000 {
1353 compatible = "mediate
1354 reg = <0 0x11f00000 0
1355 <0 0x10217080 0
1356 interrupts = <GIC_SPI
1357 clocks = <&imp_iic_wr
1358 <&infracfg C
1359 clock-names = "main",
1360 clock-div = <1>;
1361 #address-cells = <1>;
1362 #size-cells = <0>;
1363 status = "disabled";
1364 };
1365
1366 i2c6: i2c@11f01000 {
1367 compatible = "mediate
1368 reg = <0 0x11f01000 0
1369 <0 0x10217580 0
1370 interrupts = <GIC_SPI
1371 clocks = <&imp_iic_wr
1372 <&infracfg C
1373 clock-names = "main",
1374 clock-div = <1>;
1375 #address-cells = <1>;
1376 #size-cells = <0>;
1377 status = "disabled";
1378 };
1379
1380 imp_iic_wrap_n: clock-control
1381 compatible = "mediate
1382 reg = <0 0x11f02000 0
1383 #clock-cells = <1>;
1384 };
1385
1386 msdc_top: clock-controller@11
1387 compatible = "mediate
1388 reg = <0 0x11f10000 0
1389 #clock-cells = <1>;
1390 };
1391
1392 mmc0: mmc@11f60000 {
1393 compatible = "mediate
1394 reg = <0 0x11f60000 0
1395 interrupts = <GIC_SPI
1396 clocks = <&topckgen C
1397 <&msdc_top C
1398 <&msdc_top C
1399 <&msdc_top C
1400 <&msdc_top C
1401 <&msdc_top C
1402 <&msdc_top C
1403 clock-names = "source
1404 "pclk_c
1405 status = "disabled";
1406 };
1407
1408 mmc1: mmc@11f70000 {
1409 compatible = "mediate
1410 reg = <0 0x11f70000 0
1411 interrupts = <GIC_SPI
1412 clocks = <&topckgen C
1413 <&msdc_top C
1414 <&msdc_top C
1415 <&msdc_top C
1416 <&msdc_top C
1417 <&msdc_top C
1418 <&msdc_top C
1419 clock-names = "source
1420 "pclk_c
1421 status = "disabled";
1422 };
1423
1424 gpu: gpu@13000000 {
1425 compatible = "mediate
1426 reg = <0 0x13000000 0
1427 interrupts = <GIC_SPI
1428 <GIC_SPI
1429 <GIC_SPI
1430 interrupt-names = "jo
1431
1432 clocks = <&apmixedsys
1433
1434 power-domains = <&spm
1435 <&spm
1436 <&spm
1437 <&spm
1438 <&spm
1439 power-domain-names =
1440
1441 operating-points-v2 =
1442
1443 status = "disabled";
1444 };
1445
1446 mfgcfg: clock-controller@13fb
1447 compatible = "mediate
1448 reg = <0 0x13fbf000 0
1449 #clock-cells = <1>;
1450 };
1451
1452 mmsys: syscon@14000000 {
1453 compatible = "mediate
1454 reg = <0 0x14000000 0
1455 #clock-cells = <1>;
1456 #reset-cells = <1>;
1457 mboxes = <&gce 0 CMDQ
1458 <&gce 1 CMDQ
1459 mediatek,gce-client-r
1460 };
1461
1462 mutex: mutex@14001000 {
1463 compatible = "mediate
1464 reg = <0 0x14001000 0
1465 interrupts = <GIC_SPI
1466 clocks = <&mmsys CLK_
1467 mediatek,gce-client-r
1468 mediatek,gce-events =
1469
1470 power-domains = <&spm
1471 };
1472
1473 smi_common: smi@14002000 {
1474 compatible = "mediate
1475 reg = <0 0x14002000 0
1476 clocks = <&mmsys CLK_
1477 <&mmsys CLK_
1478 <&mmsys CLK_
1479 <&mmsys CLK_
1480 clock-names = "apb",
1481 power-domains = <&spm
1482 };
1483
1484 larb0: larb@14003000 {
1485 compatible = "mediate
1486 reg = <0 0x14003000 0
1487 mediatek,larb-id = <0
1488 mediatek,smi = <&smi_
1489 clocks = <&clk26m>, <
1490 clock-names = "apb",
1491 power-domains = <&spm
1492 };
1493
1494 larb1: larb@14004000 {
1495 compatible = "mediate
1496 reg = <0 0x14004000 0
1497 mediatek,larb-id = <1
1498 mediatek,smi = <&smi_
1499 clocks = <&clk26m>, <
1500 clock-names = "apb",
1501 power-domains = <&spm
1502 };
1503
1504 ovl0: ovl@14005000 {
1505 compatible = "mediate
1506 reg = <0 0x14005000 0
1507 interrupts = <GIC_SPI
1508 clocks = <&mmsys CLK_
1509 iommus = <&iommu0 M4U
1510 <&iommu0 M4U
1511 power-domains = <&spm
1512 mediatek,gce-client-r
1513 };
1514
1515 ovl_2l0: ovl@14006000 {
1516 compatible = "mediate
1517 reg = <0 0x14006000 0
1518 interrupts = <GIC_SPI
1519 power-domains = <&spm
1520 clocks = <&mmsys CLK_
1521 iommus = <&iommu0 M4U
1522 <&iommu0 M4U
1523 mediatek,gce-client-r
1524 };
1525
1526 rdma0: rdma@14007000 {
1527 compatible = "mediate
1528 "mediate
1529 reg = <0 0x14007000 0
1530 interrupts = <GIC_SPI
1531 clocks = <&mmsys CLK_
1532 iommus = <&iommu0 M4U
1533 mediatek,rdma-fifo-si
1534 power-domains = <&spm
1535 mediatek,gce-client-r
1536 };
1537
1538 color0: color@14009000 {
1539 compatible = "mediate
1540 "mediate
1541 reg = <0 0x14009000 0
1542 interrupts = <GIC_SPI
1543 power-domains = <&spm
1544 clocks = <&mmsys CLK_
1545 mediatek,gce-client-r
1546 };
1547
1548 ccorr0: ccorr@1400a000 {
1549 compatible = "mediate
1550 reg = <0 0x1400a000 0
1551 interrupts = <GIC_SPI
1552 power-domains = <&spm
1553 clocks = <&mmsys CLK_
1554 mediatek,gce-client-r
1555 };
1556
1557 aal0: aal@1400b000 {
1558 compatible = "mediate
1559 "mediate
1560 reg = <0 0x1400b000 0
1561 interrupts = <GIC_SPI
1562 power-domains = <&spm
1563 clocks = <&mmsys CLK_
1564 mediatek,gce-client-r
1565 };
1566
1567 gamma0: gamma@1400c000 {
1568 compatible = "mediate
1569 "mediate
1570 reg = <0 0x1400c000 0
1571 interrupts = <GIC_SPI
1572 power-domains = <&spm
1573 clocks = <&mmsys CLK_
1574 mediatek,gce-client-r
1575 };
1576
1577 postmask0: postmask@1400d000
1578 compatible = "mediate
1579 reg = <0 0x1400d000 0
1580 interrupts = <GIC_SPI
1581 power-domains = <&spm
1582 clocks = <&mmsys CLK_
1583 mediatek,gce-client-r
1584 };
1585
1586 dither0: dither@1400e000 {
1587 compatible = "mediate
1588 "mediate
1589 reg = <0 0x1400e000 0
1590 interrupts = <GIC_SPI
1591 power-domains = <&spm
1592 clocks = <&mmsys CLK_
1593 mediatek,gce-client-r
1594 };
1595
1596 dsi0: dsi@14010000 {
1597 compatible = "mediate
1598 reg = <0 0x14010000 0
1599 interrupts = <GIC_SPI
1600 clocks = <&mmsys CLK_
1601 <&mmsys CLK_
1602 <&mipi_tx0>;
1603 clock-names = "engine
1604 phys = <&mipi_tx0>;
1605 phy-names = "dphy";
1606 power-domains = <&spm
1607 resets = <&mmsys MT81
1608 status = "disabled";
1609
1610 port {
1611 dsi_out: endp
1612 };
1613 };
1614
1615 ovl_2l2: ovl@14014000 {
1616 compatible = "mediate
1617 reg = <0 0x14014000 0
1618 interrupts = <GIC_SPI
1619 power-domains = <&spm
1620 clocks = <&mmsys CLK_
1621 iommus = <&iommu0 M4U
1622 <&iommu0 M4U
1623 mediatek,gce-client-r
1624 };
1625
1626 rdma4: rdma@14015000 {
1627 compatible = "mediate
1628 "mediate
1629 reg = <0 0x14015000 0
1630 interrupts = <GIC_SPI
1631 power-domains = <&spm
1632 clocks = <&mmsys CLK_
1633 iommus = <&iommu0 M4U
1634 mediatek,rdma-fifo-si
1635 mediatek,gce-client-r
1636 };
1637
1638 dpi0: dpi@14016000 {
1639 compatible = "mediate
1640 reg = <0 0x14016000 0
1641 interrupts = <GIC_SPI
1642 clocks = <&mmsys CLK_
1643 <&mmsys CLK_
1644 <&apmixedsys
1645 clock-names = "pixel"
1646 status = "disabled";
1647 };
1648
1649 iommu0: m4u@1401d000 {
1650 compatible = "mediate
1651 reg = <0 0x1401d000 0
1652 mediatek,larbs = <&la
1653 <&la
1654 <&la
1655 <&la
1656 <&la
1657 interrupts = <GIC_SPI
1658 clocks = <&mmsys CLK_
1659 clock-names = "bclk";
1660 power-domains = <&spm
1661 #iommu-cells = <1>;
1662 };
1663
1664 imgsys: clock-controller@1502
1665 compatible = "mediate
1666 reg = <0 0x15020000 0
1667 #clock-cells = <1>;
1668 };
1669
1670 larb9: larb@1502e000 {
1671 compatible = "mediate
1672 reg = <0 0x1502e000 0
1673 mediatek,larb-id = <9
1674 mediatek,smi = <&smi_
1675 clocks = <&imgsys CLK
1676 <&imgsys CLK
1677 clock-names = "apb",
1678 power-domains = <&spm
1679 };
1680
1681 imgsys2: clock-controller@158
1682 compatible = "mediate
1683 reg = <0 0x15820000 0
1684 #clock-cells = <1>;
1685 };
1686
1687 larb11: larb@1582e000 {
1688 compatible = "mediate
1689 reg = <0 0x1582e000 0
1690 mediatek,larb-id = <1
1691 mediatek,smi = <&smi_
1692 clocks = <&imgsys2 CL
1693 <&imgsys2 CL
1694 clock-names = "apb",
1695 power-domains = <&spm
1696 };
1697
1698 vcodec_dec: video-codec@16000
1699 compatible = "mediate
1700 reg = <0 0x16000000 0
1701 mediatek,scp = <&scp>
1702 iommus = <&iommu0 M4U
1703 #address-cells = <2>;
1704 #size-cells = <2>;
1705 ranges = <0 0 0 0x160
1706
1707 video-codec@10000 {
1708 compatible =
1709 reg = <0x0 0x
1710 interrupts =
1711 iommus = <&io
1712 <&io
1713 <&io
1714 <&io
1715 <&io
1716 <&io
1717 <&io
1718 <&io
1719 clocks = <&to
1720 <&vd
1721 <&vd
1722 <&vd
1723 <&to
1724 clock-names =
1725 assigned-cloc
1726 assigned-cloc
1727 power-domains
1728 };
1729
1730 video-codec@25000 {
1731 compatible =
1732 reg = <0 0x25
1733 interrupts =
1734 iommus = <&io
1735 <&io
1736 <&io
1737 <&io
1738 <&io
1739 <&io
1740 <&io
1741 <&io
1742 <&io
1743 <&io
1744 <&io
1745 clocks = <&to
1746 <&vd
1747 <&vd
1748 <&vd
1749 <&to
1750 clock-names =
1751 assigned-cloc
1752 assigned-cloc
1753 power-domains
1754 };
1755 };
1756
1757 larb5: larb@1600d000 {
1758 compatible = "mediate
1759 reg = <0 0x1600d000 0
1760 mediatek,larb-id = <5
1761 mediatek,smi = <&smi_
1762 clocks = <&vdecsys_so
1763 <&vdecsys_so
1764 clock-names = "apb",
1765 power-domains = <&spm
1766 };
1767
1768 vdecsys_soc: clock-controller
1769 compatible = "mediate
1770 reg = <0 0x1600f000 0
1771 #clock-cells = <1>;
1772 };
1773
1774 larb4: larb@1602e000 {
1775 compatible = "mediate
1776 reg = <0 0x1602e000 0
1777 mediatek,larb-id = <4
1778 mediatek,smi = <&smi_
1779 clocks = <&vdecsys CL
1780 <&vdecsys CL
1781 clock-names = "apb",
1782 power-domains = <&spm
1783 };
1784
1785 vdecsys: clock-controller@160
1786 compatible = "mediate
1787 reg = <0 0x1602f000 0
1788 #clock-cells = <1>;
1789 };
1790
1791 vencsys: clock-controller@170
1792 compatible = "mediate
1793 reg = <0 0x17000000 0
1794 #clock-cells = <1>;
1795 };
1796
1797 larb7: larb@17010000 {
1798 compatible = "mediate
1799 reg = <0 0x17010000 0
1800 mediatek,larb-id = <7
1801 mediatek,smi = <&smi_
1802 clocks = <&vencsys CL
1803 <&vencsys CL
1804 clock-names = "apb",
1805 power-domains = <&spm
1806 };
1807
1808 vcodec_enc: vcodec@17020000 {
1809 compatible = "mediate
1810 reg = <0 0x17020000 0
1811 iommus = <&iommu0 M4U
1812 <&iommu0 M4U
1813 <&iommu0 M4U
1814 <&iommu0 M4U
1815 <&iommu0 M4U
1816 <&iommu0 M4U
1817 <&iommu0 M4U
1818 <&iommu0 M4U
1819 <&iommu0 M4U
1820 <&iommu0 M4U
1821 <&iommu0 M4U
1822 interrupts = <GIC_SPI
1823 mediatek,scp = <&scp>
1824 power-domains = <&spm
1825 clocks = <&vencsys CL
1826 clock-names = "venc_s
1827 assigned-clocks = <&t
1828 assigned-clock-parent
1829 };
1830
1831 camsys: clock-controller@1a00
1832 compatible = "mediate
1833 reg = <0 0x1a000000 0
1834 #clock-cells = <1>;
1835 };
1836
1837 larb13: larb@1a001000 {
1838 compatible = "mediate
1839 reg = <0 0x1a001000 0
1840 mediatek,larb-id = <1
1841 mediatek,smi = <&smi_
1842 clocks = <&camsys CLK
1843 <&camsys CLK
1844 clock-names = "apb",
1845 power-domains = <&spm
1846 };
1847
1848 larb14: larb@1a002000 {
1849 compatible = "mediate
1850 reg = <0 0x1a002000 0
1851 mediatek,larb-id = <1
1852 mediatek,smi = <&smi_
1853 clocks = <&camsys CLK
1854 <&camsys CLK
1855 clock-names = "apb",
1856 power-domains = <&spm
1857 };
1858
1859 larb16: larb@1a00f000 {
1860 compatible = "mediate
1861 reg = <0 0x1a00f000 0
1862 mediatek,larb-id = <1
1863 mediatek,smi = <&smi_
1864 clocks = <&camsys_raw
1865 <&camsys_raw
1866 clock-names = "apb",
1867 power-domains = <&spm
1868 };
1869
1870 larb17: larb@1a010000 {
1871 compatible = "mediate
1872 reg = <0 0x1a010000 0
1873 mediatek,larb-id = <1
1874 mediatek,smi = <&smi_
1875 clocks = <&camsys_raw
1876 <&camsys_raw
1877 clock-names = "apb",
1878 power-domains = <&spm
1879 };
1880
1881 larb18: larb@1a011000 {
1882 compatible = "mediate
1883 reg = <0 0x1a011000 0
1884 mediatek,larb-id = <1
1885 mediatek,smi = <&smi_
1886 clocks = <&camsys_raw
1887 <&camsys_raw
1888 clock-names = "apb",
1889 power-domains = <&spm
1890 };
1891
1892 camsys_rawa: clock-controller
1893 compatible = "mediate
1894 reg = <0 0x1a04f000 0
1895 #clock-cells = <1>;
1896 };
1897
1898 camsys_rawb: clock-controller
1899 compatible = "mediate
1900 reg = <0 0x1a06f000 0
1901 #clock-cells = <1>;
1902 };
1903
1904 camsys_rawc: clock-controller
1905 compatible = "mediate
1906 reg = <0 0x1a08f000 0
1907 #clock-cells = <1>;
1908 };
1909
1910 ipesys: clock-controller@1b00
1911 compatible = "mediate
1912 reg = <0 0x1b000000 0
1913 #clock-cells = <1>;
1914 };
1915
1916 larb20: larb@1b00f000 {
1917 compatible = "mediate
1918 reg = <0 0x1b00f000 0
1919 mediatek,larb-id = <2
1920 mediatek,smi = <&smi_
1921 clocks = <&ipesys CLK
1922 <&ipesys CLK
1923 clock-names = "apb",
1924 power-domains = <&spm
1925 };
1926
1927 larb19: larb@1b10f000 {
1928 compatible = "mediate
1929 reg = <0 0x1b10f000 0
1930 mediatek,larb-id = <1
1931 mediatek,smi = <&smi_
1932 clocks = <&ipesys CLK
1933 <&ipesys CLK
1934 clock-names = "apb",
1935 power-domains = <&spm
1936 };
1937
1938 mdpsys: clock-controller@1f00
1939 compatible = "mediate
1940 reg = <0 0x1f000000 0
1941 #clock-cells = <1>;
1942 };
1943
1944 larb2: larb@1f002000 {
1945 compatible = "mediate
1946 reg = <0 0x1f002000 0
1947 mediatek,larb-id = <2
1948 mediatek,smi = <&smi_
1949 clocks = <&mdpsys CLK
1950 <&mdpsys CLK
1951 clock-names = "apb",
1952 power-domains = <&spm
1953 };
1954 };
1955
1956 thermal_zones: thermal-zones {
1957 cpu0-thermal {
1958 polling-delay = <1000
1959 polling-delay-passive
1960 thermal-sensors = <&l
1961
1962 trips {
1963 cpu0_alert: t
1964 tempe
1965 hyste
1966 type
1967 };
1968
1969 cpu0_crit: tr
1970 tempe
1971 hyste
1972 type
1973 };
1974 };
1975
1976 cooling-maps {
1977 map0 {
1978 trip
1979 cooli
1980
1981
1982
1983 };
1984 };
1985 };
1986
1987 cpu1-thermal {
1988 polling-delay = <1000
1989 polling-delay-passive
1990 thermal-sensors = <&l
1991
1992 trips {
1993 cpu1_alert: t
1994 tempe
1995 hyste
1996 type
1997 };
1998
1999 cpu1_crit: tr
2000 tempe
2001 hyste
2002 type
2003 };
2004 };
2005
2006 cooling-maps {
2007 map0 {
2008 trip
2009 cooli
2010
2011
2012
2013 };
2014 };
2015 };
2016
2017 cpu2-thermal {
2018 polling-delay = <1000
2019 polling-delay-passive
2020 thermal-sensors = <&l
2021
2022 trips {
2023 cpu2_alert: t
2024 tempe
2025 hyste
2026 type
2027 };
2028
2029 cpu2_crit: tr
2030 tempe
2031 hyste
2032 type
2033 };
2034 };
2035
2036 cooling-maps {
2037 map0 {
2038 trip
2039 cooli
2040
2041
2042
2043 };
2044 };
2045 };
2046
2047 cpu3-thermal {
2048 polling-delay = <1000
2049 polling-delay-passive
2050 thermal-sensors = <&l
2051
2052 trips {
2053 cpu3_alert: t
2054 tempe
2055 hyste
2056 type
2057 };
2058
2059 cpu3_crit: tr
2060 tempe
2061 hyste
2062 type
2063 };
2064 };
2065
2066 cooling-maps {
2067 map0 {
2068 trip
2069 cooli
2070
2071
2072
2073 };
2074 };
2075 };
2076
2077 cpu4-thermal {
2078 polling-delay = <1000
2079 polling-delay-passive
2080 thermal-sensors = <&l
2081
2082 trips {
2083 cpu4_alert: t
2084 tempe
2085 hyste
2086 type
2087 };
2088
2089 cpu4_crit: tr
2090 tempe
2091 hyste
2092 type
2093 };
2094 };
2095
2096 cooling-maps {
2097 map0 {
2098 trip
2099 cooli
2100
2101
2102
2103 };
2104 };
2105 };
2106
2107 cpu5-thermal {
2108 polling-delay = <1000
2109 polling-delay-passive
2110 thermal-sensors = <&l
2111
2112 trips {
2113 cpu5_alert: t
2114 tempe
2115 hyste
2116 type
2117 };
2118
2119 cpu5_crit: tr
2120 tempe
2121 hyste
2122 type
2123 };
2124 };
2125
2126 cooling-maps {
2127 map0 {
2128 trip
2129 cooli
2130
2131
2132
2133 };
2134 };
2135 };
2136
2137 cpu6-thermal {
2138 polling-delay = <1000
2139 polling-delay-passive
2140 thermal-sensors = <&l
2141
2142 trips {
2143 cpu6_alert: t
2144 tempe
2145 hyste
2146 type
2147 };
2148
2149 cpu6_crit: tr
2150 tempe
2151 hyste
2152 type
2153 };
2154 };
2155
2156 cooling-maps {
2157 map0 {
2158 trip
2159 cooli
2160
2161
2162
2163 };
2164 };
2165 };
2166
2167 cpu7-thermal {
2168 polling-delay = <1000
2169 polling-delay-passive
2170 thermal-sensors = <&l
2171
2172 trips {
2173 cpu7_alert: t
2174 tempe
2175 hyste
2176 type
2177 };
2178
2179 cpu7_crit: tr
2180 tempe
2181 hyste
2182 type
2183 };
2184 };
2185
2186 cooling-maps {
2187 map0 {
2188 trip
2189 cooli
2190
2191
2192
2193 };
2194 };
2195 };
2196
2197 vpu0-thermal {
2198 polling-delay = <1000
2199 polling-delay-passive
2200 thermal-sensors = <&l
2201
2202 trips {
2203 vpu0_alert: t
2204 tempe
2205 hyste
2206 type
2207 };
2208
2209 vpu0_crit: tr
2210 tempe
2211 hyste
2212 type
2213 };
2214 };
2215 };
2216
2217 vpu1-thermal {
2218 polling-delay = <1000
2219 polling-delay-passive
2220 thermal-sensors = <&l
2221
2222 trips {
2223 vpu1_alert: t
2224 tempe
2225 hyste
2226 type
2227 };
2228
2229 vpu1_crit: tr
2230 tempe
2231 hyste
2232 type
2233 };
2234 };
2235 };
2236
2237 gpu-thermal {
2238 polling-delay = <1000
2239 polling-delay-passive
2240 thermal-sensors = <&l
2241
2242 trips {
2243 gpu0_alert: t
2244 tempe
2245 hyste
2246 type
2247 };
2248
2249 gpu0_crit: tr
2250 tempe
2251 hyste
2252 type
2253 };
2254 };
2255 };
2256
2257 gpu1-thermal {
2258 polling-delay = <1000
2259 polling-delay-passive
2260 thermal-sensors = <&l
2261
2262 trips {
2263 gpu1_alert: t
2264 tempe
2265 hyste
2266 type
2267 };
2268
2269 gpu1_crit: tr
2270 tempe
2271 hyste
2272 type
2273 };
2274 };
2275 };
2276
2277 infra-thermal {
2278 polling-delay = <1000
2279 polling-delay-passive
2280 thermal-sensors = <&l
2281
2282 trips {
2283 infra_alert:
2284 tempe
2285 hyste
2286 type
2287 };
2288
2289 infra_crit: t
2290 tempe
2291 hyste
2292 type
2293 };
2294 };
2295 };
2296
2297 cam-thermal {
2298 polling-delay = <1000
2299 polling-delay-passive
2300 thermal-sensors = <&l
2301
2302 trips {
2303 cam_alert: tr
2304 tempe
2305 hyste
2306 type
2307 };
2308
2309 cam_crit: tri
2310 tempe
2311 hyste
2312 type
2313 };
2314 };
2315 };
2316
2317 md0-thermal {
2318 polling-delay = <1000
2319 polling-delay-passive
2320 thermal-sensors = <&l
2321
2322 trips {
2323 md0_alert: tr
2324 tempe
2325 hyste
2326 type
2327 };
2328
2329 md0_crit: tri
2330 tempe
2331 hyste
2332 type
2333 };
2334 };
2335 };
2336
2337 md1-thermal {
2338 polling-delay = <1000
2339 polling-delay-passive
2340 thermal-sensors = <&l
2341
2342 trips {
2343 md1_alert: tr
2344 tempe
2345 hyste
2346 type
2347 };
2348
2349 md1_crit: tri
2350 tempe
2351 hyste
2352 type
2353 };
2354 };
2355 };
2356
2357 md2-thermal {
2358 polling-delay = <1000
2359 polling-delay-passive
2360 thermal-sensors = <&l
2361
2362 trips {
2363 md2_alert: tr
2364 tempe
2365 hyste
2366 type
2367 };
2368
2369 md2_crit: tri
2370 tempe
2371 hyste
2372 type
2373 };
2374 };
2375 };
2376 };
2377 };
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