1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /*
3 * (C) 2018 MediaTek Inc.
4 * Copyright (C) 2022 BayLibre SAS
5 * Authors: Fabien Parent <fparent@baylibre.com
6 * Bernhard Rosenkränzer <bero@baylib
7 * Alexandre Mergnat <amergnat@baylibr
8 */
9
10 #include <dt-bindings/clock/mediatek,mt8365-cl
11 #include <dt-bindings/interrupt-controller/arm
12 #include <dt-bindings/interrupt-controller/irq
13 #include <dt-bindings/phy/phy.h>
14 #include <dt-bindings/power/mediatek,mt8365-po
15
16 / {
17 compatible = "mediatek,mt8365";
18 interrupt-parent = <&sysirq>;
19 #address-cells = <2>;
20 #size-cells = <2>;
21
22 cpus {
23 #address-cells = <1>;
24 #size-cells = <0>;
25
26 cluster0_opp: opp-table-0 {
27 compatible = "operating-points
28 opp-shared;
29
30 opp-850000000 {
31 opp-hz = /bits/ 64 <85
32 opp-microvolt = <65000
33 };
34
35 opp-918000000 {
36 opp-hz = /bits/ 64 <91
37 opp-microvolt = <66875
38 };
39
40 opp-987000000 {
41 opp-hz = /bits/ 64 <98
42 opp-microvolt = <68750
43 };
44
45 opp-1056000000 {
46 opp-hz = /bits/ 64 <10
47 opp-microvolt = <70625
48 };
49
50 opp-1125000000 {
51 opp-hz = /bits/ 64 <11
52 opp-microvolt = <72500
53 };
54
55 opp-1216000000 {
56 opp-hz = /bits/ 64 <12
57 opp-microvolt = <75000
58 };
59
60 opp-1308000000 {
61 opp-hz = /bits/ 64 <13
62 opp-microvolt = <77500
63 };
64
65 opp-1400000000 {
66 opp-hz = /bits/ 64 <14
67 opp-microvolt = <80000
68 };
69
70 opp-1466000000 {
71 opp-hz = /bits/ 64 <14
72 opp-microvolt = <82500
73 };
74
75 opp-1533000000 {
76 opp-hz = /bits/ 64 <15
77 opp-microvolt = <85000
78 };
79
80 opp-1633000000 {
81 opp-hz = /bits/ 64 <16
82 opp-microvolt = <88750
83 };
84
85 opp-1700000000 {
86 opp-hz = /bits/ 64 <17
87 opp-microvolt = <91250
88 };
89
90 opp-1767000000 {
91 opp-hz = /bits/ 64 <17
92 opp-microvolt = <93750
93 };
94
95 opp-1834000000 {
96 opp-hz = /bits/ 64 <18
97 opp-microvolt = <96250
98 };
99
100 opp-1917000000 {
101 opp-hz = /bits/ 64 <19
102 opp-microvolt = <99375
103 };
104
105 opp-2001000000 {
106 opp-hz = /bits/ 64 <20
107 opp-microvolt = <10250
108 };
109 };
110
111 cpu-map {
112 cluster0 {
113 core0 {
114 cpu =
115 };
116 core1 {
117 cpu =
118 };
119 core2 {
120 cpu =
121 };
122 core3 {
123 cpu =
124 };
125 };
126 };
127
128 cpu0: cpu@0 {
129 device_type = "cpu";
130 compatible = "arm,cort
131 reg = <0x0>;
132 #cooling-cells = <2>;
133 enable-method = "psci"
134 cpu-idle-states = <&CP
135 i-cache-size = <0x8000
136 i-cache-line-size = <6
137 i-cache-sets = <256>;
138 d-cache-size = <0x8000
139 d-cache-line-size = <6
140 d-cache-sets = <256>;
141 next-level-cache = <&l
142 clocks = <&mcucfg CLK_
143 <&apmixedsys
144 clock-names = "cpu", "
145 operating-points-v2 =
146 };
147
148 cpu1: cpu@1 {
149 device_type = "cpu";
150 compatible = "arm,cort
151 reg = <0x1>;
152 #cooling-cells = <2>;
153 enable-method = "psci"
154 cpu-idle-states = <&CP
155 i-cache-size = <0x8000
156 i-cache-line-size = <6
157 i-cache-sets = <256>;
158 d-cache-size = <0x8000
159 d-cache-line-size = <6
160 d-cache-sets = <256>;
161 next-level-cache = <&l
162 clocks = <&mcucfg CLK_
163 <&apmixedsys
164 clock-names = "cpu", "
165 operating-points-v2 =
166 };
167
168 cpu2: cpu@2 {
169 device_type = "cpu";
170 compatible = "arm,cort
171 reg = <0x2>;
172 #cooling-cells = <2>;
173 enable-method = "psci"
174 cpu-idle-states = <&CP
175 i-cache-size = <0x8000
176 i-cache-line-size = <6
177 i-cache-sets = <256>;
178 d-cache-size = <0x8000
179 d-cache-line-size = <6
180 d-cache-sets = <256>;
181 next-level-cache = <&l
182 clocks = <&mcucfg CLK_
183 <&apmixedsys
184 clock-names = "cpu", "
185 operating-points-v2 =
186 };
187
188 cpu3: cpu@3 {
189 device_type = "cpu";
190 compatible = "arm,cort
191 reg = <0x3>;
192 #cooling-cells = <2>;
193 enable-method = "psci"
194 cpu-idle-states = <&CP
195 i-cache-size = <0x8000
196 i-cache-line-size = <6
197 i-cache-sets = <256>;
198 d-cache-size = <0x8000
199 d-cache-line-size = <6
200 d-cache-sets = <256>;
201 next-level-cache = <&l
202 clocks = <&mcucfg CLK_
203 <&apmixedsys
204 clock-names = "cpu", "
205 operating-points-v2 =
206 };
207
208 idle-states {
209 entry-method = "psci";
210
211 CPU_MCDI: cpu-mcdi {
212 compatible = "
213 local-timer-st
214 arm,psci-suspe
215 entry-latency-
216 exit-latency-u
217 min-residency-
218 };
219
220 CLUSTER_MCDI: cluster-
221 compatible = "
222 local-timer-st
223 arm,psci-suspe
224 entry-latency-
225 exit-latency-u
226 min-residency-
227 };
228
229 CLUSTER_DPIDLE: cluste
230 compatible = "
231 local-timer-st
232 arm,psci-suspe
233 entry-latency-
234 exit-latency-u
235 min-residency-
236 };
237 };
238
239 l2: l2-cache {
240 compatible = "cache";
241 cache-level = <2>;
242 cache-size = <0x80000>
243 cache-line-size = <64>
244 cache-sets = <512>;
245 cache-unified;
246 };
247 };
248
249 clk26m: oscillator {
250 compatible = "fixed-clock";
251 #clock-cells = <0>;
252 clock-frequency = <26000000>;
253 clock-output-names = "clk26m";
254 };
255
256 psci {
257 compatible = "arm,psci-1.0";
258 method = "smc";
259 };
260
261 soc {
262 #address-cells = <2>;
263 #size-cells = <2>;
264 compatible = "simple-bus";
265 ranges;
266
267 gic: interrupt-controller@c000
268 compatible = "arm,gic-
269 #interrupt-cells = <3>
270 interrupt-parent = <&g
271 interrupt-controller;
272 reg = <0 0x0c000000 0
273 <0 0x0c080000 0
274 <0 0x0c400000 0
275 <0 0x0c410000 0
276 <0 0x0c420000 0
277
278 interrupts = <GIC_PPI
279 };
280
281 topckgen: syscon@10000000 {
282 compatible = "mediatek
283 reg = <0 0x10000000 0
284 #clock-cells = <1>;
285 };
286
287 infracfg: syscon@10001000 {
288 compatible = "mediatek
289 reg = <0 0x10001000 0
290 #clock-cells = <1>;
291 };
292
293 pericfg: syscon@10003000 {
294 compatible = "mediatek
295 reg = <0 0x10003000 0
296 #clock-cells = <1>;
297 };
298
299 syscfg_pctl: syscfg-pctl@10005
300 compatible = "mediatek
301 reg = <0 0x10005000 0
302 };
303
304 scpsys: syscon@10006000 {
305 compatible = "mediatek
306 reg = <0 0x10006000 0
307
308 /* System Power Manage
309 spm: power-controller
310 compatible = "
311 #address-cells
312 #size-cells =
313 #power-domain-
314
315 /* power domai
316 power-domain@M
317 reg =
318 clocks
319
320
321
322
323 clock-
324
325 #power
326 mediat
327 mediat
328 #addre
329 #size-
330
331 power-
332
333
334
335
336
337
338
339
340
341
342
343
344
345 };
346
347 power-
348
349
350
351 };
352
353 power-
354
355
356
357 };
358
359 power-
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375 };
376 };
377
378 power-domain@M
379 reg =
380 clocks
381
382 clock-
383 #power
384 mediat
385 };
386
387 power-domain@M
388 reg =
389 clocks
390 clock-
391 #power
392 mediat
393 };
394
395 power-domain@M
396 reg =
397 clocks
398
399
400 clock-
401 #power
402 mediat
403 };
404
405 power-domain@M
406 reg =
407 clocks
408
409 clock-
410 #power
411 mediat
412 };
413 };
414 };
415
416 watchdog: watchdog@10007000 {
417 compatible = "mediatek
418 reg = <0 0x10007000 0
419 #reset-cells = <1>;
420 };
421
422 pio: pinctrl@1000b000 {
423 compatible = "mediatek
424 reg = <0 0x1000b000 0
425 mediatek,pctl-regmap =
426 gpio-controller;
427 #gpio-cells = <2>;
428 interrupt-controller;
429 #interrupt-cells = <2>
430 interrupts = <GIC_SPI
431 };
432
433 apmixedsys: syscon@1000c000 {
434 compatible = "mediatek
435 reg = <0 0x1000c000 0
436 #clock-cells = <1>;
437 };
438
439 pwrap: pwrap@1000d000 {
440 compatible = "mediatek
441 reg = <0 0x1000d000 0
442 reg-names = "pwrap";
443 interrupts = <GIC_SPI
444 clocks = <&infracfg CL
445 <&infracfg CL
446 <&infracfg CL
447 <&infracfg CL
448 clock-names = "spi", "
449 };
450
451 keypad: keypad@10010000 {
452 compatible = "mediatek
453 reg = <0 0x10010000 0
454 wakeup-source;
455 interrupts = <GIC_SPI
456 clocks = <&clk26m>;
457 clock-names = "kpd";
458 status = "disabled";
459 };
460
461 mcucfg: syscon@10200000 {
462 compatible = "mediatek
463 reg = <0 0x10200000 0
464 #clock-cells = <1>;
465 };
466
467 sysirq: interrupt-controller@1
468 compatible = "mediatek
469 interrupt-controller;
470 #interrupt-cells = <3>
471 interrupt-parent = <&g
472 reg = <0 0x10200a80 0
473 };
474
475 iommu: iommu@10205000 {
476 compatible = "mediatek
477 reg = <0 0x10205000 0
478 interrupts = <GIC_SPI
479 mediatek,larbs = <&lar
480 #iommu-cells = <1>;
481 };
482
483 infracfg_nao: infracfg@1020e00
484 compatible = "mediatek
485 reg = <0 0x1020e000 0
486 #clock-cells = <1>;
487 };
488
489 rng: rng@1020f000 {
490 compatible = "mediatek
491 reg = <0 0x1020f000 0
492 clocks = <&infracfg CL
493 clock-names = "rng";
494 };
495
496 apdma: dma-controller@11000280
497 compatible = "mediatek
498 reg = <0 0x11000280 0
499 <0 0x11000300 0
500 <0 0x11000380 0
501 <0 0x11000400 0
502 <0 0x11000580 0
503 <0 0x11000600 0
504 interrupts = <GIC_SPI
505 <GIC_SPI
506 <GIC_SPI
507 <GIC_SPI
508 <GIC_SPI
509 <GIC_SPI
510 dma-requests = <6>;
511 clocks = <&infracfg CL
512 clock-names = "apdma";
513 #dma-cells = <1>;
514 };
515
516 uart0: serial@11002000 {
517 compatible = "mediatek
518 reg = <0 0x11002000 0
519 interrupts = <GIC_SPI
520 clocks = <&clk26m>, <&
521 clock-names = "baud",
522 dmas = <&apdma 0>, <&a
523 dma-names = "tx", "rx"
524 status = "disabled";
525 };
526
527 uart1: serial@11003000 {
528 compatible = "mediatek
529 reg = <0 0x11003000 0
530 interrupts = <GIC_SPI
531 clocks = <&clk26m>, <&
532 clock-names = "baud",
533 dmas = <&apdma 2>, <&a
534 dma-names = "tx", "rx"
535 status = "disabled";
536 };
537
538 uart2: serial@11004000 {
539 compatible = "mediatek
540 reg = <0 0x11004000 0
541 interrupts = <GIC_SPI
542 clocks = <&clk26m>, <&
543 clock-names = "baud",
544 dmas = <&apdma 4>, <&a
545 dma-names = "tx", "rx"
546 status = "disabled";
547 };
548
549 pwm: pwm@11006000 {
550 compatible = "mediatek
551 reg = <0 0x11006000 0
552 #pwm-cells = <2>;
553 interrupts = <GIC_SPI
554 clocks = <&infracfg CL
555 <&infracfg CL
556 <&infracfg CL
557 <&infracfg CL
558 <&infracfg CL
559 clock-names = "top", "
560 };
561
562 i2c0: i2c@11007000 {
563 compatible = "mediatek
564 reg = <0 0x11007000 0
565 interrupts = <GIC_SPI
566 clock-div = <1>;
567 clocks = <&infracfg CL
568 clock-names = "main",
569 #address-cells = <1>;
570 #size-cells = <0>;
571 status = "disabled";
572 };
573
574 i2c1: i2c@11008000 {
575 compatible = "mediatek
576 reg = <0 0x11008000 0
577 interrupts = <GIC_SPI
578 clock-div = <1>;
579 clocks = <&infracfg CL
580 clock-names = "main",
581 #address-cells = <1>;
582 #size-cells = <0>;
583 status = "disabled";
584 };
585
586 i2c2: i2c@11009000 {
587 compatible = "mediatek
588 reg = <0 0x11009000 0
589 interrupts = <GIC_SPI
590 clock-div = <1>;
591 clocks = <&infracfg CL
592 clock-names = "main",
593 #address-cells = <1>;
594 #size-cells = <0>;
595 status = "disabled";
596 };
597
598 spi: spi@1100a000 {
599 compatible = "mediatek
600 reg = <0 0x1100a000 0
601 #address-cells = <1>;
602 #size-cells = <0>;
603 interrupts = <GIC_SPI
604 clocks = <&topckgen CL
605 <&topckgen CL
606 <&infracfg CL
607 clock-names = "parent-
608 status = "disabled";
609 };
610
611 i2c3: i2c@1100f000 {
612 compatible = "mediatek
613 reg = <0 0x1100f000 0
614 interrupts = <GIC_SPI
615 clock-div = <1>;
616 clocks = <&infracfg CL
617 clock-names = "main",
618 #address-cells = <1>;
619 #size-cells = <0>;
620 status = "disabled";
621 };
622
623 ssusb: usb@11201000 {
624 compatible = "mediatek
625 reg = <0 0x11201000 0
626 reg-names = "mac", "ip
627 interrupts = <GIC_SPI
628 phys = <&u2port0 PHY_T
629 <&u2port1 PHY_T
630 clocks = <&topckgen CL
631 <&infracfg CL
632 <&infracfg CL
633 <&infracfg CL
634 clock-names = "sys_ck"
635 #address-cells = <2>;
636 #size-cells = <2>;
637 ranges;
638 status = "disabled";
639
640 usb_host: usb@11200000
641 compatible = "
642 reg = <0 0x112
643 reg-names = "m
644 interrupts = <
645 clocks = <&top
646 <&inf
647 <&inf
648 <&inf
649 <&inf
650 clock-names =
651
652 status = "disa
653 };
654 };
655
656 mmc0: mmc@11230000 {
657 compatible = "mediatek
658 reg = <0 0x11230000 0
659 <0 0x11cd0000 0
660 interrupts = <GIC_SPI
661 clocks = <&topckgen CL
662 <&infracfg CL
663 <&infracfg CL
664 clock-names = "source"
665 status = "disabled";
666 };
667
668 mmc1: mmc@11240000 {
669 compatible = "mediatek
670 reg = <0 0x11240000 0
671 <0 0x11c90000 0
672 interrupts = <GIC_SPI
673 clocks = <&topckgen CL
674 <&infracfg CL
675 <&infracfg CL
676 clock-names = "source"
677 status = "disabled";
678 };
679
680 mmc2: mmc@11250000 {
681 compatible = "mediatek
682 reg = <0 0x11250000 0
683 <0 0x11c60000 0
684 interrupts = <GIC_SPI
685 clocks = <&topckgen CL
686 <&infracfg CL
687 <&infracfg CL
688 <&infracfg CL
689 <&infracfg CL
690 clock-names = "source"
691 "bus_clk
692 status = "disabled";
693 };
694
695 ethernet: ethernet@112a0000 {
696 compatible = "mediatek
697 reg = <0 0x112a0000 0
698 mediatek,pericfg = <&i
699 interrupts = <GIC_SPI
700 clocks = <&topckgen CL
701 <&infracfg CL
702 <&infracfg CL
703 clock-names = "core",
704 status = "disabled";
705 };
706
707 u3phy: t-phy@11cc0000 {
708 compatible = "mediatek
709 #address-cells = <1>;
710 #size-cells = <1>;
711 ranges = <0 0 0x11cc00
712
713 u2port0: usb-phy@0 {
714 reg = <0x0 0x4
715 clocks = <&top
716 <&top
717 clock-names =
718 #phy-cells = <
719 };
720
721 u2port1: usb-phy@1000
722 reg = <0x1000
723 clocks = <&top
724 <&top
725 clock-names =
726 #phy-cells = <
727 };
728 };
729
730 mmsys: syscon@14000000 {
731 compatible = "mediatek
732 reg = <0 0x14000000 0
733 #clock-cells = <1>;
734 };
735
736 smi_common: smi@14002000 {
737 compatible = "mediatek
738 reg = <0 0x14002000 0
739 clocks = <&mmsys CLK_M
740 <&mmsys CLK_M
741 <&mmsys CLK_M
742 <&mmsys CLK_M
743 clock-names = "apb", "
744 power-domains = <&spm
745 };
746
747 larb0: larb@14003000 {
748 compatible = "mediatek
749 "mediatek
750 reg = <0 0x14003000 0
751 mediatek,smi = <&smi_c
752 clocks = <&mmsys CLK_M
753 <&mmsys CLK_M
754 clock-names = "apb", "
755 power-domains = <&spm
756 mediatek,larb-id = <0>
757 };
758
759 camsys: syscon@15000000 {
760 compatible = "mediatek
761 reg = <0 0x15000000 0
762 #clock-cells = <1>;
763 };
764
765 larb2: larb@15001000 {
766 compatible = "mediatek
767 "mediatek
768 reg = <0 0x15001000 0
769 mediatek,smi = <&smi_c
770 clocks = <&mmsys CLK_M
771 <&camsys CLK_
772 clock-names = "apb", "
773 power-domains = <&spm
774 mediatek,larb-id = <2>
775 };
776
777 vdecsys: syscon@16000000 {
778 compatible = "mediatek
779 reg = <0 0x16000000 0
780 #clock-cells = <1>;
781 };
782
783 larb3: larb@16010000 {
784 compatible = "mediatek
785 "mediatek
786 reg = <0 0x16010000 0
787 mediatek,smi = <&smi_c
788 clocks = <&vdecsys CLK
789 <&vdecsys CLK
790 clock-names = "apb", "
791 power-domains = <&spm
792 mediatek,larb-id = <3>
793 };
794
795 vencsys: syscon@17000000 {
796 compatible = "mediatek
797 reg = <0 0x17000000 0
798 #clock-cells = <1>;
799 };
800
801 larb1: larb@17010000 {
802 compatible = "mediatek
803 "mediatek
804 reg = <0 0x17010000 0
805 mediatek,smi = <&smi_c
806 clocks = <&vencsys CLK
807 clock-names = "apb", "
808 power-domains = <&spm
809 mediatek,larb-id = <1>
810 };
811
812 apu: syscon@19020000 {
813 compatible = "mediatek
814 reg = <0 0x19020000 0
815 #clock-cells = <1>;
816 };
817
818 afe: audio-controller@11220000
819 compatible = "mediatek
820 reg = <0 0x11220000 0
821 #sound-dai-cells = <0>
822 clocks = <&clk26m>,
823 <&topckgen CL
824 <&topckgen CL
825 <&topckgen CL
826 <&topckgen CL
827 <&topckgen CL
828 <&topckgen CL
829 <&topckgen CL
830 <&topckgen CL
831 <&topckgen CL
832 <&topckgen CL
833 <&topckgen CL
834 <&topckgen CL
835 <&topckgen CL
836 clock-names = "top_clk
837 "top_aud
838 "audio_i
839 "audio_i
840 "audio_i
841 "audio_i
842 "engen1"
843 "engen2"
844 "aud1",
845 "aud2",
846 "i2s0_m_
847 "i2s1_m_
848 "i2s2_m_
849 "i2s3_m_
850 interrupts = <GIC_SPI
851 power-domains = <&spm
852 status = "disabled";
853 };
854 };
855
856 timer {
857 compatible = "arm,armv8-timer"
858 interrupt-parent = <&gic>;
859 interrupts = <GIC_PPI 13 IRQ_T
860 <GIC_PPI 14 IRQ_T
861 <GIC_PPI 11 IRQ_T
862 <GIC_PPI 10 IRQ_T
863 };
864
865 system_clk: dummy13m {
866 compatible = "fixed-clock";
867 clock-frequency = <13000000>;
868 #clock-cells = <0>;
869 };
870
871 systimer: timer@10017000 {
872 compatible = "mediatek,mt8365-
873 reg = <0 0x10017000 0 0x100>;
874 interrupts = <GIC_SPI 138 IRQ_
875 clocks = <&system_clk>;
876 clock-names = "clk13m";
877 };
878 };
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