1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /*
3 * Copyright (C) 2024 Kontron Europe GmbH
4 *
5 * Author: Michael Walle <mwalle@kernel.org>
6 */
7 /dts-v1/;
8
9 #include "mt8195.dtsi"
10 #include "mt6359.dtsi"
11
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/input/input.h>
14 #include <dt-bindings/leds/common.h>
15 #include <dt-bindings/pinctrl/mt8195-pinfunc.h
16 #include <dt-bindings/regulator/mediatek,mt636
17 #include <dt-bindings/spmi/spmi.h>
18
19 / {
20 model = "Kontron 3.5\"-SBC-i1200";
21 compatible = "kontron,3-5-sbc-i1200",
22
23 aliases {
24 mmc0 = &mmc0;
25 mmc1 = &mmc1;
26 serial0 = &uart1;
27 serial1 = &uart2;
28 serial2 = &uart3;
29 serial3 = &uart4;
30 serial4 = &uart0;
31 };
32
33 chosen {
34 stdout-path = "serial0:115200n
35 };
36
37 firmware {
38 optee {
39 compatible = "linaro,o
40 method = "smc";
41 };
42 };
43
44 gpio-keys {
45 compatible = "gpio-keys";
46 pinctrl-names = "default";
47 pinctrl-0 = <&gpio_keys_pins>;
48
49 key-0 {
50 gpios = <&pio 106 GPIO
51 label = "volume_up";
52 linux,code = <KEY_VOLU
53 wakeup-source;
54 debounce-interval = <1
55 };
56 };
57
58 leds {
59 compatible = "gpio-leds";
60 pinctrl-names = "default";
61 pinctrl-0 = <&led_pins>;
62
63 led-0 {
64 gpios = <&pio 107 GPIO
65 default-state = "keep"
66 function = LED_FUNCTIO
67 color = <LED_COLOR_ID_
68 };
69 };
70
71 memory@40000000 {
72 device_type = "memory";
73 reg = <0 0x40000000 0x0 0x8000
74 };
75
76 vsys: regulator-vsys {
77 compatible = "regulator-fixed"
78 regulator-name = "vsys";
79 regulator-always-on;
80 regulator-boot-on;
81 regulator-min-microvolt = <500
82 regulator-max-microvolt = <500
83 };
84
85 reserved-memory {
86 #address-cells = <2>;
87 #size-cells = <2>;
88 ranges;
89
90 /*
91 * 12 MiB reserved for OP-TEE
92 * +-----------------------+ 0
93 * | SHMEM 2MiB |
94 * +-----------------------+ 0
95 * | | TA_RAM 8MiB |
96 * + TZDRAM +--------------+ 0
97 * | | TEE_RAM 2MiB |
98 * +-----------------------+ 0
99 */
100 optee_reserved: optee@43200000
101 no-map;
102 reg = <0 0x43200000 0
103 };
104
105 scp_mem: memory@50000000 {
106 compatible = "shared-d
107 reg = <0 0x50000000 0
108 no-map;
109 };
110
111 vpu_mem: memory@53000000 {
112 compatible = "shared-d
113 reg = <0 0x53000000 0
114 };
115
116 /* 2 MiB reserved for ARM Trus
117 bl31_secmon_mem: memory@546000
118 no-map;
119 reg = <0 0x54600000 0x
120 };
121
122 snd_dma_mem: memory@60000000 {
123 compatible = "shared-d
124 reg = <0 0x60000000 0
125 no-map;
126 };
127
128 apu_mem: memory@62000000 {
129 compatible = "shared-d
130 reg = <0 0x62000000 0
131 };
132 };
133
134 thermal_sensor0: thermal-sensor-0 {
135 compatible = "generic-adc-ther
136 #thermal-sensor-cells = <0>;
137 io-channels = <&auxadc 0>;
138 io-channel-names = "sensor-cha
139 temperature-lookup-table = <(-
140 (-
141 (-
142 (-
143 (
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175 };
176
177 thermal_sensor1: thermal-sensor-1 {
178 compatible = "generic-adc-ther
179 #thermal-sensor-cells = <0>;
180 io-channels = <&auxadc 1>;
181 io-channel-names = "sensor-cha
182 temperature-lookup-table = <(-
183 (-
184 (-
185 (-
186 (
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218 };
219
220 thermal_sensor2: thermal-sensor-2 {
221 compatible = "generic-adc-ther
222 #thermal-sensor-cells = <0>;
223 io-channels = <&auxadc 2>;
224 io-channel-names = "sensor-cha
225 temperature-lookup-table = <(-
226 (-
227 (-
228 (-
229 (
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261 };
262 };
263
264 &auxadc {
265 status = "okay";
266 };
267
268 ð {
269 phy-mode ="rgmii-id";
270 phy-handle = <ðernet_phy0>;
271 pinctrl-names = "default", "sleep";
272 pinctrl-0 = <ð_default_pins>;
273 pinctrl-1 = <ð_sleep_pins>;
274 status = "okay";
275
276 mdio {
277 ethernet_phy0: ethernet-phy@1
278 compatible = "ethernet
279 reg = <0x1>;
280 interrupts-extended =
281 reset-assert-us = <100
282 reset-deassert-us = <8
283 reset-gpios = <&pio 93
284 };
285 };
286 };
287
288 &gpu {
289 status = "okay";
290 mali-supply = <&mt6315_7_vbuck1>;
291 };
292
293 /* CSI1/CSI2 connector */
294 &i2c0 {
295 pinctrl-names = "default";
296 pinctrl-0 = <&i2c0_pins>;
297 clock-frequency = <100000>;
298 status = "okay";
299 };
300
301 /* CSI3 connector */
302 &i2c1 {
303 pinctrl-names = "default";
304 pinctrl-0 = <&i2c1_pins>;
305 clock-frequency = <100000>;
306 status = "okay";
307 };
308
309 &i2c2 {
310 pinctrl-names = "default";
311 pinctrl-0 = <&i2c2_pins>;
312 clock-frequency = <400000>;
313 status = "okay";
314
315 /* LVDS bridge @f */
316 };
317
318 /* Touch panel connector */
319 &i2c3 {
320 pinctrl-names = "default";
321 pinctrl-0 = <&i2c3_pins>;
322 clock-frequency = <100000>;
323 status = "okay";
324 };
325
326 /* B2B connector */
327 &i2c4 {
328 clock-frequency = <100000>;
329 pinctrl-0 = <&i2c4_pins>;
330 pinctrl-names = "default";
331 status = "okay";
332 };
333
334 &i2c6 {
335 clock-frequency = <400000>;
336 pinctrl-0 = <&i2c6_pins>;
337 pinctrl-names = "default";
338 status = "okay";
339
340 mt6360: pmic@34 {
341 compatible = "mediatek,mt6360"
342 reg = <0x34>;
343 interrupt-controller;
344 interrupts-extended = <&pio 10
345 interrupt-names = "IRQB";
346 #interrupt-cells = <1>;
347
348 regulator {
349 compatible = "mediatek
350 LDO_VIN1-supply = <&vs
351 LDO_VIN2-supply = <&vs
352 LDO_VIN3-supply = <&vs
353
354 mt6360_buck1: BUCK1 {
355 regulator-name
356 regulator-min-
357 regulator-max-
358 regulator-allo
359
360
361 regulator-alwa
362 };
363
364 mt6360_buck2: BUCK2 {
365 regulator-name
366 regulator-min-
367 regulator-max-
368 regulator-allo
369
370
371 regulator-alwa
372 };
373
374 mt6360_ldo1: LDO1 {
375 regulator-name
376 regulator-min-
377 regulator-max-
378 regulator-allo
379
380 };
381
382 mt6360_ldo2: LDO2 {
383 regulator-name
384 regulator-min-
385 regulator-max-
386 regulator-allo
387
388 };
389
390 mt6360_ldo3: LDO3 {
391 regulator-name
392 regulator-min-
393 regulator-max-
394 regulator-allo
395
396 };
397
398 mt6360_ldo5: LDO5 {
399 regulator-name
400 regulator-min-
401 regulator-max-
402 regulator-allo
403
404 };
405
406 mt6360_ldo6: LDO6 {
407 regulator-name
408 regulator-min-
409 regulator-max-
410 regulator-allo
411
412 };
413
414 mt6360_ldo7: LDO7 {
415 regulator-name
416 regulator-min-
417 regulator-max-
418 regulator-allo
419
420 regulator-alwa
421 };
422 };
423 };
424 };
425
426 &mmc0 {
427 pinctrl-names = "default", "state_uhs"
428 pinctrl-0 = <&mmc0_default_pins>;
429 pinctrl-1 = <&mmc0_uhs_pins>;
430 bus-width = <8>;
431 max-frequency = <200000000>;
432 hs400-ds-delay = <0x14c11>;
433 cap-mmc-highspeed;
434 cap-mmc-hw-reset;
435 mmc-hs200-1_8v;
436 mmc-hs400-1_8v;
437 no-sdio;
438 no-sd;
439 non-removable;
440 vmmc-supply = <&mt6359_vemc_1_ldo_reg>
441 vqmmc-supply = <&mt6359_vufs_ldo_reg>;
442 status = "okay";
443 };
444
445 &mmc1 {
446 pinctrl-names = "default", "state_uhs"
447 pinctrl-0 = <&mmc1_default_pins>, <&mm
448 pinctrl-1 = <&mmc1_default_pins>;
449 cd-gpios = <&pio 129 GPIO_ACTIVE_LOW>;
450 bus-width = <4>;
451 max-frequency = <200000000>;
452 cap-sd-highspeed;
453 sd-uhs-sdr50;
454 sd-uhs-sdr104;
455 no-mmc;
456 vmmc-supply = <&mt6360_ldo5>;
457 vqmmc-supply = <&mt6360_ldo3>;
458 status = "okay";
459 };
460
461 &mt6359_vbbck_ldo_reg {
462 regulator-always-on;
463 };
464
465 &mt6359_vcore_buck_reg {
466 regulator-always-on;
467 };
468
469 &mt6359_vgpu11_buck_reg {
470 regulator-always-on;
471 };
472
473 &mt6359_vproc1_buck_reg {
474 regulator-always-on;
475 };
476
477 &mt6359_vproc2_buck_reg {
478 regulator-always-on;
479 };
480
481 &mt6359_vpu_buck_reg {
482 regulator-always-on;
483 };
484
485 &mt6359_vrf12_ldo_reg {
486 regulator-always-on;
487 };
488
489 &mt6359_vsram_md_ldo_reg {
490 regulator-always-on;
491 };
492
493 &mt6359_vsram_others_ldo_reg {
494 regulator-always-on;
495 };
496
497 &nor_flash {
498 pinctrl-names = "default";
499 pinctrl-0 = <&nor_pins_default>;
500 status = "okay";
501
502 flash@0 {
503 compatible = "jedec,spi-nor";
504 reg = <0>;
505 spi-max-frequency = <52000000>
506 spi-rx-bus-width = <2>;
507 spi-tx-bus-width = <2>;
508 };
509 };
510
511 &pcie0 {
512 pinctrl-names = "default";
513 pinctrl-0 = <&pcie0_pins_default>;
514 status = "okay";
515 };
516
517 &pcie1 {
518 pinctrl-names = "default";
519 pinctrl-0 = <&pcie1_pins_default>;
520 status = "okay";
521 };
522
523 &pciephy {
524 status = "okay";
525 };
526
527 &pio {
528 eth_default_pins: eth-default-pins {
529 pins-txd {
530 pinmux = <PINMUX_GPIO7
531 <PINMUX_GPIO7
532 <PINMUX_GPIO7
533 <PINMUX_GPIO8
534 drive-strength = <8>;
535 };
536
537 pins-rxd {
538 pinmux = <PINMUX_GPIO8
539 <PINMUX_GPIO8
540 <PINMUX_GPIO8
541 <PINMUX_GPIO8
542 };
543
544 pins-cc {
545 pinmux = <PINMUX_GPIO8
546 <PINMUX_GPIO8
547 <PINMUX_GPIO8
548 <PINMUX_GPIO8
549 drive-strength = <8>;
550 };
551
552 pins-mdio {
553 pinmux = <PINMUX_GPIO8
554 <PINMUX_GPIO9
555 input-enable;
556 };
557
558 pins-power {
559 pinmux = <PINMUX_GPIO9
560 <PINMUX_GPIO9
561 output-high;
562 };
563
564 pins-reset {
565 pinmux = <PINMUX_GPIO9
566 output-high;
567 };
568
569 pins-interrupt {
570 pinmux = <PINMUX_GPIO9
571 input-enable;
572 };
573 };
574
575 eth_sleep_pins: eth-sleep-pins {
576 pins-txd {
577 pinmux = <PINMUX_GPIO7
578 <PINMUX_GPIO7
579 <PINMUX_GPIO7
580 <PINMUX_GPIO8
581 };
582
583 pins-cc {
584 pinmux = <PINMUX_GPIO8
585 <PINMUX_GPIO8
586 <PINMUX_GPIO8
587 <PINMUX_GPIO8
588 };
589
590 pins-rxd {
591 pinmux = <PINMUX_GPIO8
592 <PINMUX_GPIO8
593 <PINMUX_GPIO8
594 <PINMUX_GPIO8
595 };
596
597 pins-mdio {
598 pinmux = <PINMUX_GPIO8
599 <PINMUX_GPIO9
600 input-disable;
601 bias-disable;
602 };
603 };
604
605 gpio_keys_pins: gpio-keys-pins {
606 pins {
607 pinmux = <PINMUX_GPIO1
608 input-enable;
609 };
610 };
611
612 i2c0_pins: i2c0-pins {
613 pins {
614 pinmux = <PINMUX_GPIO8
615 <PINMUX_GPIO9
616 bias-pull-up = <MTK_PU
617 drive-strength-microam
618 };
619 };
620
621 i2c1_pins: i2c1-pins {
622 pins {
623 pinmux = <PINMUX_GPIO1
624 <PINMUX_GPIO1
625 bias-pull-up = <MTK_PU
626 drive-strength-microam
627 };
628 };
629
630 i2c2_pins: i2c2-default-pins {
631 pins-bus {
632 pinmux = <PINMUX_GPIO1
633 <PINMUX_GPIO1
634 bias-pull-up = <MTK_PU
635 drive-strength-microam
636 };
637 };
638
639 i2c3_pins: i2c3-pins {
640 pins {
641 pinmux = <PINMUX_GPIO1
642 <PINMUX_GPIO1
643 bias-pull-up = <MTK_PU
644 drive-strength-microam
645 };
646 };
647
648 i2c4_pins: i2c4-pins {
649 pins {
650 pinmux = <PINMUX_GPIO1
651 <PINMUX_GPIO1
652 bias-pull-up = <MTK_PU
653 drive-strength-microam
654 };
655 };
656
657 i2c6_pins: i2c6-pins {
658 pins {
659 pinmux = <PINMUX_GPIO2
660 <PINMUX_GPIO2
661 bias-pull-up;
662 drive-strength-microam
663 };
664 };
665
666 mmc0_default_pins: mmc0-default-pins {
667 pins-clk {
668 pinmux = <PINMUX_GPIO1
669 drive-strength = <6>;
670 bias-pull-down = <MTK_
671 };
672
673 pins-cmd-dat {
674 pinmux = <PINMUX_GPIO1
675 <PINMUX_GPIO1
676 <PINMUX_GPIO1
677 <PINMUX_GPIO1
678 <PINMUX_GPIO1
679 <PINMUX_GPIO1
680 <PINMUX_GPIO1
681 <PINMUX_GPIO1
682 <PINMUX_GPIO1
683 input-enable;
684 drive-strength = <6>;
685 bias-pull-up = <MTK_PU
686 };
687
688 pins-rst {
689 pinmux = <PINMUX_GPIO1
690 drive-strength = <6>;
691 bias-pull-up = <MTK_PU
692 };
693 };
694
695 mmc0_uhs_pins: mmc0-uhs-pins {
696 pins-clk {
697 pinmux = <PINMUX_GPIO1
698 drive-strength = <8>;
699 bias-pull-down = <MTK_
700 };
701
702 pins-cmd-dat {
703 pinmux = <PINMUX_GPIO1
704 <PINMUX_GPIO1
705 <PINMUX_GPIO1
706 <PINMUX_GPIO1
707 <PINMUX_GPIO1
708 <PINMUX_GPIO1
709 <PINMUX_GPIO1
710 <PINMUX_GPIO1
711 <PINMUX_GPIO1
712 input-enable;
713 drive-strength = <8>;
714 bias-pull-up = <MTK_PU
715 };
716
717 pins-ds {
718 pinmux = <PINMUX_GPIO1
719 drive-strength = <8>;
720 bias-pull-down = <MTK_
721 };
722
723 pins-rst {
724 pinmux = <PINMUX_GPIO1
725 drive-strength = <8>;
726 bias-pull-up = <MTK_PU
727 };
728 };
729
730 mmc1_default_pins: mmc1-default-pins {
731 pins-clk {
732 pinmux = <PINMUX_GPIO1
733 drive-strength = <8>;
734 bias-pull-down = <MTK_
735 };
736
737 pins-cmd-dat {
738 pinmux = <PINMUX_GPIO1
739 <PINMUX_GPIO1
740 <PINMUX_GPIO1
741 <PINMUX_GPIO1
742 <PINMUX_GPIO1
743 input-enable;
744 drive-strength = <8>;
745 bias-pull-up = <MTK_PU
746 };
747 };
748
749 mmc1_detect_pins: mmc1-detect-pins {
750 pins-insert {
751 pinmux = <PINMUX_GPIO1
752 bias-pull-up;
753 };
754 };
755
756 nor_pins_default: nor-default-pins {
757 pins-ck-io {
758 pinmux = <PINMUX_GPIO1
759 <PINMUX_GPIO1
760 <PINMUX_GPIO1
761 drive-strength = <6>;
762 bias-pull-down;
763 };
764
765 pins-cs {
766 pinmux = <PINMUX_GPIO1
767 drive-strength = <6>;
768 bias-pull-up;
769 };
770 };
771
772 pcie0_pins_default: pcie0-default-pins
773 pins-bus {
774 pinmux = <PINMUX_GPIO1
775 <PINMUX_GPIO2
776 <PINMUX_GPIO2
777 bias-pull-up;
778 };
779 };
780
781 pcie1_pins_default: pcie1-default-pins
782 pins-bus {
783 pinmux = <PINMUX_GPIO0
784 <PINMUX_GPIO1
785 <PINMUX_GPIO2
786 bias-pull-up = <MTK_PU
787 };
788 };
789
790 led_pins: led-pins {
791 pins-power-en {
792 pinmux = <PINMUX_GPIO1
793 output-high;
794 };
795 };
796
797 spi0_pins: spi0-default-pins {
798 pins-cs-mosi-clk {
799 pinmux = <PINMUX_GPIO1
800 <PINMUX_GPIO1
801 <PINMUX_GPIO1
802 bias-disable;
803 };
804
805 pins-miso {
806 pinmux = <PINMUX_GPIO1
807 bias-pull-down;
808 };
809 };
810
811 spi1_pins: spi1-default-pins {
812 pins-cs-mosi-clk {
813 pinmux = <PINMUX_GPIO1
814 <PINMUX_GPIO1
815 <PINMUX_GPIO1
816 bias-disable;
817 };
818
819 pins-miso {
820 pinmux = <PINMUX_GPIO1
821 bias-pull-down;
822 };
823 };
824
825 uart0_pins: uart0-pins {
826 pins-rx {
827 pinmux = <PINMUX_GPIO9
828 input-enable;
829 bias-pull-up;
830 };
831
832 pins-tx {
833 pinmux = <PINMUX_GPIO9
834 };
835 };
836
837 uart1_pins: uart1-pins {
838 pins-rx {
839 pinmux = <PINMUX_GPIO1
840 input-enable;
841 bias-pull-up;
842 };
843
844 pins-tx {
845 pinmux = <PINMUX_GPIO1
846 };
847
848 pins-rts {
849 pinmux = <PINMUX_GPIO1
850 };
851
852 pins-cts {
853 pinmux = <PINMUX_GPIO1
854 input-enable;
855 };
856 };
857
858 uart2_pins: uart2-pins {
859 pins-rx {
860 pinmux = <PINMUX_GPIO6
861 input-enable;
862 bias-pull-up;
863 };
864
865 pins-tx {
866 pinmux = <PINMUX_GPIO6
867 };
868
869 pins-rts {
870 pinmux = <PINMUX_GPIO6
871 };
872
873 pins-cts {
874 pinmux = <PINMUX_GPIO6
875 input-enable;
876 };
877 };
878
879 uart3_pins: uart3-pins {
880 pins-rx {
881 pinmux = <PINMUX_GPIO5
882 input-enable;
883 bias-pull-up = <MTK_PU
884 };
885
886 pins-tx {
887 pinmux = <PINMUX_GPIO4
888 };
889 };
890
891 uart4_pins: uart4-pins {
892 pins-rx {
893 pinmux = <PINMUX_GPIO7
894 input-enable;
895 bias-pull-up;
896 };
897
898 pins-tx {
899 pinmux = <PINMUX_GPIO6
900 };
901 };
902 };
903
904 &pmic {
905 interrupts-extended = <&pio 222 IRQ_TY
906 };
907
908 &scp {
909 memory-region = <&scp_mem>;
910 firmware-name = "mediatek/mt8195/scp.i
911 status = "okay";
912 };
913
914 &spmi {
915 #address-cells = <2>;
916 #size-cells = <0>;
917
918 mt6315@6 {
919 compatible = "mediatek,mt6315-
920 reg = <0x6 SPMI_USID>;
921
922 regulators {
923 mt6315_6_vbuck1: vbuck
924 regulator-name
925 regulator-min-
926 regulator-max-
927 regulator-enab
928 regulator-ramp
929 regulator-allo
930 regulator-alwa
931 };
932 };
933 };
934
935 mt6315@7 {
936 compatible = "mediatek,mt6315-
937 reg = <0x7 SPMI_USID>;
938
939 regulators {
940 mt6315_7_vbuck1: vbuck
941 regulator-name
942 regulator-min-
943 regulator-max-
944 regulator-enab
945 regulator-ramp
946 regulator-allo
947 regulator-alwa
948 };
949 };
950 };
951 };
952
953 /* USB3.2 front port */
954 &ssusb0 {
955 dr_mode = "host";
956 vusb33-supply = <&mt6359_vusb_ldo_reg>
957 status = "okay";
958 };
959
960 /* USB2.0 M.2 Key-E */
961 &ssusb2 {
962 vusb33-supply = <&mt6359_vusb_ldo_reg>
963 status = "okay";
964 };
965
966 /* USB2.0 to on-board usb hub */
967 &ssusb3 {
968 vusb33-supply = <&mt6359_vusb_ldo_reg>
969 status = "okay";
970 };
971
972 &spi0 {
973 pinctrl-names = "default";
974 pinctrl-0 = <&spi0_pins>;
975 mediatek,pad-select = <0>;
976 status = "okay";
977
978 tpm: tpm@0 {
979 compatible = "infineon,slb9670
980 reg = <0>;
981 spi-max-frequency = <18500000>
982 };
983 };
984
985 /* B2B connector */
986 &spi1 {
987 pinctrl-names = "default";
988 pinctrl-0 = <&spi1_pins>;
989 mediatek,pad-select = <0>;
990 status = "okay";
991 };
992
993 &thermal_zones {
994 cpu-thermal {
995 polling-delay = <1000>; /* mil
996 polling-delay-passive = <0>; /
997 thermal-sensors = <&thermal_se
998
999 trips {
1000 trip-alert {
1001 temperature =
1002 hysteresis =
1003 type = "passi
1004 };
1005
1006 trip-crit {
1007 temperature =
1008 hysteresis =
1009 type = "criti
1010 };
1011 };
1012 };
1013
1014 pcb-top-thermal {
1015 polling-delay = <1000>; /* mi
1016 polling-delay-passive = <0>;
1017 thermal-sensors = <&thermal_s
1018
1019 trips {
1020 trip-alert {
1021 temperature =
1022 hysteresis =
1023 type = "passi
1024 };
1025
1026 trip-crit {
1027 temperature =
1028 hysteresis =
1029 type = "criti
1030 };
1031 };
1032 };
1033
1034 pcb-bottom-thermal {
1035 polling-delay = <1000>; /* mi
1036 polling-delay-passive = <0>;
1037 thermal-sensors = <&thermal_s
1038
1039 trips {
1040 trip-alert {
1041 temperature =
1042 hysteresis =
1043 type = "passi
1044 };
1045
1046 trip-crit {
1047 temperature =
1048 hysteresis =
1049 type = "criti
1050 };
1051 };
1052 };
1053 };
1054
1055 &uart0 {
1056 pinctrl-names = "default";
1057 pinctrl-0 = <&uart0_pins>;
1058 status = "okay";
1059 };
1060
1061 &uart1 {
1062 pinctrl-names = "default";
1063 pinctrl-0 = <&uart1_pins>;
1064 uart-has-rtscts;
1065 status = "okay";
1066 };
1067
1068 &uart2 {
1069 pinctrl-names = "default";
1070 pinctrl-0 = <&uart2_pins>;
1071 uart-has-rtscts;
1072 status = "okay";
1073 };
1074
1075 &uart3 {
1076 pinctrl-names = "default";
1077 pinctrl-0 = <&uart3_pins>;
1078 status = "okay";
1079 };
1080
1081 &uart4 {
1082 pinctrl-names = "default";
1083 pinctrl-0 = <&uart4_pins>;
1084 status = "okay";
1085 };
1086
1087 /* USB3 */
1088 &u3phy0 {
1089 status = "okay";
1090 };
1091
1092 /* PCIe1/USB2 */
1093 &u3phy1 {
1094 status = "okay";
1095 };
1096
1097 /* USB2 */
1098 &u3phy2 {
1099 status = "okay";
1100 };
1101
1102 /* USB2 */
1103 &u3phy3 {
1104 status = "okay";
1105 };
1106
1107 /* USB3.2 front port */
1108 &xhci0 {
1109 status = "okay";
1110 };
1111
1112 /* USB2.0 M.2 Key-B */
1113 &xhci1 {
1114 phys = <&u2port1 PHY_TYPE_USB2>;
1115 vusb33-supply = <&mt6359_vusb_ldo_reg
1116 mediatek,u3p-dis-msk = <0x01>;
1117 status = "okay";
1118 };
1119
1120 /* USB2.0 M.2 Key-E */
1121 &xhci2 {
1122 status = "okay";
1123 };
1124
1125 /* USB2.0 to on-board usb hub */
1126 &xhci3 {
1127 status = "okay";
1128 };
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