1 // SPDX-License-Identifier: BSD-3-Clause
2 /*
3 * sc7280 SoC device tree source
4 *
5 * Copyright (c) 2020-2021, The Linux Foundati
6 */
7 #include <dt-bindings/clock/qcom,camcc-sc7280.
8 #include <dt-bindings/clock/qcom,dispcc-sc7280
9 #include <dt-bindings/clock/qcom,gcc-sc7280.h>
10 #include <dt-bindings/clock/qcom,gpucc-sc7280.
11 #include <dt-bindings/clock/qcom,lpassaudiocc-
12 #include <dt-bindings/clock/qcom,lpasscorecc-s
13 #include <dt-bindings/clock/qcom,rpmh.h>
14 #include <dt-bindings/clock/qcom,videocc-sc728
15 #include <dt-bindings/dma/qcom-gpi.h>
16 #include <dt-bindings/firmware/qcom,scm.h>
17 #include <dt-bindings/gpio/gpio.h>
18 #include <dt-bindings/interconnect/qcom,icc.h>
19 #include <dt-bindings/interconnect/qcom,osm-l3
20 #include <dt-bindings/interconnect/qcom,sc7280
21 #include <dt-bindings/interrupt-controller/arm
22 #include <dt-bindings/mailbox/qcom-ipcc.h>
23 #include <dt-bindings/phy/phy-qcom-qmp.h>
24 #include <dt-bindings/power/qcom-rpmpd.h>
25 #include <dt-bindings/reset/qcom,sdm845-aoss.h
26 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
27 #include <dt-bindings/soc/qcom,apr.h>
28 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
29 #include <dt-bindings/sound/qcom,lpass.h>
30 #include <dt-bindings/thermal/thermal.h>
31
32 / {
33 interrupt-parent = <&intc>;
34
35 #address-cells = <2>;
36 #size-cells = <2>;
37
38 chosen { };
39
40 aliases {
41 i2c0 = &i2c0;
42 i2c1 = &i2c1;
43 i2c2 = &i2c2;
44 i2c3 = &i2c3;
45 i2c4 = &i2c4;
46 i2c5 = &i2c5;
47 i2c6 = &i2c6;
48 i2c7 = &i2c7;
49 i2c8 = &i2c8;
50 i2c9 = &i2c9;
51 i2c10 = &i2c10;
52 i2c11 = &i2c11;
53 i2c12 = &i2c12;
54 i2c13 = &i2c13;
55 i2c14 = &i2c14;
56 i2c15 = &i2c15;
57 mmc1 = &sdhc_1;
58 mmc2 = &sdhc_2;
59 spi0 = &spi0;
60 spi1 = &spi1;
61 spi2 = &spi2;
62 spi3 = &spi3;
63 spi4 = &spi4;
64 spi5 = &spi5;
65 spi6 = &spi6;
66 spi7 = &spi7;
67 spi8 = &spi8;
68 spi9 = &spi9;
69 spi10 = &spi10;
70 spi11 = &spi11;
71 spi12 = &spi12;
72 spi13 = &spi13;
73 spi14 = &spi14;
74 spi15 = &spi15;
75 };
76
77 clocks {
78 xo_board: xo-board {
79 compatible = "fixed-cl
80 clock-frequency = <768
81 #clock-cells = <0>;
82 };
83
84 sleep_clk: sleep-clk {
85 compatible = "fixed-cl
86 clock-frequency = <320
87 #clock-cells = <0>;
88 };
89 };
90
91 reserved-memory {
92 #address-cells = <2>;
93 #size-cells = <2>;
94 ranges;
95
96 wlan_ce_mem: wlan-ce@4cd000 {
97 no-map;
98 reg = <0x0 0x004cd000
99 };
100
101 hyp_mem: hyp@80000000 {
102 reg = <0x0 0x80000000
103 no-map;
104 };
105
106 xbl_mem: xbl@80600000 {
107 reg = <0x0 0x80600000
108 no-map;
109 };
110
111 aop_mem: aop@80800000 {
112 reg = <0x0 0x80800000
113 no-map;
114 };
115
116 aop_cmd_db_mem: aop-cmd-db@808
117 reg = <0x0 0x80860000
118 compatible = "qcom,cmd
119 no-map;
120 };
121
122 reserved_xbl_uefi_log: xbl-uef
123 reg = <0x0 0x80884000
124 no-map;
125 };
126
127 sec_apps_mem: sec-apps@808ff00
128 reg = <0x0 0x808ff000
129 no-map;
130 };
131
132 smem_mem: smem@80900000 {
133 reg = <0x0 0x80900000
134 no-map;
135 };
136
137 cpucp_mem: cpucp@80b00000 {
138 no-map;
139 reg = <0x0 0x80b00000
140 };
141
142 wlan_fw_mem: wlan-fw@80c00000
143 reg = <0x0 0x80c00000
144 no-map;
145 };
146
147 adsp_mem: adsp@86700000 {
148 reg = <0x0 0x86700000
149 no-map;
150 };
151
152 video_mem: video@8b200000 {
153 reg = <0x0 0x8b200000
154 no-map;
155 };
156
157 cdsp_mem: cdsp@88f00000 {
158 reg = <0x0 0x88f00000
159 no-map;
160 };
161
162 ipa_fw_mem: ipa-fw@8b700000 {
163 reg = <0 0x8b700000 0
164 no-map;
165 };
166
167 gpu_zap_mem: zap@8b71a000 {
168 reg = <0 0x8b71a000 0
169 no-map;
170 };
171
172 mpss_mem: mpss@8b800000 {
173 reg = <0x0 0x8b800000
174 no-map;
175 };
176
177 wpss_mem: wpss@9ae00000 {
178 reg = <0x0 0x9ae00000
179 no-map;
180 };
181
182 rmtfs_mem: rmtfs@9c900000 {
183 compatible = "qcom,rmt
184 reg = <0x0 0x9c900000
185 no-map;
186
187 qcom,client-id = <1>;
188 qcom,vmid = <QCOM_SCM_
189 };
190 };
191
192 cpus {
193 #address-cells = <2>;
194 #size-cells = <0>;
195
196 CPU0: cpu@0 {
197 device_type = "cpu";
198 compatible = "qcom,kry
199 reg = <0x0 0x0>;
200 clocks = <&cpufreq_hw
201 enable-method = "psci"
202 power-domains = <&CPU_
203 power-domain-names = "
204 next-level-cache = <&L
205 operating-points-v2 =
206 capacity-dmips-mhz = <
207 dynamic-power-coeffici
208 interconnects = <&gem_
209 <&epss
210 qcom,freq-domain = <&c
211 #cooling-cells = <2>;
212 L2_0: l2-cache {
213 compatible = "
214 cache-level =
215 cache-unified;
216 next-level-cac
217 L3_0: l3-cache
218 compat
219 cache-
220 cache-
221 };
222 };
223 };
224
225 CPU1: cpu@100 {
226 device_type = "cpu";
227 compatible = "qcom,kry
228 reg = <0x0 0x100>;
229 clocks = <&cpufreq_hw
230 enable-method = "psci"
231 power-domains = <&CPU_
232 power-domain-names = "
233 next-level-cache = <&L
234 operating-points-v2 =
235 capacity-dmips-mhz = <
236 dynamic-power-coeffici
237 interconnects = <&gem_
238 <&epss
239 qcom,freq-domain = <&c
240 #cooling-cells = <2>;
241 L2_100: l2-cache {
242 compatible = "
243 cache-level =
244 cache-unified;
245 next-level-cac
246 };
247 };
248
249 CPU2: cpu@200 {
250 device_type = "cpu";
251 compatible = "qcom,kry
252 reg = <0x0 0x200>;
253 clocks = <&cpufreq_hw
254 enable-method = "psci"
255 power-domains = <&CPU_
256 power-domain-names = "
257 next-level-cache = <&L
258 operating-points-v2 =
259 capacity-dmips-mhz = <
260 dynamic-power-coeffici
261 interconnects = <&gem_
262 <&epss
263 qcom,freq-domain = <&c
264 #cooling-cells = <2>;
265 L2_200: l2-cache {
266 compatible = "
267 cache-level =
268 cache-unified;
269 next-level-cac
270 };
271 };
272
273 CPU3: cpu@300 {
274 device_type = "cpu";
275 compatible = "qcom,kry
276 reg = <0x0 0x300>;
277 clocks = <&cpufreq_hw
278 enable-method = "psci"
279 power-domains = <&CPU_
280 power-domain-names = "
281 next-level-cache = <&L
282 operating-points-v2 =
283 capacity-dmips-mhz = <
284 dynamic-power-coeffici
285 interconnects = <&gem_
286 <&epss
287 qcom,freq-domain = <&c
288 #cooling-cells = <2>;
289 L2_300: l2-cache {
290 compatible = "
291 cache-level =
292 cache-unified;
293 next-level-cac
294 };
295 };
296
297 CPU4: cpu@400 {
298 device_type = "cpu";
299 compatible = "qcom,kry
300 reg = <0x0 0x400>;
301 clocks = <&cpufreq_hw
302 enable-method = "psci"
303 power-domains = <&CPU_
304 power-domain-names = "
305 next-level-cache = <&L
306 operating-points-v2 =
307 capacity-dmips-mhz = <
308 dynamic-power-coeffici
309 interconnects = <&gem_
310 <&epss
311 qcom,freq-domain = <&c
312 #cooling-cells = <2>;
313 L2_400: l2-cache {
314 compatible = "
315 cache-level =
316 cache-unified;
317 next-level-cac
318 };
319 };
320
321 CPU5: cpu@500 {
322 device_type = "cpu";
323 compatible = "qcom,kry
324 reg = <0x0 0x500>;
325 clocks = <&cpufreq_hw
326 enable-method = "psci"
327 power-domains = <&CPU_
328 power-domain-names = "
329 next-level-cache = <&L
330 operating-points-v2 =
331 capacity-dmips-mhz = <
332 dynamic-power-coeffici
333 interconnects = <&gem_
334 <&epss
335 qcom,freq-domain = <&c
336 #cooling-cells = <2>;
337 L2_500: l2-cache {
338 compatible = "
339 cache-level =
340 cache-unified;
341 next-level-cac
342 };
343 };
344
345 CPU6: cpu@600 {
346 device_type = "cpu";
347 compatible = "qcom,kry
348 reg = <0x0 0x600>;
349 clocks = <&cpufreq_hw
350 enable-method = "psci"
351 power-domains = <&CPU_
352 power-domain-names = "
353 next-level-cache = <&L
354 operating-points-v2 =
355 capacity-dmips-mhz = <
356 dynamic-power-coeffici
357 interconnects = <&gem_
358 <&epss
359 qcom,freq-domain = <&c
360 #cooling-cells = <2>;
361 L2_600: l2-cache {
362 compatible = "
363 cache-level =
364 cache-unified;
365 next-level-cac
366 };
367 };
368
369 CPU7: cpu@700 {
370 device_type = "cpu";
371 compatible = "qcom,kry
372 reg = <0x0 0x700>;
373 clocks = <&cpufreq_hw
374 enable-method = "psci"
375 power-domains = <&CPU_
376 power-domain-names = "
377 next-level-cache = <&L
378 operating-points-v2 =
379 capacity-dmips-mhz = <
380 dynamic-power-coeffici
381 interconnects = <&gem_
382 <&epss
383 qcom,freq-domain = <&c
384 #cooling-cells = <2>;
385 L2_700: l2-cache {
386 compatible = "
387 cache-level =
388 cache-unified;
389 next-level-cac
390 };
391 };
392
393 cpu-map {
394 cluster0 {
395 core0 {
396 cpu =
397 };
398
399 core1 {
400 cpu =
401 };
402
403 core2 {
404 cpu =
405 };
406
407 core3 {
408 cpu =
409 };
410
411 core4 {
412 cpu =
413 };
414
415 core5 {
416 cpu =
417 };
418
419 core6 {
420 cpu =
421 };
422
423 core7 {
424 cpu =
425 };
426 };
427 };
428
429 idle-states {
430 entry-method = "psci";
431
432 LITTLE_CPU_SLEEP_0: cp
433 compatible = "
434 idle-state-nam
435 arm,psci-suspe
436 entry-latency-
437 exit-latency-u
438 min-residency-
439 local-timer-st
440 };
441
442 LITTLE_CPU_SLEEP_1: cp
443 compatible = "
444 idle-state-nam
445 arm,psci-suspe
446 entry-latency-
447 exit-latency-u
448 min-residency-
449 local-timer-st
450 };
451
452 BIG_CPU_SLEEP_0: cpu-s
453 compatible = "
454 idle-state-nam
455 arm,psci-suspe
456 entry-latency-
457 exit-latency-u
458 min-residency-
459 local-timer-st
460 };
461
462 BIG_CPU_SLEEP_1: cpu-s
463 compatible = "
464 idle-state-nam
465 arm,psci-suspe
466 entry-latency-
467 exit-latency-u
468 min-residency-
469 local-timer-st
470 };
471 };
472
473 domain_idle_states: domain-idl
474 CLUSTER_SLEEP_APSS_OFF
475 compatible = "
476 arm,psci-suspe
477 entry-latency-
478 exit-latency-u
479 min-residency-
480 };
481
482 CLUSTER_SLEEP_CX_RET:
483 compatible = "
484 arm,psci-suspe
485 entry-latency-
486 exit-latency-u
487 min-residency-
488 };
489
490 CLUSTER_SLEEP_LLCC_OFF
491 compatible = "
492 arm,psci-suspe
493 entry-latency-
494 exit-latency-u
495 min-residency-
496 };
497 };
498 };
499
500 cpu0_opp_table: opp-table-cpu0 {
501 compatible = "operating-points
502 opp-shared;
503
504 cpu0_opp_300mhz: opp-300000000
505 opp-hz = /bits/ 64 <30
506 opp-peak-kBps = <80000
507 };
508
509 cpu0_opp_691mhz: opp-691200000
510 opp-hz = /bits/ 64 <69
511 opp-peak-kBps = <80000
512 };
513
514 cpu0_opp_806mhz: opp-806400000
515 opp-hz = /bits/ 64 <80
516 opp-peak-kBps = <80000
517 };
518
519 cpu0_opp_941mhz: opp-940800000
520 opp-hz = /bits/ 64 <94
521 opp-peak-kBps = <18040
522 };
523
524 cpu0_opp_1152mhz: opp-11520000
525 opp-hz = /bits/ 64 <11
526 opp-peak-kBps = <21880
527 };
528
529 cpu0_opp_1325mhz: opp-13248000
530 opp-hz = /bits/ 64 <13
531 opp-peak-kBps = <21880
532 };
533
534 cpu0_opp_1517mhz: opp-15168000
535 opp-hz = /bits/ 64 <15
536 opp-peak-kBps = <30720
537 };
538
539 cpu0_opp_1651mhz: opp-16512000
540 opp-hz = /bits/ 64 <16
541 opp-peak-kBps = <30720
542 };
543
544 cpu0_opp_1805mhz: opp-18048000
545 opp-hz = /bits/ 64 <18
546 opp-peak-kBps = <40680
547 };
548
549 cpu0_opp_1958mhz: opp-19584000
550 opp-hz = /bits/ 64 <19
551 opp-peak-kBps = <40680
552 };
553
554 cpu0_opp_2016mhz: opp-20160000
555 opp-hz = /bits/ 64 <20
556 opp-peak-kBps = <62200
557 };
558 };
559
560 cpu4_opp_table: opp-table-cpu4 {
561 compatible = "operating-points
562 opp-shared;
563
564 cpu4_opp_691mhz: opp-691200000
565 opp-hz = /bits/ 64 <69
566 opp-peak-kBps = <18040
567 };
568
569 cpu4_opp_941mhz: opp-940800000
570 opp-hz = /bits/ 64 <94
571 opp-peak-kBps = <21880
572 };
573
574 cpu4_opp_1229mhz: opp-12288000
575 opp-hz = /bits/ 64 <12
576 opp-peak-kBps = <40680
577 };
578
579 cpu4_opp_1344mhz: opp-13440000
580 opp-hz = /bits/ 64 <13
581 opp-peak-kBps = <40680
582 };
583
584 cpu4_opp_1517mhz: opp-15168000
585 opp-hz = /bits/ 64 <15
586 opp-peak-kBps = <40680
587 };
588
589 cpu4_opp_1651mhz: opp-16512000
590 opp-hz = /bits/ 64 <16
591 opp-peak-kBps = <62200
592 };
593
594 cpu4_opp_1901mhz: opp-19008000
595 opp-hz = /bits/ 64 <19
596 opp-peak-kBps = <62200
597 };
598
599 cpu4_opp_2054mhz: opp-20544000
600 opp-hz = /bits/ 64 <20
601 opp-peak-kBps = <62200
602 };
603
604 cpu4_opp_2112mhz: opp-21120000
605 opp-hz = /bits/ 64 <21
606 opp-peak-kBps = <62200
607 };
608
609 cpu4_opp_2131mhz: opp-21312000
610 opp-hz = /bits/ 64 <21
611 opp-peak-kBps = <62200
612 };
613
614 cpu4_opp_2208mhz: opp-22080000
615 opp-hz = /bits/ 64 <22
616 opp-peak-kBps = <62200
617 };
618
619 cpu4_opp_2400mhz: opp-24000000
620 opp-hz = /bits/ 64 <24
621 opp-peak-kBps = <85320
622 };
623
624 cpu4_opp_2611mhz: opp-26112000
625 opp-hz = /bits/ 64 <26
626 opp-peak-kBps = <85320
627 };
628 };
629
630 cpu7_opp_table: opp-table-cpu7 {
631 compatible = "operating-points
632 opp-shared;
633
634 cpu7_opp_806mhz: opp-806400000
635 opp-hz = /bits/ 64 <80
636 opp-peak-kBps = <18040
637 };
638
639 cpu7_opp_1056mhz: opp-10560000
640 opp-hz = /bits/ 64 <10
641 opp-peak-kBps = <21880
642 };
643
644 cpu7_opp_1325mhz: opp-13248000
645 opp-hz = /bits/ 64 <13
646 opp-peak-kBps = <40680
647 };
648
649 cpu7_opp_1517mhz: opp-15168000
650 opp-hz = /bits/ 64 <15
651 opp-peak-kBps = <40680
652 };
653
654 cpu7_opp_1766mhz: opp-17664000
655 opp-hz = /bits/ 64 <17
656 opp-peak-kBps = <62200
657 };
658
659 cpu7_opp_1862mhz: opp-18624000
660 opp-hz = /bits/ 64 <18
661 opp-peak-kBps = <62200
662 };
663
664 cpu7_opp_2035mhz: opp-20352000
665 opp-hz = /bits/ 64 <20
666 opp-peak-kBps = <62200
667 };
668
669 cpu7_opp_2112mhz: opp-21120000
670 opp-hz = /bits/ 64 <21
671 opp-peak-kBps = <62200
672 };
673
674 cpu7_opp_2208mhz: opp-22080000
675 opp-hz = /bits/ 64 <22
676 opp-peak-kBps = <62200
677 };
678
679 cpu7_opp_2381mhz: opp-23808000
680 opp-hz = /bits/ 64 <23
681 opp-peak-kBps = <68320
682 };
683
684 cpu7_opp_2400mhz: opp-24000000
685 opp-hz = /bits/ 64 <24
686 opp-peak-kBps = <85320
687 };
688
689 cpu7_opp_2515mhz: opp-25152000
690 opp-hz = /bits/ 64 <25
691 opp-peak-kBps = <85320
692 };
693
694 cpu7_opp_2707mhz: opp-27072000
695 opp-hz = /bits/ 64 <27
696 opp-peak-kBps = <85320
697 };
698
699 cpu7_opp_3014mhz: opp-30144000
700 opp-hz = /bits/ 64 <30
701 opp-peak-kBps = <85320
702 };
703 };
704
705 memory@80000000 {
706 device_type = "memory";
707 /* We expect the bootloader to
708 reg = <0 0x80000000 0 0>;
709 };
710
711 firmware {
712 scm: scm {
713 compatible = "qcom,scm
714 qcom,dload-mode = <&tc
715 };
716 };
717
718 clk_virt: interconnect {
719 compatible = "qcom,sc7280-clk-
720 #interconnect-cells = <2>;
721 qcom,bcm-voters = <&apps_bcm_v
722 };
723
724 smem {
725 compatible = "qcom,smem";
726 memory-region = <&smem_mem>;
727 hwlocks = <&tcsr_mutex 3>;
728 };
729
730 smp2p-adsp {
731 compatible = "qcom,smp2p";
732 qcom,smem = <443>, <429>;
733 interrupts-extended = <&ipcc I
734 I
735 I
736 mboxes = <&ipcc IPCC_CLIENT_LP
737 IPCC_MPROC_SIG
738
739 qcom,local-pid = <0>;
740 qcom,remote-pid = <2>;
741
742 adsp_smp2p_out: master-kernel
743 qcom,entry-name = "mas
744 #qcom,smem-state-cells
745 };
746
747 adsp_smp2p_in: slave-kernel {
748 qcom,entry-name = "sla
749 interrupt-controller;
750 #interrupt-cells = <2>
751 };
752 };
753
754 smp2p-cdsp {
755 compatible = "qcom,smp2p";
756 qcom,smem = <94>, <432>;
757 interrupts-extended = <&ipcc I
758 I
759 I
760 mboxes = <&ipcc IPCC_CLIENT_CD
761 IPCC_MPROC_SIG
762
763 qcom,local-pid = <0>;
764 qcom,remote-pid = <5>;
765
766 cdsp_smp2p_out: master-kernel
767 qcom,entry-name = "mas
768 #qcom,smem-state-cells
769 };
770
771 cdsp_smp2p_in: slave-kernel {
772 qcom,entry-name = "sla
773 interrupt-controller;
774 #interrupt-cells = <2>
775 };
776 };
777
778 smp2p-mpss {
779 compatible = "qcom,smp2p";
780 qcom,smem = <435>, <428>;
781 interrupts-extended = <&ipcc I
782 I
783 I
784 mboxes = <&ipcc IPCC_CLIENT_MP
785 IPCC_MPROC_SIG
786
787 qcom,local-pid = <0>;
788 qcom,remote-pid = <1>;
789
790 modem_smp2p_out: master-kernel
791 qcom,entry-name = "mas
792 #qcom,smem-state-cells
793 };
794
795 modem_smp2p_in: slave-kernel {
796 qcom,entry-name = "sla
797 interrupt-controller;
798 #interrupt-cells = <2>
799 };
800
801 ipa_smp2p_out: ipa-ap-to-modem
802 qcom,entry-name = "ipa
803 #qcom,smem-state-cells
804 };
805
806 ipa_smp2p_in: ipa-modem-to-ap
807 qcom,entry-name = "ipa
808 interrupt-controller;
809 #interrupt-cells = <2>
810 };
811 };
812
813 smp2p-wpss {
814 compatible = "qcom,smp2p";
815 qcom,smem = <617>, <616>;
816 interrupts-extended = <&ipcc I
817 I
818 I
819 mboxes = <&ipcc IPCC_CLIENT_WP
820 IPCC_MPROC_SIG
821
822 qcom,local-pid = <0>;
823 qcom,remote-pid = <13>;
824
825 wpss_smp2p_out: master-kernel
826 qcom,entry-name = "mas
827 #qcom,smem-state-cells
828 };
829
830 wpss_smp2p_in: slave-kernel {
831 qcom,entry-name = "sla
832 interrupt-controller;
833 #interrupt-cells = <2>
834 };
835
836 wlan_smp2p_out: wlan-ap-to-wps
837 qcom,entry-name = "wla
838 #qcom,smem-state-cells
839 };
840
841 wlan_smp2p_in: wlan-wpss-to-ap
842 qcom,entry-name = "wla
843 interrupt-controller;
844 #interrupt-cells = <2>
845 };
846 };
847
848 pmu {
849 compatible = "arm,armv8-pmuv3"
850 interrupts = <GIC_PPI 7 IRQ_TY
851 };
852
853 psci {
854 compatible = "arm,psci-1.0";
855 method = "smc";
856
857 CPU_PD0: power-domain-cpu0 {
858 #power-domain-cells =
859 power-domains = <&CLUS
860 domain-idle-states = <
861 };
862
863 CPU_PD1: power-domain-cpu1 {
864 #power-domain-cells =
865 power-domains = <&CLUS
866 domain-idle-states = <
867 };
868
869 CPU_PD2: power-domain-cpu2 {
870 #power-domain-cells =
871 power-domains = <&CLUS
872 domain-idle-states = <
873 };
874
875 CPU_PD3: power-domain-cpu3 {
876 #power-domain-cells =
877 power-domains = <&CLUS
878 domain-idle-states = <
879 };
880
881 CPU_PD4: power-domain-cpu4 {
882 #power-domain-cells =
883 power-domains = <&CLUS
884 domain-idle-states = <
885 };
886
887 CPU_PD5: power-domain-cpu5 {
888 #power-domain-cells =
889 power-domains = <&CLUS
890 domain-idle-states = <
891 };
892
893 CPU_PD6: power-domain-cpu6 {
894 #power-domain-cells =
895 power-domains = <&CLUS
896 domain-idle-states = <
897 };
898
899 CPU_PD7: power-domain-cpu7 {
900 #power-domain-cells =
901 power-domains = <&CLUS
902 domain-idle-states = <
903 };
904
905 CLUSTER_PD: power-domain-clust
906 #power-domain-cells =
907 domain-idle-states = <
908 };
909 };
910
911 qspi_opp_table: opp-table-qspi {
912 compatible = "operating-points
913
914 opp-75000000 {
915 opp-hz = /bits/ 64 <75
916 required-opps = <&rpmh
917 };
918
919 opp-150000000 {
920 opp-hz = /bits/ 64 <15
921 required-opps = <&rpmh
922 };
923
924 opp-200000000 {
925 opp-hz = /bits/ 64 <20
926 required-opps = <&rpmh
927 };
928
929 opp-300000000 {
930 opp-hz = /bits/ 64 <30
931 required-opps = <&rpmh
932 };
933 };
934
935 qup_opp_table: opp-table-qup {
936 compatible = "operating-points
937
938 opp-75000000 {
939 opp-hz = /bits/ 64 <75
940 required-opps = <&rpmh
941 };
942
943 opp-100000000 {
944 opp-hz = /bits/ 64 <10
945 required-opps = <&rpmh
946 };
947
948 opp-128000000 {
949 opp-hz = /bits/ 64 <12
950 required-opps = <&rpmh
951 };
952 };
953
954 soc: soc@0 {
955 #address-cells = <2>;
956 #size-cells = <2>;
957 ranges = <0 0 0 0 0x10 0>;
958 dma-ranges = <0 0 0 0 0x10 0>;
959 compatible = "simple-bus";
960
961 gcc: clock-controller@100000 {
962 compatible = "qcom,gcc
963 reg = <0 0x00100000 0
964 clocks = <&rpmhcc RPMH
965 <&rpmhcc RPMH
966 <0>, <&pcie1_
967 <&ufs_mem_phy
968 <&usb_1_qmpph
969 clock-names = "bi_tcxo
970 "pcie_0_
971 "ufs_phy
972 "ufs_phy
973 "usb3_ph
974 #clock-cells = <1>;
975 #reset-cells = <1>;
976 #power-domain-cells =
977 power-domains = <&rpmh
978 };
979
980 ipcc: mailbox@408000 {
981 compatible = "qcom,sc7
982 reg = <0 0x00408000 0
983 interrupts = <GIC_SPI
984 interrupt-controller;
985 #interrupt-cells = <3>
986 #mbox-cells = <2>;
987 };
988
989 qfprom: efuse@784000 {
990 compatible = "qcom,sc7
991 reg = <0 0x00784000 0
992 <0 0x00780000 0
993 <0 0x00782000 0
994 <0 0x00786000 0
995 clocks = <&gcc GCC_SEC
996 clock-names = "core";
997 power-domains = <&rpmh
998 #address-cells = <1>;
999 #size-cells = <1>;
1000
1001 gpu_speed_bin: gpu-sp
1002 reg = <0x1e9
1003 bits = <5 8>;
1004 };
1005 };
1006
1007 sdhc_1: mmc@7c4000 {
1008 compatible = "qcom,sc
1009 pinctrl-names = "defa
1010 pinctrl-0 = <&sdc1_cl
1011 pinctrl-1 = <&sdc1_cl
1012 status = "disabled";
1013
1014 reg = <0 0x007c4000 0
1015 <0 0x007c5000 0
1016 reg-names = "hc", "cq
1017
1018 iommus = <&apps_smmu
1019 interrupts = <GIC_SPI
1020 <GIC_SPI
1021 interrupt-names = "hc
1022
1023 clocks = <&gcc GCC_SD
1024 <&gcc GCC_SD
1025 <&rpmhcc RPM
1026 clock-names = "iface"
1027 interconnects = <&agg
1028 <&gem
1029 interconnect-names =
1030 power-domains = <&rpm
1031 operating-points-v2 =
1032
1033 bus-width = <8>;
1034 supports-cqe;
1035 dma-coherent;
1036
1037 qcom,dll-config = <0x
1038 qcom,ddr-config = <0x
1039
1040 mmc-ddr-1_8v;
1041 mmc-hs200-1_8v;
1042 mmc-hs400-1_8v;
1043 mmc-hs400-enhanced-st
1044
1045 resets = <&gcc GCC_SD
1046
1047 sdhc1_opp_table: opp-
1048 compatible =
1049
1050 opp-100000000
1051 opp-h
1052 requi
1053 opp-p
1054 opp-a
1055 };
1056
1057 opp-384000000
1058 opp-h
1059 requi
1060 opp-p
1061 opp-a
1062 };
1063 };
1064 };
1065
1066 gpi_dma0: dma-controller@9000
1067 #dma-cells = <3>;
1068 compatible = "qcom,sc
1069 reg = <0 0x00900000 0
1070 interrupts = <GIC_SPI
1071 <GIC_SPI
1072 <GIC_SPI
1073 <GIC_SPI
1074 <GIC_SPI
1075 <GIC_SPI
1076 <GIC_SPI
1077 <GIC_SPI
1078 <GIC_SPI
1079 <GIC_SPI
1080 <GIC_SPI
1081 <GIC_SPI
1082 dma-channels = <12>;
1083 dma-channel-mask = <0
1084 iommus = <&apps_smmu
1085 status = "disabled";
1086 };
1087
1088 qupv3_id_0: geniqup@9c0000 {
1089 compatible = "qcom,ge
1090 reg = <0 0x009c0000 0
1091 clocks = <&gcc GCC_QU
1092 <&gcc GCC_QU
1093 clock-names = "m-ahb"
1094 #address-cells = <2>;
1095 #size-cells = <2>;
1096 ranges;
1097 iommus = <&apps_smmu
1098 status = "disabled";
1099
1100 i2c0: i2c@980000 {
1101 compatible =
1102 reg = <0 0x00
1103 clocks = <&gc
1104 clock-names =
1105 pinctrl-names
1106 pinctrl-0 = <
1107 interrupts =
1108 #address-cell
1109 #size-cells =
1110 interconnects
1111
1112
1113 interconnect-
1114
1115 power-domains
1116 required-opps
1117 dmas = <&gpi_
1118 <&gpi_
1119 dma-names = "
1120 status = "dis
1121 };
1122
1123 spi0: spi@980000 {
1124 compatible =
1125 reg = <0 0x00
1126 clocks = <&gc
1127 clock-names =
1128 pinctrl-names
1129 pinctrl-0 = <
1130 interrupts =
1131 #address-cell
1132 #size-cells =
1133 power-domains
1134 operating-poi
1135 interconnects
1136
1137 interconnect-
1138 dmas = <&gpi_
1139 <&gpi_
1140 dma-names = "
1141 status = "dis
1142 };
1143
1144 uart0: serial@980000
1145 compatible =
1146 reg = <0 0x00
1147 clocks = <&gc
1148 clock-names =
1149 pinctrl-names
1150 pinctrl-0 = <
1151 interrupts =
1152 power-domains
1153 operating-poi
1154 interconnects
1155
1156 interconnect-
1157 status = "dis
1158 };
1159
1160 i2c1: i2c@984000 {
1161 compatible =
1162 reg = <0 0x00
1163 clocks = <&gc
1164 clock-names =
1165 pinctrl-names
1166 pinctrl-0 = <
1167 interrupts =
1168 #address-cell
1169 #size-cells =
1170 interconnects
1171
1172
1173 interconnect-
1174
1175 power-domains
1176 required-opps
1177 dmas = <&gpi_
1178 <&gpi_
1179 dma-names = "
1180 status = "dis
1181 };
1182
1183 spi1: spi@984000 {
1184 compatible =
1185 reg = <0 0x00
1186 clocks = <&gc
1187 clock-names =
1188 pinctrl-names
1189 pinctrl-0 = <
1190 interrupts =
1191 #address-cell
1192 #size-cells =
1193 power-domains
1194 operating-poi
1195 interconnects
1196
1197 interconnect-
1198 dmas = <&gpi_
1199 <&gpi_
1200 dma-names = "
1201 status = "dis
1202 };
1203
1204 uart1: serial@984000
1205 compatible =
1206 reg = <0 0x00
1207 clocks = <&gc
1208 clock-names =
1209 pinctrl-names
1210 pinctrl-0 = <
1211 interrupts =
1212 power-domains
1213 operating-poi
1214 interconnects
1215
1216 interconnect-
1217 status = "dis
1218 };
1219
1220 i2c2: i2c@988000 {
1221 compatible =
1222 reg = <0 0x00
1223 clocks = <&gc
1224 clock-names =
1225 pinctrl-names
1226 pinctrl-0 = <
1227 interrupts =
1228 #address-cell
1229 #size-cells =
1230 interconnects
1231
1232
1233 interconnect-
1234
1235 power-domains
1236 required-opps
1237 dmas = <&gpi_
1238 <&gpi_
1239 dma-names = "
1240 status = "dis
1241 };
1242
1243 spi2: spi@988000 {
1244 compatible =
1245 reg = <0 0x00
1246 clocks = <&gc
1247 clock-names =
1248 pinctrl-names
1249 pinctrl-0 = <
1250 interrupts =
1251 #address-cell
1252 #size-cells =
1253 power-domains
1254 operating-poi
1255 interconnects
1256
1257 interconnect-
1258 dmas = <&gpi_
1259 <&gpi_
1260 dma-names = "
1261 status = "dis
1262 };
1263
1264 uart2: serial@988000
1265 compatible =
1266 reg = <0 0x00
1267 clocks = <&gc
1268 clock-names =
1269 pinctrl-names
1270 pinctrl-0 = <
1271 interrupts =
1272 power-domains
1273 operating-poi
1274 interconnects
1275
1276 interconnect-
1277 status = "dis
1278 };
1279
1280 i2c3: i2c@98c000 {
1281 compatible =
1282 reg = <0 0x00
1283 clocks = <&gc
1284 clock-names =
1285 pinctrl-names
1286 pinctrl-0 = <
1287 interrupts =
1288 #address-cell
1289 #size-cells =
1290 interconnects
1291
1292
1293 interconnect-
1294
1295 power-domains
1296 required-opps
1297 dmas = <&gpi_
1298 <&gpi_
1299 dma-names = "
1300 status = "dis
1301 };
1302
1303 spi3: spi@98c000 {
1304 compatible =
1305 reg = <0 0x00
1306 clocks = <&gc
1307 clock-names =
1308 pinctrl-names
1309 pinctrl-0 = <
1310 interrupts =
1311 #address-cell
1312 #size-cells =
1313 power-domains
1314 operating-poi
1315 interconnects
1316
1317 interconnect-
1318 dmas = <&gpi_
1319 <&gpi_
1320 dma-names = "
1321 status = "dis
1322 };
1323
1324 uart3: serial@98c000
1325 compatible =
1326 reg = <0 0x00
1327 clocks = <&gc
1328 clock-names =
1329 pinctrl-names
1330 pinctrl-0 = <
1331 interrupts =
1332 power-domains
1333 operating-poi
1334 interconnects
1335
1336 interconnect-
1337 status = "dis
1338 };
1339
1340 i2c4: i2c@990000 {
1341 compatible =
1342 reg = <0 0x00
1343 clocks = <&gc
1344 clock-names =
1345 pinctrl-names
1346 pinctrl-0 = <
1347 interrupts =
1348 #address-cell
1349 #size-cells =
1350 interconnects
1351
1352
1353 interconnect-
1354
1355 power-domains
1356 required-opps
1357 dmas = <&gpi_
1358 <&gpi_
1359 dma-names = "
1360 status = "dis
1361 };
1362
1363 spi4: spi@990000 {
1364 compatible =
1365 reg = <0 0x00
1366 clocks = <&gc
1367 clock-names =
1368 pinctrl-names
1369 pinctrl-0 = <
1370 interrupts =
1371 #address-cell
1372 #size-cells =
1373 power-domains
1374 operating-poi
1375 interconnects
1376
1377 interconnect-
1378 dmas = <&gpi_
1379 <&gpi_
1380 dma-names = "
1381 status = "dis
1382 };
1383
1384 uart4: serial@990000
1385 compatible =
1386 reg = <0 0x00
1387 clocks = <&gc
1388 clock-names =
1389 pinctrl-names
1390 pinctrl-0 = <
1391 interrupts =
1392 power-domains
1393 operating-poi
1394 interconnects
1395
1396 interconnect-
1397 status = "dis
1398 };
1399
1400 i2c5: i2c@994000 {
1401 compatible =
1402 reg = <0 0x00
1403 clocks = <&gc
1404 clock-names =
1405 pinctrl-names
1406 pinctrl-0 = <
1407 interrupts =
1408 #address-cell
1409 #size-cells =
1410 interconnects
1411
1412
1413 interconnect-
1414
1415 power-domains
1416 required-opps
1417 dmas = <&gpi_
1418 <&gpi_
1419 dma-names = "
1420 status = "dis
1421 };
1422
1423 spi5: spi@994000 {
1424 compatible =
1425 reg = <0 0x00
1426 clocks = <&gc
1427 clock-names =
1428 pinctrl-names
1429 pinctrl-0 = <
1430 interrupts =
1431 #address-cell
1432 #size-cells =
1433 power-domains
1434 operating-poi
1435 interconnects
1436
1437 interconnect-
1438 dmas = <&gpi_
1439 <&gpi_
1440 dma-names = "
1441 status = "dis
1442 };
1443
1444 uart5: serial@994000
1445 compatible =
1446 reg = <0 0x00
1447 clocks = <&gc
1448 clock-names =
1449 pinctrl-names
1450 pinctrl-0 = <
1451 interrupts =
1452 power-domains
1453 operating-poi
1454 interconnects
1455
1456 interconnect-
1457 status = "dis
1458 };
1459
1460 i2c6: i2c@998000 {
1461 compatible =
1462 reg = <0 0x00
1463 clocks = <&gc
1464 clock-names =
1465 pinctrl-names
1466 pinctrl-0 = <
1467 interrupts =
1468 #address-cell
1469 #size-cells =
1470 interconnects
1471
1472
1473 interconnect-
1474
1475 power-domains
1476 required-opps
1477 dmas = <&gpi_
1478 <&gpi_
1479 dma-names = "
1480 status = "dis
1481 };
1482
1483 spi6: spi@998000 {
1484 compatible =
1485 reg = <0 0x00
1486 clocks = <&gc
1487 clock-names =
1488 pinctrl-names
1489 pinctrl-0 = <
1490 interrupts =
1491 #address-cell
1492 #size-cells =
1493 power-domains
1494 operating-poi
1495 interconnects
1496
1497 interconnect-
1498 dmas = <&gpi_
1499 <&gpi_
1500 dma-names = "
1501 status = "dis
1502 };
1503
1504 uart6: serial@998000
1505 compatible =
1506 reg = <0 0x00
1507 clocks = <&gc
1508 clock-names =
1509 pinctrl-names
1510 pinctrl-0 = <
1511 interrupts =
1512 power-domains
1513 operating-poi
1514 interconnects
1515
1516 interconnect-
1517 status = "dis
1518 };
1519
1520 i2c7: i2c@99c000 {
1521 compatible =
1522 reg = <0 0x00
1523 clocks = <&gc
1524 clock-names =
1525 pinctrl-names
1526 pinctrl-0 = <
1527 interrupts =
1528 #address-cell
1529 #size-cells =
1530 interconnects
1531
1532
1533 interconnect-
1534
1535 power-domains
1536 required-opps
1537 dmas = <&gpi_
1538 <&gpi_
1539 dma-names = "
1540 status = "dis
1541 };
1542
1543 spi7: spi@99c000 {
1544 compatible =
1545 reg = <0 0x00
1546 clocks = <&gc
1547 clock-names =
1548 pinctrl-names
1549 pinctrl-0 = <
1550 interrupts =
1551 #address-cell
1552 #size-cells =
1553 power-domains
1554 operating-poi
1555 interconnects
1556
1557 interconnect-
1558 dmas = <&gpi_
1559 <&gpi_
1560 dma-names = "
1561 status = "dis
1562 };
1563
1564 uart7: serial@99c000
1565 compatible =
1566 reg = <0 0x00
1567 clocks = <&gc
1568 clock-names =
1569 pinctrl-names
1570 pinctrl-0 = <
1571 interrupts =
1572 power-domains
1573 operating-poi
1574 interconnects
1575
1576 interconnect-
1577 status = "dis
1578 };
1579 };
1580
1581 gpi_dma1: dma-controller@a000
1582 #dma-cells = <3>;
1583 compatible = "qcom,sc
1584 reg = <0 0x00a00000 0
1585 interrupts = <GIC_SPI
1586 <GIC_SPI
1587 <GIC_SPI
1588 <GIC_SPI
1589 <GIC_SPI
1590 <GIC_SPI
1591 <GIC_SPI
1592 <GIC_SPI
1593 <GIC_SPI
1594 <GIC_SPI
1595 <GIC_SPI
1596 <GIC_SPI
1597 dma-channels = <12>;
1598 dma-channel-mask = <0
1599 iommus = <&apps_smmu
1600 status = "disabled";
1601 };
1602
1603 qupv3_id_1: geniqup@ac0000 {
1604 compatible = "qcom,ge
1605 reg = <0 0x00ac0000 0
1606 clocks = <&gcc GCC_QU
1607 <&gcc GCC_QU
1608 clock-names = "m-ahb"
1609 #address-cells = <2>;
1610 #size-cells = <2>;
1611 ranges;
1612 iommus = <&apps_smmu
1613 status = "disabled";
1614
1615 i2c8: i2c@a80000 {
1616 compatible =
1617 reg = <0 0x00
1618 clocks = <&gc
1619 clock-names =
1620 pinctrl-names
1621 pinctrl-0 = <
1622 interrupts =
1623 #address-cell
1624 #size-cells =
1625 interconnects
1626
1627
1628 interconnect-
1629
1630 power-domains
1631 required-opps
1632 dmas = <&gpi_
1633 <&gpi_
1634 dma-names = "
1635 status = "dis
1636 };
1637
1638 spi8: spi@a80000 {
1639 compatible =
1640 reg = <0 0x00
1641 clocks = <&gc
1642 clock-names =
1643 pinctrl-names
1644 pinctrl-0 = <
1645 interrupts =
1646 #address-cell
1647 #size-cells =
1648 power-domains
1649 operating-poi
1650 interconnects
1651
1652 interconnect-
1653 dmas = <&gpi_
1654 <&gpi_
1655 dma-names = "
1656 status = "dis
1657 };
1658
1659 uart8: serial@a80000
1660 compatible =
1661 reg = <0 0x00
1662 clocks = <&gc
1663 clock-names =
1664 pinctrl-names
1665 pinctrl-0 = <
1666 interrupts =
1667 power-domains
1668 operating-poi
1669 interconnects
1670
1671 interconnect-
1672 status = "dis
1673 };
1674
1675 i2c9: i2c@a84000 {
1676 compatible =
1677 reg = <0 0x00
1678 clocks = <&gc
1679 clock-names =
1680 pinctrl-names
1681 pinctrl-0 = <
1682 interrupts =
1683 #address-cell
1684 #size-cells =
1685 interconnects
1686
1687
1688 interconnect-
1689
1690 power-domains
1691 required-opps
1692 dmas = <&gpi_
1693 <&gpi_
1694 dma-names = "
1695 status = "dis
1696 };
1697
1698 spi9: spi@a84000 {
1699 compatible =
1700 reg = <0 0x00
1701 clocks = <&gc
1702 clock-names =
1703 pinctrl-names
1704 pinctrl-0 = <
1705 interrupts =
1706 #address-cell
1707 #size-cells =
1708 power-domains
1709 operating-poi
1710 interconnects
1711
1712 interconnect-
1713 dmas = <&gpi_
1714 <&gpi_
1715 dma-names = "
1716 status = "dis
1717 };
1718
1719 uart9: serial@a84000
1720 compatible =
1721 reg = <0 0x00
1722 clocks = <&gc
1723 clock-names =
1724 pinctrl-names
1725 pinctrl-0 = <
1726 interrupts =
1727 power-domains
1728 operating-poi
1729 interconnects
1730
1731 interconnect-
1732 status = "dis
1733 };
1734
1735 i2c10: i2c@a88000 {
1736 compatible =
1737 reg = <0 0x00
1738 clocks = <&gc
1739 clock-names =
1740 pinctrl-names
1741 pinctrl-0 = <
1742 interrupts =
1743 #address-cell
1744 #size-cells =
1745 interconnects
1746
1747
1748 interconnect-
1749
1750 power-domains
1751 required-opps
1752 dmas = <&gpi_
1753 <&gpi_
1754 dma-names = "
1755 status = "dis
1756 };
1757
1758 spi10: spi@a88000 {
1759 compatible =
1760 reg = <0 0x00
1761 clocks = <&gc
1762 clock-names =
1763 pinctrl-names
1764 pinctrl-0 = <
1765 interrupts =
1766 #address-cell
1767 #size-cells =
1768 power-domains
1769 operating-poi
1770 interconnects
1771
1772 interconnect-
1773 dmas = <&gpi_
1774 <&gpi_
1775 dma-names = "
1776 status = "dis
1777 };
1778
1779 uart10: serial@a88000
1780 compatible =
1781 reg = <0 0x00
1782 clocks = <&gc
1783 clock-names =
1784 pinctrl-names
1785 pinctrl-0 = <
1786 interrupts =
1787 power-domains
1788 operating-poi
1789 interconnects
1790
1791 interconnect-
1792 status = "dis
1793 };
1794
1795 i2c11: i2c@a8c000 {
1796 compatible =
1797 reg = <0 0x00
1798 clocks = <&gc
1799 clock-names =
1800 pinctrl-names
1801 pinctrl-0 = <
1802 interrupts =
1803 #address-cell
1804 #size-cells =
1805 interconnects
1806
1807
1808 interconnect-
1809
1810 power-domains
1811 required-opps
1812 dmas = <&gpi_
1813 <&gpi_
1814 dma-names = "
1815 status = "dis
1816 };
1817
1818 spi11: spi@a8c000 {
1819 compatible =
1820 reg = <0 0x00
1821 clocks = <&gc
1822 clock-names =
1823 pinctrl-names
1824 pinctrl-0 = <
1825 interrupts =
1826 #address-cell
1827 #size-cells =
1828 power-domains
1829 operating-poi
1830 interconnects
1831
1832 interconnect-
1833 dmas = <&gpi_
1834 <&gpi_
1835 dma-names = "
1836 status = "dis
1837 };
1838
1839 uart11: serial@a8c000
1840 compatible =
1841 reg = <0 0x00
1842 clocks = <&gc
1843 clock-names =
1844 pinctrl-names
1845 pinctrl-0 = <
1846 interrupts =
1847 power-domains
1848 operating-poi
1849 interconnects
1850
1851 interconnect-
1852 status = "dis
1853 };
1854
1855 i2c12: i2c@a90000 {
1856 compatible =
1857 reg = <0 0x00
1858 clocks = <&gc
1859 clock-names =
1860 pinctrl-names
1861 pinctrl-0 = <
1862 interrupts =
1863 #address-cell
1864 #size-cells =
1865 interconnects
1866
1867
1868 interconnect-
1869
1870 power-domains
1871 required-opps
1872 dmas = <&gpi_
1873 <&gpi_
1874 dma-names = "
1875 status = "dis
1876 };
1877
1878 spi12: spi@a90000 {
1879 compatible =
1880 reg = <0 0x00
1881 clocks = <&gc
1882 clock-names =
1883 pinctrl-names
1884 pinctrl-0 = <
1885 interrupts =
1886 #address-cell
1887 #size-cells =
1888 power-domains
1889 operating-poi
1890 interconnects
1891
1892 interconnect-
1893 dmas = <&gpi_
1894 <&gpi_
1895 dma-names = "
1896 status = "dis
1897 };
1898
1899 uart12: serial@a90000
1900 compatible =
1901 reg = <0 0x00
1902 clocks = <&gc
1903 clock-names =
1904 pinctrl-names
1905 pinctrl-0 = <
1906 interrupts =
1907 power-domains
1908 operating-poi
1909 interconnects
1910
1911 interconnect-
1912 status = "dis
1913 };
1914
1915 i2c13: i2c@a94000 {
1916 compatible =
1917 reg = <0 0x00
1918 clocks = <&gc
1919 clock-names =
1920 pinctrl-names
1921 pinctrl-0 = <
1922 interrupts =
1923 #address-cell
1924 #size-cells =
1925 interconnects
1926
1927
1928 interconnect-
1929
1930 power-domains
1931 required-opps
1932 dmas = <&gpi_
1933 <&gpi_
1934 dma-names = "
1935 status = "dis
1936 };
1937
1938 spi13: spi@a94000 {
1939 compatible =
1940 reg = <0 0x00
1941 clocks = <&gc
1942 clock-names =
1943 pinctrl-names
1944 pinctrl-0 = <
1945 interrupts =
1946 #address-cell
1947 #size-cells =
1948 power-domains
1949 operating-poi
1950 interconnects
1951
1952 interconnect-
1953 dmas = <&gpi_
1954 <&gpi_
1955 dma-names = "
1956 status = "dis
1957 };
1958
1959 uart13: serial@a94000
1960 compatible =
1961 reg = <0 0x00
1962 clocks = <&gc
1963 clock-names =
1964 pinctrl-names
1965 pinctrl-0 = <
1966 interrupts =
1967 power-domains
1968 operating-poi
1969 interconnects
1970
1971 interconnect-
1972 status = "dis
1973 };
1974
1975 i2c14: i2c@a98000 {
1976 compatible =
1977 reg = <0 0x00
1978 clocks = <&gc
1979 clock-names =
1980 pinctrl-names
1981 pinctrl-0 = <
1982 interrupts =
1983 #address-cell
1984 #size-cells =
1985 interconnects
1986
1987
1988 interconnect-
1989
1990 power-domains
1991 required-opps
1992 dmas = <&gpi_
1993 <&gpi_
1994 dma-names = "
1995 status = "dis
1996 };
1997
1998 spi14: spi@a98000 {
1999 compatible =
2000 reg = <0 0x00
2001 clocks = <&gc
2002 clock-names =
2003 pinctrl-names
2004 pinctrl-0 = <
2005 interrupts =
2006 #address-cell
2007 #size-cells =
2008 power-domains
2009 operating-poi
2010 interconnects
2011
2012 interconnect-
2013 dmas = <&gpi_
2014 <&gpi_
2015 dma-names = "
2016 status = "dis
2017 };
2018
2019 uart14: serial@a98000
2020 compatible =
2021 reg = <0 0x00
2022 clocks = <&gc
2023 clock-names =
2024 pinctrl-names
2025 pinctrl-0 = <
2026 interrupts =
2027 power-domains
2028 operating-poi
2029 interconnects
2030
2031 interconnect-
2032 status = "dis
2033 };
2034
2035 i2c15: i2c@a9c000 {
2036 compatible =
2037 reg = <0 0x00
2038 clocks = <&gc
2039 clock-names =
2040 pinctrl-names
2041 pinctrl-0 = <
2042 interrupts =
2043 #address-cell
2044 #size-cells =
2045 interconnects
2046
2047
2048 interconnect-
2049
2050 power-domains
2051 required-opps
2052 dmas = <&gpi_
2053 <&gpi_
2054 dma-names = "
2055 status = "dis
2056 };
2057
2058 spi15: spi@a9c000 {
2059 compatible =
2060 reg = <0 0x00
2061 clocks = <&gc
2062 clock-names =
2063 pinctrl-names
2064 pinctrl-0 = <
2065 interrupts =
2066 #address-cell
2067 #size-cells =
2068 power-domains
2069 operating-poi
2070 interconnects
2071
2072 interconnect-
2073 dmas = <&gpi_
2074 <&gpi_
2075 dma-names = "
2076 status = "dis
2077 };
2078
2079 uart15: serial@a9c000
2080 compatible =
2081 reg = <0 0x00
2082 clocks = <&gc
2083 clock-names =
2084 pinctrl-names
2085 pinctrl-0 = <
2086 interrupts =
2087 power-domains
2088 operating-poi
2089 interconnects
2090
2091 interconnect-
2092 status = "dis
2093 };
2094 };
2095
2096 rng: rng@10d3000 {
2097 compatible = "qcom,sc
2098 reg = <0 0x010d3000 0
2099 };
2100
2101 cnoc2: interconnect@1500000 {
2102 reg = <0 0x01500000 0
2103 compatible = "qcom,sc
2104 #interconnect-cells =
2105 qcom,bcm-voters = <&a
2106 };
2107
2108 cnoc3: interconnect@1502000 {
2109 reg = <0 0x01502000 0
2110 compatible = "qcom,sc
2111 #interconnect-cells =
2112 qcom,bcm-voters = <&a
2113 };
2114
2115 mc_virt: interconnect@1580000
2116 reg = <0 0x01580000 0
2117 compatible = "qcom,sc
2118 #interconnect-cells =
2119 qcom,bcm-voters = <&a
2120 };
2121
2122 system_noc: interconnect@1680
2123 reg = <0 0x01680000 0
2124 compatible = "qcom,sc
2125 #interconnect-cells =
2126 qcom,bcm-voters = <&a
2127 };
2128
2129 aggre1_noc: interconnect@16e0
2130 compatible = "qcom,sc
2131 reg = <0 0x016e0000 0
2132 #interconnect-cells =
2133 qcom,bcm-voters = <&a
2134 clocks = <&gcc GCC_AG
2135 <&gcc GCC_AG
2136 };
2137
2138 aggre2_noc: interconnect@1700
2139 reg = <0 0x01700000 0
2140 compatible = "qcom,sc
2141 #interconnect-cells =
2142 qcom,bcm-voters = <&a
2143 clocks = <&rpmhcc RPM
2144 };
2145
2146 mmss_noc: interconnect@174000
2147 reg = <0 0x01740000 0
2148 compatible = "qcom,sc
2149 #interconnect-cells =
2150 qcom,bcm-voters = <&a
2151 };
2152
2153 wifi: wifi@17a10040 {
2154 compatible = "qcom,wc
2155 reg = <0 0x17a10040 0
2156 iommus = <&apps_smmu
2157 interrupts = <GIC_SPI
2158 <GIC_SPI
2159 <GIC_SPI
2160 <GIC_SPI
2161 <GIC_SPI
2162 <GIC_SPI
2163 <GIC_SPI
2164 <GIC_SPI
2165 <GIC_SPI
2166 <GIC_SPI
2167 <GIC_SPI
2168 <GIC_SPI
2169 <GIC_SPI
2170 <GIC_SPI
2171 <GIC_SPI
2172 <GIC_SPI
2173 <GIC_SPI
2174 <GIC_SPI
2175 <GIC_SPI
2176 <GIC_SPI
2177 <GIC_SPI
2178 <GIC_SPI
2179 <GIC_SPI
2180 <GIC_SPI
2181 <GIC_SPI
2182 <GIC_SPI
2183 <GIC_SPI
2184 <GIC_SPI
2185 <GIC_SPI
2186 <GIC_SPI
2187 <GIC_SPI
2188 <GIC_SPI
2189 qcom,rproc = <&remote
2190 memory-region = <&wla
2191 status = "disabled";
2192 qcom,smem-states = <&
2193 qcom,smem-state-names
2194 };
2195
2196 pcie1: pcie@1c08000 {
2197 compatible = "qcom,pc
2198 reg = <0 0x01c08000 0
2199 <0 0x40000000 0
2200 <0 0x40000f20 0
2201 <0 0x40001000 0
2202 <0 0x40100000 0
2203
2204 reg-names = "parf", "
2205 device_type = "pci";
2206 linux,pci-domain = <1
2207 bus-range = <0x00 0xf
2208 num-lanes = <2>;
2209
2210 #address-cells = <3>;
2211 #size-cells = <2>;
2212
2213 ranges = <0x01000000
2214 <0x02000000
2215
2216 interrupts = <GIC_SPI
2217 <GIC_SPI
2218 <GIC_SPI
2219 <GIC_SPI
2220 <GIC_SPI
2221 <GIC_SPI
2222 <GIC_SPI
2223 <GIC_SPI
2224 interrupt-names = "ms
2225 "ms
2226 #interrupt-cells = <1
2227 interrupt-map-mask =
2228 interrupt-map = <0 0
2229 <0 0
2230 <0 0
2231 <0 0
2232
2233 clocks = <&gcc GCC_PC
2234 <&gcc GCC_PC
2235 <&pcie1_phy>
2236 <&rpmhcc RPM
2237 <&gcc GCC_PC
2238 <&gcc GCC_PC
2239 <&gcc GCC_PC
2240 <&gcc GCC_PC
2241 <&gcc GCC_PC
2242 <&gcc GCC_AG
2243 <&gcc GCC_DD
2244 <&gcc GCC_AG
2245 <&gcc GCC_AG
2246
2247 clock-names = "pipe",
2248 "pipe_m
2249 "phy_pi
2250 "ref",
2251 "aux",
2252 "cfg",
2253 "bus_ma
2254 "bus_sl
2255 "slave_
2256 "tbu",
2257 "ddrss_
2258 "aggre0
2259 "aggre1
2260
2261 assigned-clocks = <&g
2262 assigned-clock-rates
2263
2264 resets = <&gcc GCC_PC
2265 reset-names = "pci";
2266
2267 power-domains = <&gcc
2268
2269 phys = <&pcie1_phy>;
2270 phy-names = "pciephy"
2271
2272 pinctrl-names = "defa
2273 pinctrl-0 = <&pcie1_c
2274
2275 dma-coherent;
2276
2277 iommu-map = <0x0 &app
2278 <0x100 &a
2279
2280 status = "disabled";
2281
2282 pcie@0 {
2283 device_type =
2284 reg = <0x0 0x
2285 bus-range = <
2286
2287 #address-cell
2288 #size-cells =
2289 ranges;
2290 };
2291 };
2292
2293 pcie1_phy: phy@1c0e000 {
2294 compatible = "qcom,sm
2295 reg = <0 0x01c0e000 0
2296 clocks = <&gcc GCC_PC
2297 <&gcc GCC_PC
2298 <&gcc GCC_PC
2299 <&gcc GCC_PC
2300 <&gcc GCC_PC
2301 clock-names = "aux",
2302 "cfg_ah
2303 "ref",
2304 "refgen
2305 "pipe";
2306
2307 clock-output-names =
2308 #clock-cells = <0>;
2309
2310 #phy-cells = <0>;
2311
2312 resets = <&gcc GCC_PC
2313 reset-names = "phy";
2314
2315 assigned-clocks = <&g
2316 assigned-clock-rates
2317
2318 status = "disabled";
2319 };
2320
2321 ufs_mem_hc: ufs@1d84000 {
2322 compatible = "qcom,sc
2323 "jedec,u
2324 reg = <0x0 0x01d84000
2325 interrupts = <GIC_SPI
2326 phys = <&ufs_mem_phy>
2327 phy-names = "ufsphy";
2328 lanes-per-direction =
2329 #reset-cells = <1>;
2330 resets = <&gcc GCC_UF
2331 reset-names = "rst";
2332
2333 power-domains = <&gcc
2334 required-opps = <&rpm
2335
2336 iommus = <&apps_smmu
2337 dma-coherent;
2338
2339 interconnects = <&agg
2340 &mc_
2341 <&gem
2342 &cno
2343 interconnect-names =
2344
2345 clocks = <&gcc GCC_UF
2346 <&gcc GCC_AG
2347 <&gcc GCC_UF
2348 <&gcc GCC_UF
2349 <&rpmhcc RPM
2350 <&gcc GCC_UF
2351 <&gcc GCC_UF
2352 <&gcc GCC_UF
2353 clock-names = "core_c
2354 "bus_ag
2355 "iface_
2356 "core_c
2357 "ref_cl
2358 "tx_lan
2359 "rx_lan
2360 "rx_lan
2361 freq-table-hz =
2362 <75000000 300
2363 <0 0>,
2364 <0 0>,
2365 <75000000 300
2366 <0 0>,
2367 <0 0>,
2368 <0 0>,
2369 <0 0>;
2370 qcom,ice = <&ice>;
2371
2372 status = "disabled";
2373 };
2374
2375 ufs_mem_phy: phy@1d87000 {
2376 compatible = "qcom,sc
2377 reg = <0x0 0x01d87000
2378 clocks = <&rpmhcc RPM
2379 <&gcc GCC_UF
2380 <&gcc GCC_UF
2381 clock-names = "ref",
2382
2383 power-domains = <&rpm
2384
2385 resets = <&ufs_mem_hc
2386 reset-names = "ufsphy
2387
2388 #clock-cells = <1>;
2389 #phy-cells = <0>;
2390
2391 status = "disabled";
2392 };
2393
2394 ice: crypto@1d88000 {
2395 compatible = "qcom,sc
2396 "qcom,in
2397 reg = <0 0x01d88000 0
2398 clocks = <&gcc GCC_UF
2399 };
2400
2401 cryptobam: dma-controller@1dc
2402 compatible = "qcom,ba
2403 reg = <0x0 0x01dc4000
2404 interrupts = <GIC_SPI
2405 #dma-cells = <1>;
2406 iommus = <&apps_smmu
2407 <&apps_smmu
2408 qcom,ee = <0>;
2409 qcom,controlled-remot
2410 num-channels = <16>;
2411 qcom,num-ees = <4>;
2412 };
2413
2414 crypto: crypto@1dfa000 {
2415 compatible = "qcom,sc
2416 reg = <0x0 0x01dfa000
2417 dmas = <&cryptobam 4>
2418 dma-names = "rx", "tx
2419 iommus = <&apps_smmu
2420 <&apps_smmu
2421 interconnects = <&agg
2422 interconnect-names =
2423 };
2424
2425 ipa: ipa@1e40000 {
2426 compatible = "qcom,sc
2427
2428 iommus = <&apps_smmu
2429 <&apps_smmu
2430 reg = <0 0x01e40000 0
2431 <0 0x01e50000 0
2432 <0 0x01e04000 0
2433 reg-names = "ipa-reg"
2434 "ipa-shar
2435 "gsi";
2436
2437 interrupts-extended =
2438
2439
2440
2441 interrupt-names = "ip
2442 "gs
2443 "ip
2444 "ip
2445
2446 clocks = <&rpmhcc RPM
2447 clock-names = "core";
2448
2449 interconnects = <&agg
2450 <&gem
2451 interconnect-names =
2452
2453
2454 qcom,qmp = <&aoss_qmp
2455
2456 qcom,smem-states = <&
2457 <&
2458 qcom,smem-state-names
2459
2460
2461 status = "disabled";
2462 };
2463
2464 tcsr_mutex: hwlock@1f40000 {
2465 compatible = "qcom,tc
2466 reg = <0 0x01f40000 0
2467 #hwlock-cells = <1>;
2468 };
2469
2470 tcsr_1: syscon@1f60000 {
2471 compatible = "qcom,sc
2472 reg = <0 0x01f60000 0
2473 };
2474
2475 tcsr_2: syscon@1fc0000 {
2476 compatible = "qcom,sc
2477 reg = <0 0x01fc0000 0
2478 };
2479
2480 lpasscc: lpasscc@3000000 {
2481 compatible = "qcom,sc
2482 reg = <0 0x03000000 0
2483 <0 0x03c04000 0
2484 reg-names = "qdsp6ss"
2485 clocks = <&gcc GCC_CF
2486 clock-names = "iface"
2487 #clock-cells = <1>;
2488 status = "reserved";
2489 };
2490
2491 lpass_rx_macro: codec@3200000
2492 compatible = "qcom,sc
2493 reg = <0 0x03200000 0
2494
2495 pinctrl-names = "defa
2496 pinctrl-0 = <&lpass_r
2497
2498 clocks = <&lpass_aon
2499 <&lpass_aon
2500 <&lpass_va_m
2501 clock-names = "mclk",
2502
2503 power-domains = <&lpa
2504 <&lpa
2505 power-domain-names =
2506
2507 #clock-cells = <0>;
2508 #sound-dai-cells = <1
2509
2510 status = "disabled";
2511 };
2512
2513 swr0: soundwire@3210000 {
2514 compatible = "qcom,so
2515 reg = <0 0x03210000 0
2516
2517 interrupts = <GIC_SPI
2518 clocks = <&lpass_rx_m
2519 clock-names = "iface"
2520
2521 qcom,din-ports = <0>;
2522 qcom,dout-ports = <5>
2523
2524 resets = <&lpass_audi
2525 reset-names = "swr_au
2526
2527 qcom,ports-word-lengt
2528 qcom,ports-sinterval-
2529 qcom,ports-offset1 =
2530 qcom,ports-offset2 =
2531 qcom,ports-lane-contr
2532 qcom,ports-block-pack
2533 qcom,ports-hstart =
2534 qcom,ports-hstop =
2535 qcom,ports-block-grou
2536
2537 #sound-dai-cells = <1
2538 #address-cells = <2>;
2539 #size-cells = <0>;
2540
2541 status = "disabled";
2542 };
2543
2544 lpass_tx_macro: codec@3220000
2545 compatible = "qcom,sc
2546 reg = <0 0x03220000 0
2547
2548 pinctrl-names = "defa
2549 pinctrl-0 = <&lpass_t
2550
2551 clocks = <&lpass_aon
2552 <&lpass_aon
2553 <&lpass_va_m
2554 clock-names = "mclk",
2555
2556 power-domains = <&lpa
2557 <&lpa
2558 power-domain-names =
2559
2560 #clock-cells = <0>;
2561 #sound-dai-cells = <1
2562
2563 status = "disabled";
2564 };
2565
2566 swr1: soundwire@3230000 {
2567 compatible = "qcom,so
2568 reg = <0 0x03230000 0
2569
2570 interrupts-extended =
2571
2572 clocks = <&lpass_tx_m
2573 clock-names = "iface"
2574
2575 qcom,din-ports = <3>;
2576 qcom,dout-ports = <0>
2577
2578 resets = <&lpass_audi
2579 reset-names = "swr_au
2580
2581 qcom,ports-sinterval-
2582 qcom,ports-offset1 =
2583 qcom,ports-offset2 =
2584 qcom,ports-hstart =
2585 qcom,ports-hstop =
2586 qcom,ports-word-lengt
2587 qcom,ports-block-pack
2588 qcom,ports-block-grou
2589 qcom,ports-lane-contr
2590
2591 #sound-dai-cells = <1
2592 #address-cells = <2>;
2593 #size-cells = <0>;
2594
2595 status = "disabled";
2596 };
2597
2598 lpass_audiocc: clock-controll
2599 compatible = "qcom,sc
2600 reg = <0 0x03300000 0
2601 <0 0x032a9000 0
2602 clocks = <&rpmhcc RPM
2603 <&lpass_aon LP
2604 clock-names = "bi_tcx
2605 power-domains = <&lpa
2606 #clock-cells = <1>;
2607 #power-domain-cells =
2608 #reset-cells = <1>;
2609 };
2610
2611 lpass_va_macro: codec@3370000
2612 compatible = "qcom,sc
2613 reg = <0 0x03370000 0
2614
2615 pinctrl-names = "defa
2616 pinctrl-0 = <&lpass_d
2617
2618 clocks = <&lpass_aon
2619 clock-names = "mclk";
2620
2621 power-domains = <&lpa
2622 <&lpa
2623 power-domain-names =
2624
2625 #clock-cells = <0>;
2626 #sound-dai-cells = <1
2627
2628 status = "disabled";
2629 };
2630
2631 lpass_aon: clock-controller@3
2632 compatible = "qcom,sc
2633 reg = <0 0x03380000 0
2634 clocks = <&rpmhcc RPM
2635 <&rpmhcc RPMH_
2636 <&lpass_core L
2637 clock-names = "bi_tcx
2638 #clock-cells = <1>;
2639 #power-domain-cells =
2640 status = "reserved";
2641 };
2642
2643 lpass_core: clock-controller@
2644 compatible = "qcom,sc
2645 reg = <0 0x03900000 0
2646 clocks = <&rpmhcc RPM
2647 clock-names = "bi_tcx
2648 power-domains = <&lpa
2649 #clock-cells = <1>;
2650 #power-domain-cells =
2651 status = "reserved";
2652 };
2653
2654 lpass_cpu: audio@3987000 {
2655 compatible = "qcom,sc
2656
2657 reg = <0 0x03987000 0
2658 <0 0x03b00000 0
2659 <0 0x03260000 0
2660 <0 0x03280000 0
2661 <0 0x03340000 0
2662 <0 0x0336c000 0
2663 reg-names = "lpass-hd
2664 "lpass-lp
2665 "lpass-rx
2666 "lpass-rx
2667 "lpass-va
2668 "lpass-va
2669
2670 iommus = <&apps_smmu
2671 <&apps_smmu
2672 <&apps_smmu
2673
2674 power-domains = <&rpm
2675 power-domain-names =
2676 required-opps = <&rpm
2677
2678 clocks = <&lpass_aon
2679 <&lpass_core
2680 <&lpass_core
2681 <&lpass_core
2682 <&lpass_core
2683 <&lpass_audi
2684 <&lpass_audi
2685 <&lpass_audi
2686 <&lpass_audi
2687 <&lpass_aon
2688 clock-names = "aon_cc
2689 "audio_
2690 "core_c
2691 "core_c
2692 "core_c
2693 "audio_
2694 "audio_
2695 "audio_
2696 "audio_
2697 "aon_cc
2698
2699 #sound-dai-cells = <1
2700 #address-cells = <1>;
2701 #size-cells = <0>;
2702
2703 interrupts = <GIC_SPI
2704 <GIC_SPI
2705 <GIC_SPI
2706 <GIC_SPI
2707 interrupt-names = "lp
2708 "lp
2709 "lp
2710 "lp
2711
2712 status = "disabled";
2713 };
2714
2715 slimbam: dma-controller@3a840
2716 compatible = "qcom,ba
2717 reg = <0 0x03a84000 0
2718 interrupts = <GIC_SPI
2719 #dma-cells = <1>;
2720 qcom,controlled-remot
2721 num-channels = <31>;
2722 qcom,ee = <1>;
2723 qcom,num-ees = <2>;
2724 iommus = <&apps_smmu
2725 status = "disabled";
2726 };
2727
2728 slim: slim-ngd@3ac0000 {
2729 compatible = "qcom,sl
2730 reg = <0 0x03ac0000 0
2731 interrupts = <GIC_SPI
2732 dmas = <&slimbam 3>,
2733 dma-names = "rx", "tx
2734 iommus = <&apps_smmu
2735 #address-cells = <1>;
2736 #size-cells = <0>;
2737 status = "disabled";
2738 };
2739
2740 lpass_hm: clock-controller@3c
2741 compatible = "qcom,sc
2742 reg = <0 0x03c00000 0
2743 clocks = <&rpmhcc RPM
2744 clock-names = "bi_tcx
2745 #clock-cells = <1>;
2746 #power-domain-cells =
2747 status = "reserved";
2748 };
2749
2750 lpass_ag_noc: interconnect@3c
2751 reg = <0 0x03c40000 0
2752 compatible = "qcom,sc
2753 #interconnect-cells =
2754 qcom,bcm-voters = <&a
2755 };
2756
2757 lpass_tlmm: pinctrl@33c0000 {
2758 compatible = "qcom,sc
2759 reg = <0 0x033c0000 0
2760 <0 0x03550000
2761 gpio-controller;
2762 #gpio-cells = <2>;
2763 gpio-ranges = <&lpass
2764
2765 lpass_dmic01_clk: dmi
2766 pins = "gpio6
2767 function = "d
2768 };
2769
2770 lpass_dmic01_data: dm
2771 pins = "gpio7
2772 function = "d
2773 };
2774
2775 lpass_dmic23_clk: dmi
2776 pins = "gpio8
2777 function = "d
2778 };
2779
2780 lpass_dmic23_data: dm
2781 pins = "gpio9
2782 function = "d
2783 };
2784
2785 lpass_rx_swr_clk: rx-
2786 pins = "gpio3
2787 function = "s
2788 };
2789
2790 lpass_rx_swr_data: rx
2791 pins = "gpio4
2792 function = "s
2793 };
2794
2795 lpass_tx_swr_clk: tx-
2796 pins = "gpio0
2797 function = "s
2798 };
2799
2800 lpass_tx_swr_data: tx
2801 pins = "gpio1
2802 function = "s
2803 };
2804 };
2805
2806 gpu: gpu@3d00000 {
2807 compatible = "qcom,ad
2808 reg = <0 0x03d00000 0
2809 <0 0x03d9e000 0
2810 <0 0x03d61000 0
2811 reg-names = "kgsl_3d0
2812 "cx_mem",
2813 "cx_dbgc"
2814 interrupts = <GIC_SPI
2815 iommus = <&adreno_smm
2816 <&adreno_smm
2817 operating-points-v2 =
2818 qcom,gmu = <&gmu>;
2819 interconnects = <&gem
2820 interconnect-names =
2821 #cooling-cells = <2>;
2822
2823 nvmem-cells = <&gpu_s
2824 nvmem-cell-names = "s
2825
2826 gpu_zap_shader: zap-s
2827 memory-region
2828 };
2829
2830 gpu_opp_table: opp-ta
2831 compatible =
2832
2833 opp-315000000
2834 opp-h
2835 opp-l
2836 opp-p
2837 opp-s
2838 };
2839
2840 opp-450000000
2841 opp-h
2842 opp-l
2843 opp-p
2844 opp-s
2845 };
2846
2847 /* Only appli
2848 opp-550000000
2849 opp-h
2850 opp-l
2851 opp-p
2852 opp-s
2853 };
2854
2855 opp-550000000
2856 opp-h
2857 opp-l
2858 opp-p
2859 opp-s
2860 };
2861
2862 opp-608000000
2863 opp-h
2864 opp-l
2865 opp-p
2866 opp-s
2867 };
2868
2869 opp-700000000
2870 opp-h
2871 opp-l
2872 opp-p
2873 opp-s
2874 };
2875
2876 opp-812000000
2877 opp-h
2878 opp-l
2879 opp-p
2880 opp-s
2881 };
2882
2883 opp-840000000
2884 opp-h
2885 opp-l
2886 opp-p
2887 opp-s
2888 };
2889
2890 opp-900000000
2891 opp-h
2892 opp-l
2893 opp-p
2894 opp-s
2895 };
2896 };
2897 };
2898
2899 gmu: gmu@3d6a000 {
2900 compatible = "qcom,ad
2901 reg = <0 0x03d6a000 0
2902 <0 0x3de0000
2903 <0 0x0b290000
2904 reg-names = "gmu", "r
2905 interrupts = <GIC_SPI
2906 <GIC_
2907 interrupt-names = "hf
2908 clocks = <&gpucc GPU_
2909 <&gpucc GPU_
2910 <&gcc GCC_DD
2911 <&gcc GCC_GP
2912 <&gpucc GPU_
2913 <&gpucc GPU_
2914 <&gpucc GPU_
2915 clock-names = "gmu",
2916 "cxo",
2917 "axi",
2918 "memnoc
2919 "ahb",
2920 "hub",
2921 "smmu_v
2922 power-domains = <&gpu
2923 <&gpu
2924 power-domain-names =
2925
2926 iommus = <&adreno_smm
2927 operating-points-v2 =
2928
2929 gmu_opp_table: opp-ta
2930 compatible =
2931
2932 opp-200000000
2933 opp-h
2934 opp-l
2935 };
2936 };
2937 };
2938
2939 gpucc: clock-controller@3d900
2940 compatible = "qcom,sc
2941 reg = <0 0x03d90000 0
2942 clocks = <&rpmhcc RPM
2943 <&gcc GCC_GP
2944 <&gcc GCC_GP
2945 clock-names = "bi_tcx
2946 "gcc_gp
2947 "gcc_gp
2948 #clock-cells = <1>;
2949 #reset-cells = <1>;
2950 #power-domain-cells =
2951 };
2952
2953 dma@117f000 {
2954 compatible = "qcom,sc
2955 reg = <0x0 0x0117f000
2956 <0x0 0x01112000
2957 };
2958
2959 adreno_smmu: iommu@3da0000 {
2960 compatible = "qcom,sc
2961 "qcom,sm
2962 reg = <0 0x03da0000 0
2963 #iommu-cells = <2>;
2964 #global-interrupts =
2965 interrupts = <GIC_SPI
2966 <GIC_
2967 <GIC_
2968 <GIC_
2969 <GIC_
2970 <GIC_
2971 <GIC_
2972 <GIC_
2973 <GIC_
2974 <GIC_
2975 <GIC_
2976 <GIC_
2977
2978 clocks = <&gcc GCC_GP
2979 <&gcc GCC_GP
2980 <&gpucc GPU_
2981 <&gpucc GPU_
2982 <&gpucc GPU_
2983 <&gpucc GPU_
2984 <&gpucc GPU_
2985 clock-names = "gcc_gp
2986 "gcc_
2987 "gpu_
2988 "gpu_
2989 "gpu_
2990 "gpu_
2991 "gpu_
2992
2993 power-domains = <&gpu
2994 dma-coherent;
2995 };
2996
2997 gfx_0_tbu: tbu@3dd9000 {
2998 compatible = "qcom,sc
2999 reg = <0x0 0x3dd9000
3000 qcom,stream-id-range
3001 };
3002
3003 gfx_1_tbu: tbu@3ddd000 {
3004 compatible = "qcom,sc
3005 reg = <0x0 0x3ddd000
3006 qcom,stream-id-range
3007 };
3008
3009 remoteproc_mpss: remoteproc@4
3010 compatible = "qcom,sc
3011 reg = <0 0x04080000 0
3012
3013 interrupts-extended =
3014
3015
3016
3017
3018
3019 interrupt-names = "wd
3020 "st
3021
3022 clocks = <&rpmhcc RPM
3023 clock-names = "xo";
3024
3025 power-domains = <&rpm
3026 <&rpm
3027 power-domain-names =
3028
3029 memory-region = <&mps
3030
3031 qcom,qmp = <&aoss_qmp
3032
3033 qcom,smem-states = <&
3034 qcom,smem-state-names
3035
3036 status = "disabled";
3037
3038 glink-edge {
3039 interrupts-ex
3040
3041
3042 mboxes = <&ip
3043
3044 label = "mode
3045 qcom,remote-p
3046 };
3047 };
3048
3049 stm@6002000 {
3050 compatible = "arm,cor
3051 reg = <0 0x06002000 0
3052 <0 0x16280000 0
3053 reg-names = "stm-base
3054
3055 clocks = <&aoss_qmp>;
3056 clock-names = "apb_pc
3057
3058 out-ports {
3059 port {
3060 stm_o
3061
3062 };
3063 };
3064 };
3065 };
3066
3067 funnel@6041000 {
3068 compatible = "arm,cor
3069 reg = <0 0x06041000 0
3070
3071 clocks = <&aoss_qmp>;
3072 clock-names = "apb_pc
3073
3074 out-ports {
3075 port {
3076 funne
3077
3078 };
3079 };
3080 };
3081
3082 in-ports {
3083 #address-cell
3084 #size-cells =
3085
3086 port@7 {
3087 reg =
3088 funne
3089
3090 };
3091 };
3092 };
3093 };
3094
3095 funnel@6042000 {
3096 compatible = "arm,cor
3097 reg = <0 0x06042000 0
3098
3099 clocks = <&aoss_qmp>;
3100 clock-names = "apb_pc
3101
3102 out-ports {
3103 port {
3104 funne
3105
3106 };
3107 };
3108 };
3109
3110 in-ports {
3111 #address-cell
3112 #size-cells =
3113
3114 port@4 {
3115 reg =
3116 funne
3117
3118 };
3119 };
3120 };
3121 };
3122
3123 funnel@6045000 {
3124 compatible = "arm,cor
3125 reg = <0 0x06045000 0
3126
3127 clocks = <&aoss_qmp>;
3128 clock-names = "apb_pc
3129
3130 out-ports {
3131 port {
3132 merge
3133
3134 };
3135 };
3136 };
3137
3138 in-ports {
3139 #address-cell
3140 #size-cells =
3141
3142 port@0 {
3143 reg =
3144 merge
3145
3146 };
3147 };
3148
3149 port@1 {
3150 reg =
3151 merge
3152
3153 };
3154 };
3155 };
3156 };
3157
3158 replicator@6046000 {
3159 compatible = "arm,cor
3160 reg = <0 0x06046000 0
3161
3162 clocks = <&aoss_qmp>;
3163 clock-names = "apb_pc
3164
3165 out-ports {
3166 port {
3167 repli
3168
3169 };
3170 };
3171 };
3172
3173 in-ports {
3174 port {
3175 repli
3176
3177 };
3178 };
3179 };
3180 };
3181
3182 etr@6048000 {
3183 compatible = "arm,cor
3184 reg = <0 0x06048000 0
3185 iommus = <&apps_smmu
3186
3187 clocks = <&aoss_qmp>;
3188 clock-names = "apb_pc
3189 arm,scatter-gather;
3190
3191 in-ports {
3192 port {
3193 etr_i
3194
3195 };
3196 };
3197 };
3198 };
3199
3200 funnel@6b04000 {
3201 compatible = "arm,cor
3202 reg = <0 0x06b04000 0
3203
3204 clocks = <&aoss_qmp>;
3205 clock-names = "apb_pc
3206
3207 out-ports {
3208 port {
3209 swao_
3210
3211 };
3212 };
3213 };
3214
3215 in-ports {
3216 #address-cell
3217 #size-cells =
3218
3219 port@7 {
3220 reg =
3221 swao_
3222
3223 };
3224 };
3225 };
3226 };
3227
3228 etf@6b05000 {
3229 compatible = "arm,cor
3230 reg = <0 0x06b05000 0
3231
3232 clocks = <&aoss_qmp>;
3233 clock-names = "apb_pc
3234
3235 out-ports {
3236 port {
3237 etf_o
3238
3239 };
3240 };
3241 };
3242
3243 in-ports {
3244 port {
3245 etf_i
3246
3247 };
3248 };
3249 };
3250 };
3251
3252 replicator@6b06000 {
3253 compatible = "arm,cor
3254 reg = <0 0x06b06000 0
3255
3256 clocks = <&aoss_qmp>;
3257 clock-names = "apb_pc
3258 qcom,replicator-loses
3259
3260 out-ports {
3261 port {
3262 swao_
3263
3264 };
3265 };
3266 };
3267
3268 in-ports {
3269 port {
3270 swao_
3271
3272 };
3273 };
3274 };
3275 };
3276
3277 etm@7040000 {
3278 compatible = "arm,cor
3279 reg = <0 0x07040000 0
3280
3281 cpu = <&CPU0>;
3282
3283 clocks = <&aoss_qmp>;
3284 clock-names = "apb_pc
3285 arm,coresight-loses-c
3286 qcom,skip-power-up;
3287
3288 out-ports {
3289 port {
3290 etm0_
3291
3292 };
3293 };
3294 };
3295 };
3296
3297 etm@7140000 {
3298 compatible = "arm,cor
3299 reg = <0 0x07140000 0
3300
3301 cpu = <&CPU1>;
3302
3303 clocks = <&aoss_qmp>;
3304 clock-names = "apb_pc
3305 arm,coresight-loses-c
3306 qcom,skip-power-up;
3307
3308 out-ports {
3309 port {
3310 etm1_
3311
3312 };
3313 };
3314 };
3315 };
3316
3317 etm@7240000 {
3318 compatible = "arm,cor
3319 reg = <0 0x07240000 0
3320
3321 cpu = <&CPU2>;
3322
3323 clocks = <&aoss_qmp>;
3324 clock-names = "apb_pc
3325 arm,coresight-loses-c
3326 qcom,skip-power-up;
3327
3328 out-ports {
3329 port {
3330 etm2_
3331
3332 };
3333 };
3334 };
3335 };
3336
3337 etm@7340000 {
3338 compatible = "arm,cor
3339 reg = <0 0x07340000 0
3340
3341 cpu = <&CPU3>;
3342
3343 clocks = <&aoss_qmp>;
3344 clock-names = "apb_pc
3345 arm,coresight-loses-c
3346 qcom,skip-power-up;
3347
3348 out-ports {
3349 port {
3350 etm3_
3351
3352 };
3353 };
3354 };
3355 };
3356
3357 etm@7440000 {
3358 compatible = "arm,cor
3359 reg = <0 0x07440000 0
3360
3361 cpu = <&CPU4>;
3362
3363 clocks = <&aoss_qmp>;
3364 clock-names = "apb_pc
3365 arm,coresight-loses-c
3366 qcom,skip-power-up;
3367
3368 out-ports {
3369 port {
3370 etm4_
3371
3372 };
3373 };
3374 };
3375 };
3376
3377 etm@7540000 {
3378 compatible = "arm,cor
3379 reg = <0 0x07540000 0
3380
3381 cpu = <&CPU5>;
3382
3383 clocks = <&aoss_qmp>;
3384 clock-names = "apb_pc
3385 arm,coresight-loses-c
3386 qcom,skip-power-up;
3387
3388 out-ports {
3389 port {
3390 etm5_
3391
3392 };
3393 };
3394 };
3395 };
3396
3397 etm@7640000 {
3398 compatible = "arm,cor
3399 reg = <0 0x07640000 0
3400
3401 cpu = <&CPU6>;
3402
3403 clocks = <&aoss_qmp>;
3404 clock-names = "apb_pc
3405 arm,coresight-loses-c
3406 qcom,skip-power-up;
3407
3408 out-ports {
3409 port {
3410 etm6_
3411
3412 };
3413 };
3414 };
3415 };
3416
3417 etm@7740000 {
3418 compatible = "arm,cor
3419 reg = <0 0x07740000 0
3420
3421 cpu = <&CPU7>;
3422
3423 clocks = <&aoss_qmp>;
3424 clock-names = "apb_pc
3425 arm,coresight-loses-c
3426 qcom,skip-power-up;
3427
3428 out-ports {
3429 port {
3430 etm7_
3431
3432 };
3433 };
3434 };
3435 };
3436
3437 funnel@7800000 { /* APSS Funn
3438 compatible = "arm,cor
3439 reg = <0 0x07800000 0
3440
3441 clocks = <&aoss_qmp>;
3442 clock-names = "apb_pc
3443
3444 out-ports {
3445 port {
3446 apss_
3447
3448 };
3449 };
3450 };
3451
3452 in-ports {
3453 #address-cell
3454 #size-cells =
3455
3456 port@0 {
3457 reg =
3458 apss_
3459
3460 };
3461 };
3462
3463 port@1 {
3464 reg =
3465 apss_
3466
3467 };
3468 };
3469
3470 port@2 {
3471 reg =
3472 apss_
3473
3474 };
3475 };
3476
3477 port@3 {
3478 reg =
3479 apss_
3480
3481 };
3482 };
3483
3484 port@4 {
3485 reg =
3486 apss_
3487
3488 };
3489 };
3490
3491 port@5 {
3492 reg =
3493 apss_
3494
3495 };
3496 };
3497
3498 port@6 {
3499 reg =
3500 apss_
3501
3502 };
3503 };
3504
3505 port@7 {
3506 reg =
3507 apss_
3508
3509 };
3510 };
3511 };
3512 };
3513
3514 funnel@7810000 {
3515 compatible = "arm,cor
3516 reg = <0 0x07810000 0
3517
3518 clocks = <&aoss_qmp>;
3519 clock-names = "apb_pc
3520
3521 out-ports {
3522 port {
3523 apss_
3524
3525 };
3526 };
3527 };
3528
3529 in-ports {
3530 port {
3531 apss_
3532
3533 };
3534 };
3535 };
3536 };
3537
3538 sdhc_2: mmc@8804000 {
3539 compatible = "qcom,sc
3540 pinctrl-names = "defa
3541 pinctrl-0 = <&sdc2_cl
3542 pinctrl-1 = <&sdc2_cl
3543 status = "disabled";
3544
3545 reg = <0 0x08804000 0
3546
3547 iommus = <&apps_smmu
3548 interrupts = <GIC_SPI
3549 <GIC_SPI
3550 interrupt-names = "hc
3551
3552 clocks = <&gcc GCC_SD
3553 <&gcc GCC_SD
3554 <&rpmhcc RPM
3555 clock-names = "iface"
3556 interconnects = <&agg
3557 <&gem
3558 interconnect-names =
3559 power-domains = <&rpm
3560 operating-points-v2 =
3561
3562 bus-width = <4>;
3563 dma-coherent;
3564
3565 qcom,dll-config = <0x
3566
3567 resets = <&gcc GCC_SD
3568
3569 sdhc2_opp_table: opp-
3570 compatible =
3571
3572 opp-100000000
3573 opp-h
3574 requi
3575 opp-p
3576 opp-a
3577 };
3578
3579 opp-202000000
3580 opp-h
3581 requi
3582 opp-p
3583 opp-a
3584 };
3585 };
3586 };
3587
3588 usb_1_hsphy: phy@88e3000 {
3589 compatible = "qcom,sc
3590 "qcom,us
3591 reg = <0 0x088e3000 0
3592 status = "disabled";
3593 #phy-cells = <0>;
3594
3595 clocks = <&rpmhcc RPM
3596 clock-names = "ref";
3597
3598 resets = <&gcc GCC_QU
3599 };
3600
3601 usb_2_hsphy: phy@88e4000 {
3602 compatible = "qcom,sc
3603 "qcom,us
3604 reg = <0 0x088e4000 0
3605 status = "disabled";
3606 #phy-cells = <0>;
3607
3608 clocks = <&rpmhcc RPM
3609 clock-names = "ref";
3610
3611 resets = <&gcc GCC_QU
3612 };
3613
3614 usb_1_qmpphy: phy@88e8000 {
3615 compatible = "qcom,sc
3616 reg = <0 0x088e8000 0
3617 status = "disabled";
3618
3619 clocks = <&gcc GCC_US
3620 <&rpmhcc RPM
3621 <&gcc GCC_US
3622 <&gcc GCC_US
3623 clock-names = "aux",
3624 "ref",
3625 "com_au
3626 "usb3_p
3627
3628 resets = <&gcc GCC_US
3629 <&gcc GCC_US
3630 reset-names = "phy",
3631
3632 #clock-cells = <1>;
3633 #phy-cells = <1>;
3634
3635 ports {
3636 #address-cell
3637 #size-cells =
3638
3639 port@0 {
3640 reg =
3641
3642 usb_d
3643 };
3644 };
3645
3646 port@1 {
3647 reg =
3648
3649 usb_d
3650 };
3651 };
3652
3653 port@2 {
3654 reg =
3655
3656 usb_d
3657 };
3658 };
3659 };
3660 };
3661
3662 usb_2: usb@8cf8800 {
3663 compatible = "qcom,sc
3664 reg = <0 0x08cf8800 0
3665 status = "disabled";
3666 #address-cells = <2>;
3667 #size-cells = <2>;
3668 ranges;
3669 dma-ranges;
3670
3671 clocks = <&gcc GCC_CF
3672 <&gcc GCC_US
3673 <&gcc GCC_AG
3674 <&gcc GCC_US
3675 <&gcc GCC_US
3676 clock-names = "cfg_no
3677 "core",
3678 "iface"
3679 "sleep"
3680 "mock_u
3681
3682 assigned-clocks = <&g
3683 <&g
3684 assigned-clock-rates
3685
3686 interrupts-extended =
3687
3688
3689
3690 interrupt-names = "pw
3691 "hs
3692 "dp
3693 "dm
3694
3695 power-domains = <&gcc
3696 required-opps = <&rpm
3697
3698 resets = <&gcc GCC_US
3699
3700 interconnects = <&agg
3701 <&gem
3702 interconnect-names =
3703
3704 usb_2_dwc3: usb@8c000
3705 compatible =
3706 reg = <0 0x08
3707 interrupts =
3708 iommus = <&ap
3709 snps,dis_u2_s
3710 snps,dis_enbl
3711 phys = <&usb_
3712 phy-names = "
3713 maximum-speed
3714 usb-role-swit
3715
3716 port {
3717 usb2_
3718
3719 };
3720 };
3721 };
3722 };
3723
3724 qspi: spi@88dc000 {
3725 compatible = "qcom,sc
3726 reg = <0 0x088dc000 0
3727 iommus = <&apps_smmu
3728 #address-cells = <1>;
3729 #size-cells = <0>;
3730 interrupts = <GIC_SPI
3731 clocks = <&gcc GCC_QS
3732 <&gcc GCC_QS
3733 clock-names = "iface"
3734 interconnects = <&gem
3735 &cnoc
3736 interconnect-names =
3737 power-domains = <&rpm
3738 operating-points-v2 =
3739 status = "disabled";
3740 };
3741
3742 remoteproc_adsp: remoteproc@3
3743 compatible = "qcom,sc
3744 reg = <0 0x03700000 0
3745
3746 interrupts-extended =
3747
3748
3749
3750
3751
3752 interrupt-names = "wd
3753 "st
3754
3755 clocks = <&rpmhcc RPM
3756 clock-names = "xo";
3757
3758 power-domains = <&rpm
3759 <&rpm
3760 power-domain-names =
3761
3762 memory-region = <&ads
3763
3764 qcom,qmp = <&aoss_qmp
3765
3766 qcom,smem-states = <&
3767 qcom,smem-state-names
3768
3769 status = "disabled";
3770
3771 glink-edge {
3772 interrupts-ex
3773
3774
3775
3776 mboxes = <&ip
3777
3778
3779 label = "lpas
3780 qcom,remote-p
3781
3782 apr {
3783 compa
3784 qcom,
3785 qcom,
3786 #addr
3787 #size
3788
3789 servi
3790
3791
3792
3793 };
3794
3795 q6afe
3796
3797
3798
3799
3800
3801
3802
3803
3804
3805
3806
3807
3808
3809
3810
3811 };
3812
3813 q6asm
3814
3815
3816
3817
3818
3819
3820
3821
3822
3823
3824
3825
3826
3827
3828
3829
3830
3831
3832
3833
3834
3835
3836
3837 };
3838
3839 q6adm
3840
3841
3842
3843
3844
3845
3846
3847
3848 };
3849 };
3850
3851 fastrpc {
3852 compa
3853 qcom,
3854 label
3855 qcom,
3856 #addr
3857 #size
3858
3859 compu
3860
3861
3862
3863 };
3864
3865 compu
3866
3867
3868
3869 };
3870
3871 compu
3872
3873
3874
3875 };
3876 };
3877 };
3878 };
3879
3880 remoteproc_wpss: remoteproc@8
3881 compatible = "qcom,sc
3882 reg = <0 0x08a00000 0
3883
3884 interrupts-extended =
3885
3886
3887
3888
3889
3890 interrupt-names = "wd
3891 "st
3892
3893 clocks = <&rpmhcc RPM
3894 clock-names = "xo";
3895
3896 power-domains = <&rpm
3897 <&rpm
3898 power-domain-names =
3899
3900 memory-region = <&wps
3901
3902 qcom,qmp = <&aoss_qmp
3903
3904 qcom,smem-states = <&
3905 qcom,smem-state-names
3906
3907
3908 status = "disabled";
3909
3910 glink-edge {
3911 interrupts-ex
3912
3913
3914 mboxes = <&ip
3915
3916
3917 label = "wpss
3918 qcom,remote-p
3919 };
3920 };
3921
3922 pmu@9091000 {
3923 compatible = "qcom,sc
3924 reg = <0 0x09091000 0
3925
3926 interrupts = <GIC_SPI
3927
3928 interconnects = <&mc_
3929
3930 operating-points-v2 =
3931
3932 llcc_bwmon_opp_table:
3933 compatible =
3934
3935 opp-0 {
3936 opp-p
3937 };
3938 opp-1 {
3939 opp-p
3940 };
3941 opp-2 {
3942 opp-p
3943 };
3944 opp-3 {
3945 opp-p
3946 };
3947 opp-4 {
3948 opp-p
3949 };
3950 opp-5 {
3951 opp-p
3952 };
3953 opp-6 {
3954 opp-p
3955 };
3956 opp-7 {
3957 opp-p
3958 };
3959 };
3960 };
3961
3962 pmu@90b6400 {
3963 compatible = "qcom,sc
3964 reg = <0 0x090b6400 0
3965
3966 interrupts = <GIC_SPI
3967
3968 interconnects = <&gem
3969 operating-points-v2 =
3970
3971 cpu_bwmon_opp_table:
3972 compatible =
3973
3974 opp-0 {
3975 opp-p
3976 };
3977 opp-1 {
3978 opp-p
3979 };
3980 opp-2 {
3981 opp-p
3982 };
3983 opp-3 {
3984 opp-p
3985 };
3986 opp-4 {
3987 opp-p
3988 };
3989 opp-5 {
3990 opp-p
3991 };
3992 opp-6 {
3993 opp-p
3994 };
3995 };
3996 };
3997
3998 dc_noc: interconnect@90e0000
3999 reg = <0 0x090e0000 0
4000 compatible = "qcom,sc
4001 #interconnect-cells =
4002 qcom,bcm-voters = <&a
4003 };
4004
4005 gem_noc: interconnect@9100000
4006 reg = <0 0x09100000 0
4007 compatible = "qcom,sc
4008 #interconnect-cells =
4009 qcom,bcm-voters = <&a
4010 };
4011
4012 system-cache-controller@92000
4013 compatible = "qcom,sc
4014 reg = <0 0x09200000 0
4015 <0 0x09600000 0
4016 reg-names = "llcc0_ba
4017 interrupts = <GIC_SPI
4018 };
4019
4020 eud: eud@88e0000 {
4021 compatible = "qcom,sc
4022 reg = <0 0x88e0000 0
4023 <0 0x88e2000 0
4024 interrupts-extended =
4025
4026 status = "disabled";
4027
4028 ports {
4029 #address-cell
4030 #size-cells =
4031
4032 port@0 {
4033 reg =
4034 eud_e
4035
4036 };
4037 };
4038 };
4039 };
4040
4041 nsp_noc: interconnect@a0c0000
4042 reg = <0 0x0a0c0000 0
4043 compatible = "qcom,sc
4044 #interconnect-cells =
4045 qcom,bcm-voters = <&a
4046 };
4047
4048 remoteproc_cdsp: remoteproc@a
4049 compatible = "qcom,sc
4050 reg = <0 0x0a300000 0
4051
4052 interrupts-extended =
4053
4054
4055
4056
4057
4058 interrupt-names = "wd
4059 "st
4060
4061 clocks = <&rpmhcc RPM
4062 clock-names = "xo";
4063
4064 power-domains = <&rpm
4065 <&rpm
4066 power-domain-names =
4067
4068 interconnects = <&nsp
4069
4070 memory-region = <&cds
4071
4072 qcom,qmp = <&aoss_qmp
4073
4074 qcom,smem-states = <&
4075 qcom,smem-state-names
4076
4077 status = "disabled";
4078
4079 glink-edge {
4080 interrupts-ex
4081
4082
4083 mboxes = <&ip
4084
4085
4086 label = "cdsp
4087 qcom,remote-p
4088
4089 fastrpc {
4090 compa
4091 qcom,
4092 label
4093 qcom,
4094 #addr
4095 #size
4096
4097 compu
4098
4099
4100
4101
4102 };
4103
4104 compu
4105
4106
4107
4108
4109 };
4110
4111 compu
4112
4113
4114
4115
4116 };
4117
4118 compu
4119
4120
4121
4122
4123 };
4124
4125 compu
4126
4127
4128
4129
4130 };
4131
4132 compu
4133
4134
4135
4136
4137 };
4138
4139 compu
4140
4141
4142
4143
4144 };
4145
4146 compu
4147
4148
4149
4150
4151 };
4152
4153 /* no
4154
4155 compu
4156
4157
4158
4159
4160 };
4161
4162 compu
4163
4164
4165
4166
4167 };
4168
4169 compu
4170
4171
4172
4173
4174 };
4175
4176 compu
4177
4178
4179
4180
4181 };
4182 };
4183 };
4184 };
4185
4186 usb_1: usb@a6f8800 {
4187 compatible = "qcom,sc
4188 reg = <0 0x0a6f8800 0
4189 status = "disabled";
4190 #address-cells = <2>;
4191 #size-cells = <2>;
4192 ranges;
4193 dma-ranges;
4194
4195 clocks = <&gcc GCC_CF
4196 <&gcc GCC_US
4197 <&gcc GCC_AG
4198 <&gcc GCC_US
4199 <&gcc GCC_US
4200 clock-names = "cfg_no
4201 "core",
4202 "iface"
4203 "sleep"
4204 "mock_u
4205
4206 assigned-clocks = <&g
4207 <&g
4208 assigned-clock-rates
4209
4210 interrupts-extended =
4211
4212
4213
4214
4215 interrupt-names = "pw
4216 "hs
4217 "dp
4218 "dm
4219 "ss
4220
4221 power-domains = <&gcc
4222 required-opps = <&rpm
4223
4224 resets = <&gcc GCC_US
4225
4226 interconnects = <&agg
4227 <&gem
4228 interconnect-names =
4229
4230 wakeup-source;
4231
4232 usb_1_dwc3: usb@a6000
4233 compatible =
4234 reg = <0 0x0a
4235 interrupts =
4236 iommus = <&ap
4237 snps,dis_u2_s
4238 snps,dis_enbl
4239 snps,parkmode
4240 phys = <&usb_
4241 phy-names = "
4242 maximum-speed
4243
4244 ports {
4245 #addr
4246 #size
4247
4248 port@
4249
4250
4251
4252
4253 };
4254
4255 port@
4256
4257
4258
4259
4260 };
4261 };
4262 };
4263 };
4264
4265 venus: video-codec@aa00000 {
4266 compatible = "qcom,sc
4267 reg = <0 0x0aa00000 0
4268 interrupts = <GIC_SPI
4269
4270 clocks = <&videocc VI
4271 <&videocc VI
4272 <&videocc VI
4273 <&videocc VI
4274 <&videocc VI
4275 clock-names = "core",
4276 "vcodec
4277
4278 power-domains = <&vid
4279 <&vid
4280 <&rpm
4281 power-domain-names =
4282 operating-points-v2 =
4283
4284 interconnects = <&gem
4285 <&mms
4286 interconnect-names =
4287
4288 iommus = <&apps_smmu
4289 memory-region = <&vid
4290
4291 status = "disabled";
4292
4293 video-decoder {
4294 compatible =
4295 };
4296
4297 video-encoder {
4298 compatible =
4299 };
4300
4301 venus_opp_table: opp-
4302 compatible =
4303
4304 opp-133330000
4305 opp-h
4306 requi
4307 };
4308
4309 opp-240000000
4310 opp-h
4311 requi
4312 };
4313
4314 opp-335000000
4315 opp-h
4316 requi
4317 };
4318
4319 opp-424000000
4320 opp-h
4321 requi
4322 };
4323
4324 opp-460000048
4325 opp-h
4326 requi
4327 };
4328 };
4329 };
4330
4331 videocc: clock-controller@aaf
4332 compatible = "qcom,sc
4333 reg = <0 0x0aaf0000 0
4334 clocks = <&rpmhcc RPM
4335 <&rpmhcc RPMH
4336 clock-names = "bi_tcx
4337 #clock-cells = <1>;
4338 #reset-cells = <1>;
4339 #power-domain-cells =
4340 };
4341
4342 cci0: cci@ac4a000 {
4343 compatible = "qcom,sc
4344 reg = <0 0x0ac4a000 0
4345 interrupts = <GIC_SPI
4346 power-domains = <&cam
4347
4348 clocks = <&camcc CAM_
4349 <&camcc CAM_
4350 <&camcc CAM_
4351 <&camcc CAM_
4352 <&camcc CAM_
4353 clock-names = "camnoc
4354 "slow_a
4355 "cpas_a
4356 "cci",
4357 "cci_sr
4358 pinctrl-0 = <&cci0_de
4359 pinctrl-1 = <&cci0_sl
4360 pinctrl-names = "defa
4361
4362 #address-cells = <1>;
4363 #size-cells = <0>;
4364
4365 status = "disabled";
4366
4367 cci0_i2c0: i2c-bus@0
4368 reg = <0>;
4369 clock-frequen
4370 #address-cell
4371 #size-cells =
4372 };
4373
4374 cci0_i2c1: i2c-bus@1
4375 reg = <1>;
4376 clock-frequen
4377 #address-cell
4378 #size-cells =
4379 };
4380 };
4381
4382 cci1: cci@ac4b000 {
4383 compatible = "qcom,sc
4384 reg = <0 0x0ac4b000 0
4385 interrupts = <GIC_SPI
4386 power-domains = <&cam
4387
4388 clocks = <&camcc CAM_
4389 <&camcc CAM_
4390 <&camcc CAM_
4391 <&camcc CAM_
4392 <&camcc CAM_
4393 clock-names = "camnoc
4394 "slow_a
4395 "cpas_a
4396 "cci",
4397 "cci_sr
4398 pinctrl-0 = <&cci2_de
4399 pinctrl-1 = <&cci2_sl
4400 pinctrl-names = "defa
4401
4402 #address-cells = <1>;
4403 #size-cells = <0>;
4404
4405 status = "disabled";
4406
4407 cci1_i2c0: i2c-bus@0
4408 reg = <0>;
4409 clock-frequen
4410 #address-cell
4411 #size-cells =
4412 };
4413
4414 cci1_i2c1: i2c-bus@1
4415 reg = <1>;
4416 clock-frequen
4417 #address-cell
4418 #size-cells =
4419 };
4420 };
4421
4422 camcc: clock-controller@ad000
4423 compatible = "qcom,sc
4424 reg = <0 0x0ad00000 0
4425 clocks = <&rpmhcc RPM
4426 <&rpmhcc RPMH
4427 <&sleep_clk>;
4428 clock-names = "bi_tcx
4429 #clock-cells = <1>;
4430 #reset-cells = <1>;
4431 #power-domain-cells =
4432 };
4433
4434 dispcc: clock-controller@af00
4435 compatible = "qcom,sc
4436 reg = <0 0x0af00000 0
4437 clocks = <&rpmhcc RPM
4438 <&gcc GCC_DI
4439 <&mdss_dsi_p
4440 <&mdss_dsi_p
4441 <&usb_1_qmpp
4442 <&usb_1_qmpp
4443 <&mdss_edp_p
4444 <&mdss_edp_p
4445 clock-names = "bi_tcx
4446 "gcc_di
4447 "dsi0_p
4448 "dsi0_p
4449 "dp_phy
4450 "dp_phy
4451 "edp_ph
4452 "edp_ph
4453 #clock-cells = <1>;
4454 #reset-cells = <1>;
4455 #power-domain-cells =
4456 };
4457
4458 mdss: display-subsystem@ae000
4459 compatible = "qcom,sc
4460 reg = <0 0x0ae00000 0
4461 reg-names = "mdss";
4462
4463 power-domains = <&dis
4464
4465 clocks = <&gcc GCC_DI
4466 <&dispcc DIS
4467 <&dispcc DISP
4468 clock-names = "iface"
4469 "ahb",
4470 "core";
4471
4472 interrupts = <GIC_SPI
4473 interrupt-controller;
4474 #interrupt-cells = <1
4475
4476 interconnects = <&mms
4477 &mc_
4478 <&gem
4479 &cno
4480 interconnect-names =
4481
4482
4483 iommus = <&apps_smmu
4484
4485 #address-cells = <2>;
4486 #size-cells = <2>;
4487 ranges;
4488
4489 status = "disabled";
4490
4491 mdss_mdp: display-con
4492 compatible =
4493 reg = <0 0x0a
4494 <0 0x
4495 reg-names = "
4496
4497 clocks = <&gc
4498 <&gcc
4499 <&dis
4500 <&dis
4501 <&dis
4502 <&dis
4503 clock-names =
4504
4505
4506
4507
4508
4509 assigned-cloc
4510
4511 assigned-cloc
4512
4513 operating-poi
4514 power-domains
4515
4516 interrupt-par
4517 interrupts =
4518
4519 ports {
4520 #addr
4521 #size
4522
4523 port@
4524
4525
4526
4527
4528 };
4529
4530 port@
4531
4532
4533
4534
4535 };
4536
4537 port@
4538
4539
4540
4541
4542 };
4543 };
4544
4545 mdp_opp_table
4546 compa
4547
4548 opp-2
4549
4550
4551 };
4552
4553 opp-3
4554
4555
4556 };
4557
4558 opp-3
4559
4560
4561 };
4562
4563 opp-5
4564
4565
4566 };
4567
4568 opp-6
4569
4570
4571 };
4572 };
4573 };
4574
4575 mdss_dsi: dsi@ae94000
4576 compatible =
4577
4578 reg = <0 0x0a
4579 reg-names = "
4580
4581 interrupt-par
4582 interrupts =
4583
4584 clocks = <&di
4585 <&di
4586 <&di
4587 <&di
4588 <&di
4589 <&gc
4590 clock-names =
4591
4592
4593
4594
4595
4596
4597 assigned-cloc
4598 assigned-cloc
4599
4600 operating-poi
4601 power-domains
4602
4603 phys = <&mdss
4604
4605 #address-cell
4606 #size-cells =
4607
4608 status = "dis
4609
4610 ports {
4611 #addr
4612 #size
4613
4614 port@
4615
4616
4617
4618
4619 };
4620
4621 port@
4622
4623
4624
4625 };
4626 };
4627
4628 dsi_opp_table
4629 compa
4630
4631 opp-1
4632
4633
4634 };
4635
4636 opp-3
4637
4638
4639 };
4640
4641 opp-3
4642
4643
4644 };
4645 };
4646 };
4647
4648 mdss_dsi_phy: phy@ae9
4649 compatible =
4650 reg = <0 0x0a
4651 <0 0x0a
4652 <0 0x0a
4653 reg-names = "
4654 "
4655 "
4656
4657 #clock-cells
4658 #phy-cells =
4659
4660 clocks = <&di
4661 <&rp
4662 clock-names =
4663
4664 status = "dis
4665 };
4666
4667 mdss_edp: edp@aea0000
4668 compatible =
4669 pinctrl-names
4670 pinctrl-0 = <
4671
4672 reg = <0 0x0a
4673 <0 0x0a
4674 <0 0x0a
4675 <0 0x0a
4676
4677 interrupt-par
4678 interrupts =
4679
4680 clocks = <&di
4681 <&di
4682 <&di
4683 <&di
4684 <&di
4685 clock-names =
4686
4687
4688
4689
4690 assigned-cloc
4691
4692 assigned-cloc
4693
4694 phys = <&mdss
4695 phy-names = "
4696
4697 operating-poi
4698 power-domains
4699
4700 status = "dis
4701
4702 ports {
4703 #addr
4704 #size
4705
4706 port@
4707
4708
4709
4710
4711 };
4712
4713 port@
4714
4715
4716 };
4717 };
4718
4719 edp_opp_table
4720 compa
4721
4722 opp-1
4723
4724
4725 };
4726
4727 opp-2
4728
4729
4730 };
4731
4732 opp-5
4733
4734
4735 };
4736
4737 opp-8
4738
4739
4740 };
4741 };
4742 };
4743
4744 mdss_edp_phy: phy@aec
4745 compatible =
4746
4747 reg = <0 0x0a
4748 <0 0x0a
4749 <0 0x0a
4750 <0 0x0a
4751
4752 clocks = <&rp
4753 <&gc
4754 clock-names =
4755
4756
4757 #clock-cells
4758 #phy-cells =
4759
4760 status = "dis
4761 };
4762
4763 mdss_dp: displayport-
4764 compatible =
4765
4766 reg = <0 0x0a
4767 <0 0x0a
4768 <0 0x0a
4769 <0 0x0a
4770 <0 0x0a
4771
4772 interrupt-par
4773 interrupts =
4774
4775 clocks = <&di
4776 <&di
4777 <&di
4778 <&di
4779 <&di
4780 clock-names =
4781
4782
4783
4784
4785 assigned-cloc
4786
4787 assigned-cloc
4788
4789 phys = <&usb_
4790 phy-names = "
4791
4792 operating-poi
4793 power-domains
4794
4795 #sound-dai-ce
4796
4797 status = "dis
4798
4799 ports {
4800 #addr
4801 #size
4802
4803 port@
4804
4805
4806
4807
4808 };
4809
4810 port@
4811
4812
4813 };
4814 };
4815
4816 dp_opp_table:
4817 compa
4818
4819 opp-1
4820
4821
4822 };
4823
4824 opp-2
4825
4826
4827 };
4828
4829 opp-5
4830
4831
4832 };
4833
4834 opp-8
4835
4836
4837 };
4838 };
4839 };
4840 };
4841
4842 pdc: interrupt-controller@b22
4843 compatible = "qcom,sc
4844 reg = <0 0x0b220000 0
4845 qcom,pdc-ranges = <0
4846 <55
4847 <64
4848 <70
4849 <15
4850 #interrupt-cells = <2
4851 interrupt-parent = <&
4852 interrupt-controller;
4853 };
4854
4855 pdc_reset: reset-controller@b
4856 compatible = "qcom,sc
4857 reg = <0 0x0b5e0000 0
4858 #reset-cells = <1>;
4859 status = "reserved";
4860 };
4861
4862 tsens0: thermal-sensor@c26300
4863 compatible = "qcom,sc
4864 reg = <0 0x0c263000 0
4865 <0 0x0c222000
4866 #qcom,sensors = <15>;
4867 interrupts = <GIC_SPI
4868 <GIC_SPI
4869 interrupt-names = "up
4870 #thermal-sensor-cells
4871 };
4872
4873 tsens1: thermal-sensor@c26500
4874 compatible = "qcom,sc
4875 reg = <0 0x0c265000 0
4876 <0 0x0c223000
4877 #qcom,sensors = <12>;
4878 interrupts = <GIC_SPI
4879 <GIC_SPI
4880 interrupt-names = "up
4881 #thermal-sensor-cells
4882 };
4883
4884 aoss_reset: reset-controller@
4885 compatible = "qcom,sc
4886 reg = <0 0x0c2a0000 0
4887 #reset-cells = <1>;
4888 };
4889
4890 aoss_qmp: power-management@c3
4891 compatible = "qcom,sc
4892 reg = <0 0x0c300000 0
4893 interrupts-extended =
4894
4895
4896 mboxes = <&ipcc IPCC_
4897 IPCC_
4898
4899 #clock-cells = <0>;
4900 };
4901
4902 sram@c3f0000 {
4903 compatible = "qcom,rp
4904 reg = <0 0x0c3f0000 0
4905 };
4906
4907 spmi_bus: spmi@c440000 {
4908 compatible = "qcom,sp
4909 reg = <0 0x0c440000 0
4910 <0 0x0c600000 0
4911 <0 0x0e600000 0
4912 <0 0x0e700000 0
4913 <0 0x0c40a000 0
4914 reg-names = "core", "
4915 interrupt-names = "pe
4916 interrupts-extended =
4917 qcom,ee = <0>;
4918 qcom,channel = <0>;
4919 #address-cells = <2>;
4920 #size-cells = <0>;
4921 interrupt-controller;
4922 #interrupt-cells = <4
4923 };
4924
4925 tlmm: pinctrl@f100000 {
4926 compatible = "qcom,sc
4927 reg = <0 0x0f100000 0
4928 interrupts = <GIC_SPI
4929 gpio-controller;
4930 #gpio-cells = <2>;
4931 interrupt-controller;
4932 #interrupt-cells = <2
4933 gpio-ranges = <&tlmm
4934 wakeup-parent = <&pdc
4935
4936 cci0_default: cci0-de
4937 pins = "gpio6
4938 function = "c
4939 drive-strengt
4940 bias-pull-up;
4941 };
4942
4943 cci0_sleep: cci0-slee
4944 pins = "gpio6
4945 function = "c
4946 drive-strengt
4947 bias-pull-dow
4948 };
4949
4950 cci1_default: cci1-de
4951 pins = "gpio7
4952 function = "c
4953 drive-strengt
4954 bias-pull-up;
4955 };
4956
4957 cci1_sleep: cci1-slee
4958 pins = "gpio7
4959 function = "c
4960 drive-strengt
4961 bias-pull-dow
4962 };
4963
4964 cci2_default: cci2-de
4965 pins = "gpio7
4966 function = "c
4967 drive-strengt
4968 bias-pull-up;
4969 };
4970
4971 cci2_sleep: cci2-slee
4972 pins = "gpio7
4973 function = "c
4974 drive-strengt
4975 bias-pull-dow
4976 };
4977
4978 cci3_default: cci3-de
4979 pins = "gpio7
4980 function = "c
4981 drive-strengt
4982 bias-pull-up;
4983 };
4984
4985 cci3_sleep: cci3-slee
4986 pins = "gpio7
4987 function = "c
4988 drive-strengt
4989 bias-pull-dow
4990 };
4991
4992 dp_hot_plug_det: dp-h
4993 pins = "gpio4
4994 function = "d
4995 };
4996
4997 edp_hot_plug_det: edp
4998 pins = "gpio6
4999 function = "e
5000 };
5001
5002 mi2s0_data0: mi2s0-da
5003 pins = "gpio9
5004 function = "m
5005 };
5006
5007 mi2s0_data1: mi2s0-da
5008 pins = "gpio9
5009 function = "m
5010 };
5011
5012 mi2s0_mclk: mi2s0-mcl
5013 pins = "gpio9
5014 function = "p
5015 };
5016
5017 mi2s0_sclk: mi2s0-scl
5018 pins = "gpio9
5019 function = "m
5020 };
5021
5022 mi2s0_ws: mi2s0-ws-st
5023 pins = "gpio1
5024 function = "m
5025 };
5026
5027 mi2s1_data0: mi2s1-da
5028 pins = "gpio1
5029 function = "m
5030 };
5031
5032 mi2s1_sclk: mi2s1-scl
5033 pins = "gpio1
5034 function = "m
5035 };
5036
5037 mi2s1_ws: mi2s1-ws-st
5038 pins = "gpio1
5039 function = "m
5040 };
5041
5042 pcie1_clkreq_n: pcie1
5043 pins = "gpio7
5044 function = "p
5045 };
5046
5047 qspi_clk: qspi-clk-st
5048 pins = "gpio1
5049 function = "q
5050 };
5051
5052 qspi_cs0: qspi-cs0-st
5053 pins = "gpio1
5054 function = "q
5055 };
5056
5057 qspi_cs1: qspi-cs1-st
5058 pins = "gpio1
5059 function = "q
5060 };
5061
5062 qspi_data0: qspi-data
5063 pins = "gpio1
5064 function = "q
5065 };
5066
5067 qspi_data1: qspi-data
5068 pins = "gpio1
5069 function = "q
5070 };
5071
5072 qspi_data23: qspi-dat
5073 pins = "gpio1
5074 function = "q
5075 };
5076
5077 qup_i2c0_data_clk: qu
5078 pins = "gpio0
5079 function = "q
5080 };
5081
5082 qup_i2c1_data_clk: qu
5083 pins = "gpio4
5084 function = "q
5085 };
5086
5087 qup_i2c2_data_clk: qu
5088 pins = "gpio8
5089 function = "q
5090 };
5091
5092 qup_i2c3_data_clk: qu
5093 pins = "gpio1
5094 function = "q
5095 };
5096
5097 qup_i2c4_data_clk: qu
5098 pins = "gpio1
5099 function = "q
5100 };
5101
5102 qup_i2c5_data_clk: qu
5103 pins = "gpio2
5104 function = "q
5105 };
5106
5107 qup_i2c6_data_clk: qu
5108 pins = "gpio2
5109 function = "q
5110 };
5111
5112 qup_i2c7_data_clk: qu
5113 pins = "gpio2
5114 function = "q
5115 };
5116
5117 qup_i2c8_data_clk: qu
5118 pins = "gpio3
5119 function = "q
5120 };
5121
5122 qup_i2c9_data_clk: qu
5123 pins = "gpio3
5124 function = "q
5125 };
5126
5127 qup_i2c10_data_clk: q
5128 pins = "gpio4
5129 function = "q
5130 };
5131
5132 qup_i2c11_data_clk: q
5133 pins = "gpio4
5134 function = "q
5135 };
5136
5137 qup_i2c12_data_clk: q
5138 pins = "gpio4
5139 function = "q
5140 };
5141
5142 qup_i2c13_data_clk: q
5143 pins = "gpio5
5144 function = "q
5145 };
5146
5147 qup_i2c14_data_clk: q
5148 pins = "gpio5
5149 function = "q
5150 };
5151
5152 qup_i2c15_data_clk: q
5153 pins = "gpio6
5154 function = "q
5155 };
5156
5157 qup_spi0_data_clk: qu
5158 pins = "gpio0
5159 function = "q
5160 };
5161
5162 qup_spi0_cs: qup-spi0
5163 pins = "gpio3
5164 function = "q
5165 };
5166
5167 qup_spi0_cs_gpio: qup
5168 pins = "gpio3
5169 function = "g
5170 };
5171
5172 qup_spi1_data_clk: qu
5173 pins = "gpio4
5174 function = "q
5175 };
5176
5177 qup_spi1_cs: qup-spi1
5178 pins = "gpio7
5179 function = "q
5180 };
5181
5182 qup_spi1_cs_gpio: qup
5183 pins = "gpio7
5184 function = "g
5185 };
5186
5187 qup_spi2_data_clk: qu
5188 pins = "gpio8
5189 function = "q
5190 };
5191
5192 qup_spi2_cs: qup-spi2
5193 pins = "gpio1
5194 function = "q
5195 };
5196
5197 qup_spi2_cs_gpio: qup
5198 pins = "gpio1
5199 function = "g
5200 };
5201
5202 qup_spi3_data_clk: qu
5203 pins = "gpio1
5204 function = "q
5205 };
5206
5207 qup_spi3_cs: qup-spi3
5208 pins = "gpio1
5209 function = "q
5210 };
5211
5212 qup_spi3_cs_gpio: qup
5213 pins = "gpio1
5214 function = "g
5215 };
5216
5217 qup_spi4_data_clk: qu
5218 pins = "gpio1
5219 function = "q
5220 };
5221
5222 qup_spi4_cs: qup-spi4
5223 pins = "gpio1
5224 function = "q
5225 };
5226
5227 qup_spi4_cs_gpio: qup
5228 pins = "gpio1
5229 function = "g
5230 };
5231
5232 qup_spi5_data_clk: qu
5233 pins = "gpio2
5234 function = "q
5235 };
5236
5237 qup_spi5_cs: qup-spi5
5238 pins = "gpio2
5239 function = "q
5240 };
5241
5242 qup_spi5_cs_gpio: qup
5243 pins = "gpio2
5244 function = "g
5245 };
5246
5247 qup_spi6_data_clk: qu
5248 pins = "gpio2
5249 function = "q
5250 };
5251
5252 qup_spi6_cs: qup-spi6
5253 pins = "gpio2
5254 function = "q
5255 };
5256
5257 qup_spi6_cs_gpio: qup
5258 pins = "gpio2
5259 function = "g
5260 };
5261
5262 qup_spi7_data_clk: qu
5263 pins = "gpio2
5264 function = "q
5265 };
5266
5267 qup_spi7_cs: qup-spi7
5268 pins = "gpio3
5269 function = "q
5270 };
5271
5272 qup_spi7_cs_gpio: qup
5273 pins = "gpio3
5274 function = "g
5275 };
5276
5277 qup_spi8_data_clk: qu
5278 pins = "gpio3
5279 function = "q
5280 };
5281
5282 qup_spi8_cs: qup-spi8
5283 pins = "gpio3
5284 function = "q
5285 };
5286
5287 qup_spi8_cs_gpio: qup
5288 pins = "gpio3
5289 function = "g
5290 };
5291
5292 qup_spi9_data_clk: qu
5293 pins = "gpio3
5294 function = "q
5295 };
5296
5297 qup_spi9_cs: qup-spi9
5298 pins = "gpio3
5299 function = "q
5300 };
5301
5302 qup_spi9_cs_gpio: qup
5303 pins = "gpio3
5304 function = "g
5305 };
5306
5307 qup_spi10_data_clk: q
5308 pins = "gpio4
5309 function = "q
5310 };
5311
5312 qup_spi10_cs: qup-spi
5313 pins = "gpio4
5314 function = "q
5315 };
5316
5317 qup_spi10_cs_gpio: qu
5318 pins = "gpio4
5319 function = "g
5320 };
5321
5322 qup_spi11_data_clk: q
5323 pins = "gpio4
5324 function = "q
5325 };
5326
5327 qup_spi11_cs: qup-spi
5328 pins = "gpio4
5329 function = "q
5330 };
5331
5332 qup_spi11_cs_gpio: qu
5333 pins = "gpio4
5334 function = "g
5335 };
5336
5337 qup_spi12_data_clk: q
5338 pins = "gpio4
5339 function = "q
5340 };
5341
5342 qup_spi12_cs: qup-spi
5343 pins = "gpio5
5344 function = "q
5345 };
5346
5347 qup_spi12_cs_gpio: qu
5348 pins = "gpio5
5349 function = "g
5350 };
5351
5352 qup_spi13_data_clk: q
5353 pins = "gpio5
5354 function = "q
5355 };
5356
5357 qup_spi13_cs: qup-spi
5358 pins = "gpio5
5359 function = "q
5360 };
5361
5362 qup_spi13_cs_gpio: qu
5363 pins = "gpio5
5364 function = "g
5365 };
5366
5367 qup_spi14_data_clk: q
5368 pins = "gpio5
5369 function = "q
5370 };
5371
5372 qup_spi14_cs: qup-spi
5373 pins = "gpio5
5374 function = "q
5375 };
5376
5377 qup_spi14_cs_gpio: qu
5378 pins = "gpio5
5379 function = "g
5380 };
5381
5382 qup_spi15_data_clk: q
5383 pins = "gpio6
5384 function = "q
5385 };
5386
5387 qup_spi15_cs: qup-spi
5388 pins = "gpio6
5389 function = "q
5390 };
5391
5392 qup_spi15_cs_gpio: qu
5393 pins = "gpio6
5394 function = "g
5395 };
5396
5397 qup_uart0_cts: qup-ua
5398 pins = "gpio0
5399 function = "q
5400 };
5401
5402 qup_uart0_rts: qup-ua
5403 pins = "gpio1
5404 function = "q
5405 };
5406
5407 qup_uart0_tx: qup-uar
5408 pins = "gpio2
5409 function = "q
5410 };
5411
5412 qup_uart0_rx: qup-uar
5413 pins = "gpio3
5414 function = "q
5415 };
5416
5417 qup_uart1_cts: qup-ua
5418 pins = "gpio4
5419 function = "q
5420 };
5421
5422 qup_uart1_rts: qup-ua
5423 pins = "gpio5
5424 function = "q
5425 };
5426
5427 qup_uart1_tx: qup-uar
5428 pins = "gpio6
5429 function = "q
5430 };
5431
5432 qup_uart1_rx: qup-uar
5433 pins = "gpio7
5434 function = "q
5435 };
5436
5437 qup_uart2_cts: qup-ua
5438 pins = "gpio8
5439 function = "q
5440 };
5441
5442 qup_uart2_rts: qup-ua
5443 pins = "gpio9
5444 function = "q
5445 };
5446
5447 qup_uart2_tx: qup-uar
5448 pins = "gpio1
5449 function = "q
5450 };
5451
5452 qup_uart2_rx: qup-uar
5453 pins = "gpio1
5454 function = "q
5455 };
5456
5457 qup_uart3_cts: qup-ua
5458 pins = "gpio1
5459 function = "q
5460 };
5461
5462 qup_uart3_rts: qup-ua
5463 pins = "gpio1
5464 function = "q
5465 };
5466
5467 qup_uart3_tx: qup-uar
5468 pins = "gpio1
5469 function = "q
5470 };
5471
5472 qup_uart3_rx: qup-uar
5473 pins = "gpio1
5474 function = "q
5475 };
5476
5477 qup_uart4_cts: qup-ua
5478 pins = "gpio1
5479 function = "q
5480 };
5481
5482 qup_uart4_rts: qup-ua
5483 pins = "gpio1
5484 function = "q
5485 };
5486
5487 qup_uart4_tx: qup-uar
5488 pins = "gpio1
5489 function = "q
5490 };
5491
5492 qup_uart4_rx: qup-uar
5493 pins = "gpio1
5494 function = "q
5495 };
5496
5497 qup_uart5_tx: qup-uar
5498 pins = "gpio2
5499 function = "q
5500 };
5501
5502 qup_uart5_rx: qup-uar
5503 pins = "gpio2
5504 function = "q
5505 };
5506
5507 qup_uart6_cts: qup-ua
5508 pins = "gpio2
5509 function = "q
5510 };
5511
5512 qup_uart6_rts: qup-ua
5513 pins = "gpio2
5514 function = "q
5515 };
5516
5517 qup_uart6_tx: qup-uar
5518 pins = "gpio2
5519 function = "q
5520 };
5521
5522 qup_uart6_rx: qup-uar
5523 pins = "gpio2
5524 function = "q
5525 };
5526
5527 qup_uart7_cts: qup-ua
5528 pins = "gpio2
5529 function = "q
5530 };
5531
5532 qup_uart7_rts: qup-ua
5533 pins = "gpio2
5534 function = "q
5535 };
5536
5537 qup_uart7_tx: qup-uar
5538 pins = "gpio3
5539 function = "q
5540 };
5541
5542 qup_uart7_rx: qup-uar
5543 pins = "gpio3
5544 function = "q
5545 };
5546
5547 qup_uart8_cts: qup-ua
5548 pins = "gpio3
5549 function = "q
5550 };
5551
5552 qup_uart8_rts: qup-ua
5553 pins = "gpio3
5554 function = "q
5555 };
5556
5557 qup_uart8_tx: qup-uar
5558 pins = "gpio3
5559 function = "q
5560 };
5561
5562 qup_uart8_rx: qup-uar
5563 pins = "gpio3
5564 function = "q
5565 };
5566
5567 qup_uart9_cts: qup-ua
5568 pins = "gpio3
5569 function = "q
5570 };
5571
5572 qup_uart9_rts: qup-ua
5573 pins = "gpio3
5574 function = "q
5575 };
5576
5577 qup_uart9_tx: qup-uar
5578 pins = "gpio3
5579 function = "q
5580 };
5581
5582 qup_uart9_rx: qup-uar
5583 pins = "gpio3
5584 function = "q
5585 };
5586
5587 qup_uart10_cts: qup-u
5588 pins = "gpio4
5589 function = "q
5590 };
5591
5592 qup_uart10_rts: qup-u
5593 pins = "gpio4
5594 function = "q
5595 };
5596
5597 qup_uart10_tx: qup-ua
5598 pins = "gpio4
5599 function = "q
5600 };
5601
5602 qup_uart10_rx: qup-ua
5603 pins = "gpio4
5604 function = "q
5605 };
5606
5607 qup_uart11_cts: qup-u
5608 pins = "gpio4
5609 function = "q
5610 };
5611
5612 qup_uart11_rts: qup-u
5613 pins = "gpio4
5614 function = "q
5615 };
5616
5617 qup_uart11_tx: qup-ua
5618 pins = "gpio4
5619 function = "q
5620 };
5621
5622 qup_uart11_rx: qup-ua
5623 pins = "gpio4
5624 function = "q
5625 };
5626
5627 qup_uart12_cts: qup-u
5628 pins = "gpio4
5629 function = "q
5630 };
5631
5632 qup_uart12_rts: qup-u
5633 pins = "gpio4
5634 function = "q
5635 };
5636
5637 qup_uart12_tx: qup-ua
5638 pins = "gpio5
5639 function = "q
5640 };
5641
5642 qup_uart12_rx: qup-ua
5643 pins = "gpio5
5644 function = "q
5645 };
5646
5647 qup_uart13_cts: qup-u
5648 pins = "gpio5
5649 function = "q
5650 };
5651
5652 qup_uart13_rts: qup-u
5653 pins = "gpio5
5654 function = "q
5655 };
5656
5657 qup_uart13_tx: qup-ua
5658 pins = "gpio5
5659 function = "q
5660 };
5661
5662 qup_uart13_rx: qup-ua
5663 pins = "gpio5
5664 function = "q
5665 };
5666
5667 qup_uart14_cts: qup-u
5668 pins = "gpio5
5669 function = "q
5670 };
5671
5672 qup_uart14_rts: qup-u
5673 pins = "gpio5
5674 function = "q
5675 };
5676
5677 qup_uart14_tx: qup-ua
5678 pins = "gpio5
5679 function = "q
5680 };
5681
5682 qup_uart14_rx: qup-ua
5683 pins = "gpio5
5684 function = "q
5685 };
5686
5687 qup_uart15_cts: qup-u
5688 pins = "gpio6
5689 function = "q
5690 };
5691
5692 qup_uart15_rts: qup-u
5693 pins = "gpio6
5694 function = "q
5695 };
5696
5697 qup_uart15_tx: qup-ua
5698 pins = "gpio6
5699 function = "q
5700 };
5701
5702 qup_uart15_rx: qup-ua
5703 pins = "gpio6
5704 function = "q
5705 };
5706
5707 sdc1_clk: sdc1-clk-st
5708 pins = "sdc1_
5709 };
5710
5711 sdc1_cmd: sdc1-cmd-st
5712 pins = "sdc1_
5713 };
5714
5715 sdc1_data: sdc1-data-
5716 pins = "sdc1_
5717 };
5718
5719 sdc1_rclk: sdc1-rclk-
5720 pins = "sdc1_
5721 };
5722
5723 sdc1_clk_sleep: sdc1-
5724 pins = "sdc1_
5725 drive-strengt
5726 bias-bus-hold
5727 };
5728
5729 sdc1_cmd_sleep: sdc1-
5730 pins = "sdc1_
5731 drive-strengt
5732 bias-bus-hold
5733 };
5734
5735 sdc1_data_sleep: sdc1
5736 pins = "sdc1_
5737 drive-strengt
5738 bias-bus-hold
5739 };
5740
5741 sdc1_rclk_sleep: sdc1
5742 pins = "sdc1_
5743 drive-strengt
5744 bias-bus-hold
5745 };
5746
5747 sdc2_clk: sdc2-clk-st
5748 pins = "sdc2_
5749 };
5750
5751 sdc2_cmd: sdc2-cmd-st
5752 pins = "sdc2_
5753 };
5754
5755 sdc2_data: sdc2-data-
5756 pins = "sdc2_
5757 };
5758
5759 sdc2_clk_sleep: sdc2-
5760 pins = "sdc2_
5761 drive-strengt
5762 bias-bus-hold
5763 };
5764
5765 sdc2_cmd_sleep: sdc2-
5766 pins = "sdc2_
5767 drive-strengt
5768 bias-bus-hold
5769 };
5770
5771 sdc2_data_sleep: sdc2
5772 pins = "sdc2_
5773 drive-strengt
5774 bias-bus-hold
5775 };
5776 };
5777
5778 sram@146a5000 {
5779 compatible = "qcom,sc
5780 reg = <0 0x146a5000 0
5781
5782 #address-cells = <1>;
5783 #size-cells = <1>;
5784
5785 ranges = <0 0 0x146a5
5786
5787 pil-reloc@594c {
5788 compatible =
5789 reg = <0x594c
5790 };
5791 };
5792
5793 apps_smmu: iommu@15000000 {
5794 compatible = "qcom,sc
5795 reg = <0 0x15000000 0
5796 #iommu-cells = <2>;
5797 #global-interrupts =
5798 dma-coherent;
5799 interrupts = <GIC_SPI
5800 <GIC_SPI
5801 <GIC_SPI
5802 <GIC_SPI
5803 <GIC_SPI
5804 <GIC_SPI
5805 <GIC_SPI
5806 <GIC_SPI
5807 <GIC_SPI
5808 <GIC_SPI
5809 <GIC_SPI
5810 <GIC_SPI
5811 <GIC_SPI
5812 <GIC_SPI
5813 <GIC_SPI
5814 <GIC_SPI
5815 <GIC_SPI
5816 <GIC_SPI
5817 <GIC_SPI
5818 <GIC_SPI
5819 <GIC_SPI
5820 <GIC_SPI
5821 <GIC_SPI
5822 <GIC_SPI
5823 <GIC_SPI
5824 <GIC_SPI
5825 <GIC_SPI
5826 <GIC_SPI
5827 <GIC_SPI
5828 <GIC_SPI
5829 <GIC_SPI
5830 <GIC_SPI
5831 <GIC_SPI
5832 <GIC_SPI
5833 <GIC_SPI
5834 <GIC_SPI
5835 <GIC_SPI
5836 <GIC_SPI
5837 <GIC_SPI
5838 <GIC_SPI
5839 <GIC_SPI
5840 <GIC_SPI
5841 <GIC_SPI
5842 <GIC_SPI
5843 <GIC_SPI
5844 <GIC_SPI
5845 <GIC_SPI
5846 <GIC_SPI
5847 <GIC_SPI
5848 <GIC_SPI
5849 <GIC_SPI
5850 <GIC_SPI
5851 <GIC_SPI
5852 <GIC_SPI
5853 <GIC_SPI
5854 <GIC_SPI
5855 <GIC_SPI
5856 <GIC_SPI
5857 <GIC_SPI
5858 <GIC_SPI
5859 <GIC_SPI
5860 <GIC_SPI
5861 <GIC_SPI
5862 <GIC_SPI
5863 <GIC_SPI
5864 <GIC_SPI
5865 <GIC_SPI
5866 <GIC_SPI
5867 <GIC_SPI
5868 <GIC_SPI
5869 <GIC_SPI
5870 <GIC_SPI
5871 <GIC_SPI
5872 <GIC_SPI
5873 <GIC_SPI
5874 <GIC_SPI
5875 <GIC_SPI
5876 <GIC_SPI
5877 <GIC_SPI
5878 <GIC_SPI
5879 <GIC_SPI
5880 };
5881
5882 anoc_1_tbu: tbu@151dd000 {
5883 compatible = "qcom,sc
5884 reg = <0x0 0x151dd000
5885 interconnects = <&gem
5886 &cno
5887 qcom,stream-id-range
5888 };
5889
5890 anoc_2_tbu: tbu@151e1000 {
5891 compatible = "qcom,sc
5892 reg = <0x0 0x151e1000
5893 interconnects = <&gem
5894 &cno
5895 qcom,stream-id-range
5896 };
5897
5898 mnoc_hf_0_tbu: tbu@151e5000 {
5899 compatible = "qcom,sc
5900 reg = <0x0 0x151e5000
5901 interconnects = <&mms
5902 &mc_
5903 power-domains = <&gcc
5904 qcom,stream-id-range
5905 };
5906
5907 mnoc_hf_1_tbu: tbu@151e9000 {
5908 compatible = "qcom,sc
5909 reg = <0x0 0x151e9000
5910 interconnects = <&mms
5911 &mc_
5912 power-domains = <&gcc
5913 qcom,stream-id-range
5914 };
5915
5916 compute_dsp_1_tbu: tbu@151ed0
5917 compatible = "qcom,sc
5918 reg = <0x0 0x151ed000
5919 interconnects = <&nsp
5920 &mc_
5921 power-domains = <&gcc
5922 qcom,stream-id-range
5923 };
5924
5925 compute_dsp_0_tbu: tbu@151f10
5926 compatible = "qcom,sc
5927 reg = <0x0 0x151f1000
5928 interconnects = <&nsp
5929 &mc_
5930 power-domains = <&gcc
5931 qcom,stream-id-range
5932 };
5933
5934 adsp_tbu: tbu@151f5000 {
5935 compatible = "qcom,sc
5936 reg = <0x0 0x151f5000
5937 interconnects = <&gem
5938 &lpa
5939 qcom,stream-id-range
5940 };
5941
5942 anoc_1_pcie_tbu: tbu@151f9000
5943 compatible = "qcom,sc
5944 reg = <0x0 0x151f9000
5945 interconnects = <&gem
5946 &cno
5947 qcom,stream-id-range
5948 };
5949
5950 mnoc_sf_0_tbu: tbu@151fd000 {
5951 compatible = "qcom,sc
5952 reg = <0x0 0x151fd000
5953 interconnects = <&mms
5954 &mc_
5955 power-domains = <&gcc
5956 qcom,stream-id-range
5957 };
5958
5959 intc: interrupt-controller@17
5960 compatible = "arm,gic
5961 reg = <0 0x17a00000 0
5962 <0 0x17a60000 0
5963 interrupts = <GIC_PPI
5964 #interrupt-cells = <3
5965 interrupt-controller;
5966 #address-cells = <2>;
5967 #size-cells = <2>;
5968 ranges;
5969
5970 msi-controller@17a400
5971 compatible =
5972 reg = <0 0x17
5973 msi-controlle
5974 #msi-cells =
5975 status = "dis
5976 };
5977 };
5978
5979 watchdog: watchdog@17c10000 {
5980 compatible = "qcom,ap
5981 reg = <0 0x17c10000 0
5982 clocks = <&sleep_clk>
5983 interrupts = <GIC_SPI
5984 status = "reserved";
5985 };
5986
5987 timer@17c20000 {
5988 #address-cells = <1>;
5989 #size-cells = <1>;
5990 ranges = <0 0 0 0x200
5991 compatible = "arm,arm
5992 reg = <0 0x17c20000 0
5993
5994 frame@17c21000 {
5995 frame-number
5996 interrupts =
5997
5998 reg = <0x17c2
5999 <0x17c2
6000 };
6001
6002 frame@17c23000 {
6003 frame-number
6004 interrupts =
6005 reg = <0x17c2
6006 status = "dis
6007 };
6008
6009 frame@17c25000 {
6010 frame-number
6011 interrupts =
6012 reg = <0x17c2
6013 status = "dis
6014 };
6015
6016 frame@17c27000 {
6017 frame-number
6018 interrupts =
6019 reg = <0x17c2
6020 status = "dis
6021 };
6022
6023 frame@17c29000 {
6024 frame-number
6025 interrupts =
6026 reg = <0x17c2
6027 status = "dis
6028 };
6029
6030 frame@17c2b000 {
6031 frame-number
6032 interrupts =
6033 reg = <0x17c2
6034 status = "dis
6035 };
6036
6037 frame@17c2d000 {
6038 frame-number
6039 interrupts =
6040 reg = <0x17c2
6041 status = "dis
6042 };
6043 };
6044
6045 apps_rsc: rsc@18200000 {
6046 compatible = "qcom,rp
6047 reg = <0 0x18200000 0
6048 <0 0x18210000 0
6049 <0 0x18220000 0
6050 reg-names = "drv-0",
6051 interrupts = <GIC_SPI
6052 <GIC_SPI
6053 <GIC_SPI
6054 qcom,tcs-offset = <0x
6055 qcom,drv-id = <2>;
6056 qcom,tcs-config = <AC
6057 <SL
6058 <WA
6059 <CO
6060 power-domains = <&CLU
6061
6062 apps_bcm_voter: bcm-v
6063 compatible =
6064 };
6065
6066 rpmhpd: power-control
6067 compatible =
6068 #power-domain
6069 operating-poi
6070
6071 rpmhpd_opp_ta
6072 compa
6073
6074 rpmhp
6075
6076 };
6077
6078 rpmhp
6079
6080 };
6081
6082 rpmhp
6083
6084 };
6085
6086 rpmhp
6087
6088 };
6089
6090 rpmhp
6091
6092 };
6093
6094 rpmhp
6095
6096 };
6097
6098 rpmhp
6099
6100 };
6101
6102 rpmhp
6103
6104 };
6105
6106 rpmhp
6107
6108 };
6109 };
6110 };
6111
6112 rpmhcc: clock-control
6113 compatible =
6114 clocks = <&xo
6115 clock-names =
6116 #clock-cells
6117 };
6118 };
6119
6120 epss_l3: interconnect@1859000
6121 compatible = "qcom,sc
6122 reg = <0 0x18590000 0
6123 clocks = <&rpmhcc RPM
6124 clock-names = "xo", "
6125 #interconnect-cells =
6126 };
6127
6128 cpufreq_hw: cpufreq@18591000
6129 compatible = "qcom,sc
6130 reg = <0 0x18591000 0
6131 <0 0x18592000 0
6132 <0 0x18593000 0
6133
6134 interrupts = <GIC_SPI
6135 <GIC_SPI
6136 <GIC_SPI
6137 interrupt-names = "dc
6138 "dc
6139 "dc
6140
6141 clocks = <&rpmhcc RPM
6142 clock-names = "xo", "
6143 #freq-domain-cells =
6144 #clock-cells = <1>;
6145 };
6146 };
6147
6148 sound: sound {
6149 };
6150
6151 thermal_zones: thermal-zones {
6152 cpu0-thermal {
6153 polling-delay-passive
6154
6155 thermal-sensors = <&t
6156
6157 trips {
6158 cpu0_alert0:
6159 tempe
6160 hyste
6161 type
6162 };
6163
6164 cpu0_alert1:
6165 tempe
6166 hyste
6167 type
6168 };
6169
6170 cpu0_crit: cp
6171 tempe
6172 hyste
6173 type
6174 };
6175 };
6176
6177 cooling-maps {
6178 map0 {
6179 trip
6180 cooli
6181
6182
6183
6184 };
6185 map1 {
6186 trip
6187 cooli
6188
6189
6190
6191 };
6192 };
6193 };
6194
6195 cpu1-thermal {
6196 polling-delay-passive
6197
6198 thermal-sensors = <&t
6199
6200 trips {
6201 cpu1_alert0:
6202 tempe
6203 hyste
6204 type
6205 };
6206
6207 cpu1_alert1:
6208 tempe
6209 hyste
6210 type
6211 };
6212
6213 cpu1_crit: cp
6214 tempe
6215 hyste
6216 type
6217 };
6218 };
6219
6220 cooling-maps {
6221 map0 {
6222 trip
6223 cooli
6224
6225
6226
6227 };
6228 map1 {
6229 trip
6230 cooli
6231
6232
6233
6234 };
6235 };
6236 };
6237
6238 cpu2-thermal {
6239 polling-delay-passive
6240
6241 thermal-sensors = <&t
6242
6243 trips {
6244 cpu2_alert0:
6245 tempe
6246 hyste
6247 type
6248 };
6249
6250 cpu2_alert1:
6251 tempe
6252 hyste
6253 type
6254 };
6255
6256 cpu2_crit: cp
6257 tempe
6258 hyste
6259 type
6260 };
6261 };
6262
6263 cooling-maps {
6264 map0 {
6265 trip
6266 cooli
6267
6268
6269
6270 };
6271 map1 {
6272 trip
6273 cooli
6274
6275
6276
6277 };
6278 };
6279 };
6280
6281 cpu3-thermal {
6282 polling-delay-passive
6283
6284 thermal-sensors = <&t
6285
6286 trips {
6287 cpu3_alert0:
6288 tempe
6289 hyste
6290 type
6291 };
6292
6293 cpu3_alert1:
6294 tempe
6295 hyste
6296 type
6297 };
6298
6299 cpu3_crit: cp
6300 tempe
6301 hyste
6302 type
6303 };
6304 };
6305
6306 cooling-maps {
6307 map0 {
6308 trip
6309 cooli
6310
6311
6312
6313 };
6314 map1 {
6315 trip
6316 cooli
6317
6318
6319
6320 };
6321 };
6322 };
6323
6324 cpu4-thermal {
6325 polling-delay-passive
6326
6327 thermal-sensors = <&t
6328
6329 trips {
6330 cpu4_alert0:
6331 tempe
6332 hyste
6333 type
6334 };
6335
6336 cpu4_alert1:
6337 tempe
6338 hyste
6339 type
6340 };
6341
6342 cpu4_crit: cp
6343 tempe
6344 hyste
6345 type
6346 };
6347 };
6348
6349 cooling-maps {
6350 map0 {
6351 trip
6352 cooli
6353
6354
6355
6356 };
6357 map1 {
6358 trip
6359 cooli
6360
6361
6362
6363 };
6364 };
6365 };
6366
6367 cpu5-thermal {
6368 polling-delay-passive
6369
6370 thermal-sensors = <&t
6371
6372 trips {
6373 cpu5_alert0:
6374 tempe
6375 hyste
6376 type
6377 };
6378
6379 cpu5_alert1:
6380 tempe
6381 hyste
6382 type
6383 };
6384
6385 cpu5_crit: cp
6386 tempe
6387 hyste
6388 type
6389 };
6390 };
6391
6392 cooling-maps {
6393 map0 {
6394 trip
6395 cooli
6396
6397
6398
6399 };
6400 map1 {
6401 trip
6402 cooli
6403
6404
6405
6406 };
6407 };
6408 };
6409
6410 cpu6-thermal {
6411 polling-delay-passive
6412
6413 thermal-sensors = <&t
6414
6415 trips {
6416 cpu6_alert0:
6417 tempe
6418 hyste
6419 type
6420 };
6421
6422 cpu6_alert1:
6423 tempe
6424 hyste
6425 type
6426 };
6427
6428 cpu6_crit: cp
6429 tempe
6430 hyste
6431 type
6432 };
6433 };
6434
6435 cooling-maps {
6436 map0 {
6437 trip
6438 cooli
6439
6440
6441
6442 };
6443 map1 {
6444 trip
6445 cooli
6446
6447
6448
6449 };
6450 };
6451 };
6452
6453 cpu7-thermal {
6454 polling-delay-passive
6455
6456 thermal-sensors = <&t
6457
6458 trips {
6459 cpu7_alert0:
6460 tempe
6461 hyste
6462 type
6463 };
6464
6465 cpu7_alert1:
6466 tempe
6467 hyste
6468 type
6469 };
6470
6471 cpu7_crit: cp
6472 tempe
6473 hyste
6474 type
6475 };
6476 };
6477
6478 cooling-maps {
6479 map0 {
6480 trip
6481 cooli
6482
6483
6484
6485 };
6486 map1 {
6487 trip
6488 cooli
6489
6490
6491
6492 };
6493 };
6494 };
6495
6496 cpu8-thermal {
6497 polling-delay-passive
6498
6499 thermal-sensors = <&t
6500
6501 trips {
6502 cpu8_alert0:
6503 tempe
6504 hyste
6505 type
6506 };
6507
6508 cpu8_alert1:
6509 tempe
6510 hyste
6511 type
6512 };
6513
6514 cpu8_crit: cp
6515 tempe
6516 hyste
6517 type
6518 };
6519 };
6520
6521 cooling-maps {
6522 map0 {
6523 trip
6524 cooli
6525
6526
6527
6528 };
6529 map1 {
6530 trip
6531 cooli
6532
6533
6534
6535 };
6536 };
6537 };
6538
6539 cpu9-thermal {
6540 polling-delay-passive
6541
6542 thermal-sensors = <&t
6543
6544 trips {
6545 cpu9_alert0:
6546 tempe
6547 hyste
6548 type
6549 };
6550
6551 cpu9_alert1:
6552 tempe
6553 hyste
6554 type
6555 };
6556
6557 cpu9_crit: cp
6558 tempe
6559 hyste
6560 type
6561 };
6562 };
6563
6564 cooling-maps {
6565 map0 {
6566 trip
6567 cooli
6568
6569
6570
6571 };
6572 map1 {
6573 trip
6574 cooli
6575
6576
6577
6578 };
6579 };
6580 };
6581
6582 cpu10-thermal {
6583 polling-delay-passive
6584
6585 thermal-sensors = <&t
6586
6587 trips {
6588 cpu10_alert0:
6589 tempe
6590 hyste
6591 type
6592 };
6593
6594 cpu10_alert1:
6595 tempe
6596 hyste
6597 type
6598 };
6599
6600 cpu10_crit: c
6601 tempe
6602 hyste
6603 type
6604 };
6605 };
6606
6607 cooling-maps {
6608 map0 {
6609 trip
6610 cooli
6611
6612
6613
6614 };
6615 map1 {
6616 trip
6617 cooli
6618
6619
6620
6621 };
6622 };
6623 };
6624
6625 cpu11-thermal {
6626 polling-delay-passive
6627
6628 thermal-sensors = <&t
6629
6630 trips {
6631 cpu11_alert0:
6632 tempe
6633 hyste
6634 type
6635 };
6636
6637 cpu11_alert1:
6638 tempe
6639 hyste
6640 type
6641 };
6642
6643 cpu11_crit: c
6644 tempe
6645 hyste
6646 type
6647 };
6648 };
6649
6650 cooling-maps {
6651 map0 {
6652 trip
6653 cooli
6654
6655
6656
6657 };
6658 map1 {
6659 trip
6660 cooli
6661
6662
6663
6664 };
6665 };
6666 };
6667
6668 aoss0-thermal {
6669 polling-delay-passive
6670
6671 thermal-sensors = <&t
6672
6673 trips {
6674 aoss0_alert0:
6675 tempe
6676 hyste
6677 type
6678 };
6679
6680 aoss0_crit: a
6681 tempe
6682 hyste
6683 type
6684 };
6685 };
6686 };
6687
6688 aoss1-thermal {
6689 polling-delay-passive
6690
6691 thermal-sensors = <&t
6692
6693 trips {
6694 aoss1_alert0:
6695 tempe
6696 hyste
6697 type
6698 };
6699
6700 aoss1_crit: a
6701 tempe
6702 hyste
6703 type
6704 };
6705 };
6706 };
6707
6708 cpuss0-thermal {
6709 polling-delay-passive
6710
6711 thermal-sensors = <&t
6712
6713 trips {
6714 cpuss0_alert0
6715 tempe
6716 hyste
6717 type
6718 };
6719 cpuss0_crit:
6720 tempe
6721 hyste
6722 type
6723 };
6724 };
6725 };
6726
6727 cpuss1-thermal {
6728 polling-delay-passive
6729
6730 thermal-sensors = <&t
6731
6732 trips {
6733 cpuss1_alert0
6734 tempe
6735 hyste
6736 type
6737 };
6738 cpuss1_crit:
6739 tempe
6740 hyste
6741 type
6742 };
6743 };
6744 };
6745
6746 gpuss0-thermal {
6747 polling-delay-passive
6748
6749 thermal-sensors = <&t
6750
6751 trips {
6752 gpuss0_alert0
6753 tempe
6754 hyste
6755 type
6756 };
6757
6758 gpuss0_crit:
6759 tempe
6760 hyste
6761 type
6762 };
6763 };
6764
6765 cooling-maps {
6766 map0 {
6767 trip
6768 cooli
6769 };
6770 };
6771 };
6772
6773 gpuss1-thermal {
6774 polling-delay-passive
6775
6776 thermal-sensors = <&t
6777
6778 trips {
6779 gpuss1_alert0
6780 tempe
6781 hyste
6782 type
6783 };
6784
6785 gpuss1_crit:
6786 tempe
6787 hyste
6788 type
6789 };
6790 };
6791
6792 cooling-maps {
6793 map0 {
6794 trip
6795 cooli
6796 };
6797 };
6798 };
6799
6800 nspss0-thermal {
6801 thermal-sensors = <&t
6802
6803 trips {
6804 nspss0_alert0
6805 tempe
6806 hyste
6807 type
6808 };
6809
6810 nspss0_crit:
6811 tempe
6812 hyste
6813 type
6814 };
6815 };
6816 };
6817
6818 nspss1-thermal {
6819 thermal-sensors = <&t
6820
6821 trips {
6822 nspss1_alert0
6823 tempe
6824 hyste
6825 type
6826 };
6827
6828 nspss1_crit:
6829 tempe
6830 hyste
6831 type
6832 };
6833 };
6834 };
6835
6836 video-thermal {
6837 thermal-sensors = <&t
6838
6839 trips {
6840 video_alert0:
6841 tempe
6842 hyste
6843 type
6844 };
6845
6846 video_crit: v
6847 tempe
6848 hyste
6849 type
6850 };
6851 };
6852 };
6853
6854 ddr-thermal {
6855 thermal-sensors = <&t
6856
6857 trips {
6858 ddr_alert0: t
6859 tempe
6860 hyste
6861 type
6862 };
6863
6864 ddr_crit: ddr
6865 tempe
6866 hyste
6867 type
6868 };
6869 };
6870 };
6871
6872 mdmss0-thermal {
6873 thermal-sensors = <&t
6874
6875 trips {
6876 mdmss0_alert0
6877 tempe
6878 hyste
6879 type
6880 };
6881
6882 mdmss0_crit:
6883 tempe
6884 hyste
6885 type
6886 };
6887 };
6888 };
6889
6890 mdmss1-thermal {
6891 thermal-sensors = <&t
6892
6893 trips {
6894 mdmss1_alert0
6895 tempe
6896 hyste
6897 type
6898 };
6899
6900 mdmss1_crit:
6901 tempe
6902 hyste
6903 type
6904 };
6905 };
6906 };
6907
6908 mdmss2-thermal {
6909 thermal-sensors = <&t
6910
6911 trips {
6912 mdmss2_alert0
6913 tempe
6914 hyste
6915 type
6916 };
6917
6918 mdmss2_crit:
6919 tempe
6920 hyste
6921 type
6922 };
6923 };
6924 };
6925
6926 mdmss3-thermal {
6927 thermal-sensors = <&t
6928
6929 trips {
6930 mdmss3_alert0
6931 tempe
6932 hyste
6933 type
6934 };
6935
6936 mdmss3_crit:
6937 tempe
6938 hyste
6939 type
6940 };
6941 };
6942 };
6943
6944 camera0-thermal {
6945 thermal-sensors = <&t
6946
6947 trips {
6948 camera0_alert
6949 tempe
6950 hyste
6951 type
6952 };
6953
6954 camera0_crit:
6955 tempe
6956 hyste
6957 type
6958 };
6959 };
6960 };
6961 };
6962
6963 timer {
6964 compatible = "arm,armv8-timer
6965 interrupts = <GIC_PPI 13 IRQ_
6966 <GIC_PPI 14 IRQ_
6967 <GIC_PPI 11 IRQ_
6968 <GIC_PPI 10 IRQ_
6969 };
6970 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.