1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * SDM670 SoC device tree source, adapted from
4 *
5 * Copyright (c) 2018, The Linux Foundation. A
6 * Copyright (c) 2022, Richard Acayan. All rig
7 */
8
9 #include <dt-bindings/clock/qcom,dispcc-sdm845
10 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
11 #include <dt-bindings/clock/qcom,rpmh.h>
12 #include <dt-bindings/dma/qcom-gpi.h>
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/interconnect/qcom,osm-l3
15 #include <dt-bindings/interconnect/qcom,sdm670
16 #include <dt-bindings/interrupt-controller/arm
17 #include <dt-bindings/phy/phy-qcom-qusb2.h>
18 #include <dt-bindings/power/qcom-rpmpd.h>
19 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
20
21 / {
22 interrupt-parent = <&intc>;
23
24 #address-cells = <2>;
25 #size-cells = <2>;
26
27 aliases { };
28
29 chosen { };
30
31 cpus {
32 #address-cells = <2>;
33 #size-cells = <0>;
34
35 CPU0: cpu@0 {
36 device_type = "cpu";
37 compatible = "qcom,kry
38 reg = <0x0 0x0>;
39 enable-method = "psci"
40 capacity-dmips-mhz = <
41 dynamic-power-coeffici
42 qcom,freq-domain = <&c
43 operating-points-v2 =
44 interconnects = <&glad
45 <&osm_
46 power-domains = <&CPU_
47 power-domain-names = "
48 next-level-cache = <&L
49 L2_0: l2-cache {
50 compatible = "
51 next-level-cac
52 cache-level =
53 cache-unified;
54 L3_0: l3-cache
55 compat
56 cache-
57 cache-
58 };
59 };
60 };
61
62 CPU1: cpu@100 {
63 device_type = "cpu";
64 compatible = "qcom,kry
65 reg = <0x0 0x100>;
66 enable-method = "psci"
67 capacity-dmips-mhz = <
68 dynamic-power-coeffici
69 qcom,freq-domain = <&c
70 operating-points-v2 =
71 interconnects = <&glad
72 <&osm_
73 power-domains = <&CPU_
74 power-domain-names = "
75 next-level-cache = <&L
76 L2_100: l2-cache {
77 compatible = "
78 cache-level =
79 cache-unified;
80 next-level-cac
81 };
82 };
83
84 CPU2: cpu@200 {
85 device_type = "cpu";
86 compatible = "qcom,kry
87 reg = <0x0 0x200>;
88 enable-method = "psci"
89 capacity-dmips-mhz = <
90 dynamic-power-coeffici
91 qcom,freq-domain = <&c
92 operating-points-v2 =
93 interconnects = <&glad
94 <&osm_
95 power-domains = <&CPU_
96 power-domain-names = "
97 next-level-cache = <&L
98 L2_200: l2-cache {
99 compatible = "
100 cache-level =
101 cache-unified;
102 next-level-cac
103 };
104 };
105
106 CPU3: cpu@300 {
107 device_type = "cpu";
108 compatible = "qcom,kry
109 reg = <0x0 0x300>;
110 enable-method = "psci"
111 capacity-dmips-mhz = <
112 dynamic-power-coeffici
113 qcom,freq-domain = <&c
114 operating-points-v2 =
115 interconnects = <&glad
116 <&osm_
117 power-domains = <&CPU_
118 power-domain-names = "
119 next-level-cache = <&L
120 L2_300: l2-cache {
121 compatible = "
122 cache-level =
123 cache-unified;
124 next-level-cac
125 };
126 };
127
128 CPU4: cpu@400 {
129 device_type = "cpu";
130 compatible = "qcom,kry
131 reg = <0x0 0x400>;
132 enable-method = "psci"
133 capacity-dmips-mhz = <
134 dynamic-power-coeffici
135 qcom,freq-domain = <&c
136 operating-points-v2 =
137 interconnects = <&glad
138 <&osm_
139 power-domains = <&CPU_
140 power-domain-names = "
141 next-level-cache = <&L
142 L2_400: l2-cache {
143 compatible = "
144 cache-level =
145 cache-unified;
146 next-level-cac
147 };
148 };
149
150 CPU5: cpu@500 {
151 device_type = "cpu";
152 compatible = "qcom,kry
153 reg = <0x0 0x500>;
154 enable-method = "psci"
155 capacity-dmips-mhz = <
156 dynamic-power-coeffici
157 qcom,freq-domain = <&c
158 operating-points-v2 =
159 interconnects = <&glad
160 <&osm_
161 power-domains = <&CPU_
162 power-domain-names = "
163 next-level-cache = <&L
164 L2_500: l2-cache {
165 compatible = "
166 cache-level =
167 cache-unified;
168 next-level-cac
169 };
170 };
171
172 CPU6: cpu@600 {
173 device_type = "cpu";
174 compatible = "qcom,kry
175 reg = <0x0 0x600>;
176 enable-method = "psci"
177 capacity-dmips-mhz = <
178 dynamic-power-coeffici
179 qcom,freq-domain = <&c
180 operating-points-v2 =
181 interconnects = <&glad
182 <&osm_
183 power-domains = <&CPU_
184 power-domain-names = "
185 next-level-cache = <&L
186 L2_600: l2-cache {
187 compatible = "
188 cache-level =
189 cache-unified;
190 next-level-cac
191 };
192 };
193
194 CPU7: cpu@700 {
195 device_type = "cpu";
196 compatible = "qcom,kry
197 reg = <0x0 0x700>;
198 enable-method = "psci"
199 capacity-dmips-mhz = <
200 dynamic-power-coeffici
201 qcom,freq-domain = <&c
202 operating-points-v2 =
203 interconnects = <&glad
204 <&osm_
205 power-domains = <&CPU_
206 power-domain-names = "
207 next-level-cache = <&L
208 L2_700: l2-cache {
209 compatible = "
210 cache-level =
211 cache-unified;
212 next-level-cac
213 };
214 };
215
216 cpu-map {
217 cluster0 {
218 core0 {
219 cpu =
220 };
221
222 core1 {
223 cpu =
224 };
225
226 core2 {
227 cpu =
228 };
229
230 core3 {
231 cpu =
232 };
233
234 core4 {
235 cpu =
236 };
237
238 core5 {
239 cpu =
240 };
241
242 core6 {
243 cpu =
244 };
245
246 core7 {
247 cpu =
248 };
249 };
250 };
251
252 idle-states {
253 entry-method = "psci";
254
255 LITTLE_CPU_SLEEP_0: cp
256 compatible = "
257 idle-state-nam
258 arm,psci-suspe
259 entry-latency-
260 exit-latency-u
261 min-residency-
262 local-timer-st
263 };
264
265 BIG_CPU_SLEEP_0: cpu-s
266 compatible = "
267 idle-state-nam
268 arm,psci-suspe
269 entry-latency-
270 exit-latency-u
271 min-residency-
272 local-timer-st
273 };
274 };
275
276 domain-idle-states {
277 CLUSTER_SLEEP_0: clust
278 compatible = "
279 arm,psci-suspe
280 entry-latency-
281 exit-latency-u
282 min-residency-
283 };
284 };
285 };
286
287 firmware {
288 scm {
289 compatible = "qcom,scm
290 };
291 };
292
293 memory@80000000 {
294 device_type = "memory";
295 /* We expect the bootloader to
296 reg = <0x0 0x80000000 0x0 0x0>
297 };
298
299 cpu0_opp_table: opp-table-cpu0 {
300 compatible = "operating-points
301 opp-shared;
302
303 cpu0_opp1: opp-300000000 {
304 opp-hz = /bits/ 64 <30
305 opp-peak-kBps = <40000
306 };
307
308 cpu0_opp2: opp-576000000 {
309 opp-hz = /bits/ 64 <57
310 opp-peak-kBps = <40000
311 };
312
313 cpu0_opp3: opp-748800000 {
314 opp-hz = /bits/ 64 <74
315 opp-peak-kBps = <12000
316 };
317
318 cpu0_opp4: opp-998400000 {
319 opp-hz = /bits/ 64 <99
320 opp-peak-kBps = <18040
321 };
322
323 cpu0_opp5: opp-1209600000 {
324 opp-hz = /bits/ 64 <12
325 opp-peak-kBps = <21880
326 };
327
328 cpu0_opp6: opp-1324800000 {
329 opp-hz = /bits/ 64 <13
330 opp-peak-kBps = <21880
331 };
332
333 cpu0_opp7: opp-1516800000 {
334 opp-hz = /bits/ 64 <15
335 opp-peak-kBps = <30720
336 };
337
338 cpu0_opp8: opp-1612800000 {
339 opp-hz = /bits/ 64 <16
340 opp-peak-kBps = <30720
341 };
342
343 cpu0_opp9: opp-1708800000 {
344 opp-hz = /bits/ 64 <17
345 opp-peak-kBps = <40680
346 };
347 };
348
349 cpu6_opp_table: opp-table-cpu6 {
350 compatible = "operating-points
351 opp-shared;
352
353 cpu6_opp1: opp-300000000 {
354 opp-hz = /bits/ 64 <30
355 opp-peak-kBps = <40000
356 };
357
358 cpu6_opp2: opp-652800000 {
359 opp-hz = /bits/ 64 <65
360 opp-peak-kBps = <40000
361 };
362
363 cpu6_opp3: opp-825600000 {
364 opp-hz = /bits/ 64 <82
365 opp-peak-kBps = <12000
366 };
367
368 cpu6_opp4: opp-979200000 {
369 opp-hz = /bits/ 64 <97
370 opp-peak-kBps = <12000
371 };
372
373 cpu6_opp5: opp-1132800000 {
374 opp-hz = /bits/ 64 <11
375 opp-peak-kBps = <21880
376 };
377
378 cpu6_opp6: opp-1363200000 {
379 opp-hz = /bits/ 64 <13
380 opp-peak-kBps = <40680
381 };
382
383 cpu6_opp7: opp-1536000000 {
384 opp-hz = /bits/ 64 <15
385 opp-peak-kBps = <40680
386 };
387
388 cpu6_opp8: opp-1747200000 {
389 opp-hz = /bits/ 64 <17
390 opp-peak-kBps = <40680
391 };
392
393 cpu6_opp9: opp-1843200000 {
394 opp-hz = /bits/ 64 <18
395 opp-peak-kBps = <40680
396 };
397
398 cpu6_opp10: opp-1996800000 {
399 opp-hz = /bits/ 64 <19
400 opp-peak-kBps = <62200
401 };
402 };
403
404 dsi_opp_table: opp-table-dsi {
405 compatible = "operating-points
406
407 opp-19200000 {
408 opp-hz = /bits/ 64 <19
409 required-opps = <&rpmh
410 };
411
412 opp-180000000 {
413 opp-hz = /bits/ 64 <18
414 required-opps = <&rpmh
415 };
416
417 opp-275000000 {
418 opp-hz = /bits/ 64 <27
419 required-opps = <&rpmh
420 };
421
422 opp-358000000 {
423 opp-hz = /bits/ 64 <35
424 required-opps = <&rpmh
425 };
426 };
427
428 psci {
429 compatible = "arm,psci-1.0";
430 method = "smc";
431
432 CPU_PD0: power-domain-cpu0 {
433 #power-domain-cells =
434 power-domains = <&CLUS
435 domain-idle-states = <
436 };
437
438 CPU_PD1: power-domain-cpu1 {
439 #power-domain-cells =
440 power-domains = <&CLUS
441 domain-idle-states = <
442 };
443
444 CPU_PD2: power-domain-cpu2 {
445 #power-domain-cells =
446 power-domains = <&CLUS
447 domain-idle-states = <
448 };
449
450 CPU_PD3: power-domain-cpu3 {
451 #power-domain-cells =
452 power-domains = <&CLUS
453 domain-idle-states = <
454 };
455
456 CPU_PD4: power-domain-cpu4 {
457 #power-domain-cells =
458 power-domains = <&CLUS
459 domain-idle-states = <
460 };
461
462 CPU_PD5: power-domain-cpu5 {
463 #power-domain-cells =
464 power-domains = <&CLUS
465 domain-idle-states = <
466 };
467
468 CPU_PD6: power-domain-cpu6 {
469 #power-domain-cells =
470 power-domains = <&CLUS
471 domain-idle-states = <
472 };
473
474 CPU_PD7: power-domain-cpu7 {
475 #power-domain-cells =
476 power-domains = <&CLUS
477 domain-idle-states = <
478 };
479
480 CLUSTER_PD: power-domain-clust
481 #power-domain-cells =
482 domain-idle-states = <
483 };
484 };
485
486 reserved-memory {
487 #address-cells = <2>;
488 #size-cells = <2>;
489 ranges;
490
491 hyp_mem: hyp-mem@85700000 {
492 reg = <0 0x85700000 0
493 no-map;
494 };
495
496 xbl_mem: xbl-mem@85e00000 {
497 reg = <0 0x85e00000 0
498 no-map;
499 };
500
501 aop_mem: aop-mem@85fc0000 {
502 reg = <0 0x85fc0000 0
503 no-map;
504 };
505
506 aop_cmd_db_mem: aop-cmd-db-mem
507 compatible = "qcom,cmd
508 reg = <0 0x85fe0000 0
509 no-map;
510 };
511
512 smem@86000000 {
513 compatible = "qcom,sme
514 reg = <0 0x86000000 0
515 no-map;
516 hwlocks = <&tcsr_mutex
517 };
518
519 tz_mem: tz@86200000 {
520 reg = <0 0x86200000 0
521 no-map;
522 };
523
524 camera_mem: camera-mem@8ab0000
525 reg = <0 0x8ab00000 0
526 no-map;
527 };
528
529 mpss_region: mpss@8b000000 {
530 reg = <0 0x8b000000 0
531 no-map;
532 };
533
534 venus_mem: venus@92e00000 {
535 reg = <0 0x92e00000 0
536 no-map;
537 };
538
539 wlan_msa_mem: wlan-msa@9330000
540 reg = <0 0x93300000 0
541 no-map;
542 };
543
544 cdsp_mem: cdsp@93400000 {
545 reg = <0 0x93400000 0
546 no-map;
547 };
548
549 mba_region: mba@93c00000 {
550 reg = <0 0x93c00000 0
551 no-map;
552 };
553
554 adsp_mem: adsp@93e00000 {
555 reg = <0 0x93e00000 0
556 no-map;
557 };
558
559 ipa_fw_mem: ipa-fw@95c00000 {
560 reg = <0 0x95c00000 0
561 no-map;
562 };
563
564 ipa_gsi_mem: ipa-gsi@95c10000
565 reg = <0 0x95c10000 0
566 no-map;
567 };
568
569 gpu_mem: gpu@95c15000 {
570 reg = <0 0x95c15000 0
571 no-map;
572 };
573
574 spss_mem: spss@97b00000 {
575 reg = <0 0x97b00000 0
576 no-map;
577 };
578
579 qseecom_mem: qseecom@9e400000
580 reg = <0 0x9e400000 0
581 no-map;
582 };
583 };
584
585 timer {
586 compatible = "arm,armv8-timer"
587 interrupts = <GIC_PPI 1 IRQ_TY
588 <GIC_PPI 2 IRQ_TY
589 <GIC_PPI 3 IRQ_TY
590 <GIC_PPI 0 IRQ_TY
591 };
592
593 soc: soc@0 {
594 #address-cells = <2>;
595 #size-cells = <2>;
596 ranges = <0 0 0 0 0x10 0>;
597 dma-ranges = <0 0 0 0 0x10 0>;
598 compatible = "simple-bus";
599
600 gcc: clock-controller@100000 {
601 compatible = "qcom,gcc
602 reg = <0 0x00100000 0
603 clocks = <&rpmhcc RPMH
604 <&rpmhcc RPMH
605 <&sleep_clk>;
606 clock-names = "bi_tcxo
607 "bi_tcxo
608 "sleep_c
609 #clock-cells = <1>;
610 #reset-cells = <1>;
611 #power-domain-cells =
612 };
613
614 qfprom: qfprom@784000 {
615 compatible = "qcom,sdm
616 reg = <0 0x00784000 0
617 #address-cells = <1>;
618 #size-cells = <1>;
619
620 qusb2_hstx_trim: hstx-
621 reg = <0x1eb 0
622 bits = <1 4>;
623 };
624 };
625
626 sdhc_1: mmc@7c4000 {
627 compatible = "qcom,sdm
628 reg = <0 0x007c4000 0
629 <0 0x007c5000 0
630 <0 0x007c8000 0
631 reg-names = "hc", "cqh
632
633 interrupts = <GIC_SPI
634 <GIC_SPI
635 interrupt-names = "hc_
636
637 clocks = <&gcc GCC_SDC
638 <&gcc GCC_SDC
639 <&rpmhcc RPMH
640 <&gcc GCC_SDC
641 <&gcc GCC_AGG
642 clock-names = "iface",
643 interconnects = <&aggr
644 <&glad
645 interconnect-names = "
646 operating-points-v2 =
647
648 iommus = <&apps_smmu 0
649
650 pinctrl-names = "defau
651 pinctrl-0 = <&sdc1_sta
652 pinctrl-1 = <&sdc1_sta
653 power-domains = <&rpmh
654
655 bus-width = <8>;
656 non-removable;
657
658 status = "disabled";
659
660 sdhc1_opp_table: opp-t
661 compatible = "
662
663 opp-20000000 {
664 opp-hz
665 requir
666 opp-pe
667 opp-av
668 };
669
670 opp-50000000 {
671 opp-hz
672 requir
673 opp-pe
674 opp-av
675 };
676
677 opp-100000000
678 opp-hz
679 requir
680 opp-pe
681 opp-av
682 };
683
684 opp-384000000
685 opp-hz
686 requir
687 opp-pe
688 opp-av
689 };
690 };
691 };
692
693 gpi_dma0: dma-controller@80000
694 #dma-cells = <3>;
695 compatible = "qcom,sdm
696 reg = <0 0x00800000 0
697 interrupts = <GIC_SPI
698 <GIC_SPI
699 <GIC_SPI
700 <GIC_SPI
701 <GIC_SPI
702 <GIC_SPI
703 <GIC_SPI
704 <GIC_SPI
705 <GIC_SPI
706 <GIC_SPI
707 <GIC_SPI
708 <GIC_SPI
709 <GIC_SPI
710 dma-channels = <13>;
711 dma-channel-mask = <0x
712 iommus = <&apps_smmu 0
713 status = "disabled";
714 };
715
716 qupv3_id_0: geniqup@8c0000 {
717 compatible = "qcom,gen
718 reg = <0 0x008c0000 0
719 clock-names = "m-ahb",
720 clocks = <&gcc GCC_QUP
721 <&gcc GCC_QUP
722 iommus = <&apps_smmu 0
723 #address-cells = <2>;
724 #size-cells = <2>;
725 ranges;
726 interconnects = <&aggr
727 interconnect-names = "
728 status = "disabled";
729
730 i2c0: i2c@880000 {
731 compatible = "
732 reg = <0 0x008
733 clock-names =
734 clocks = <&gcc
735 pinctrl-names
736 pinctrl-0 = <&
737 interrupts = <
738 #address-cells
739 #size-cells =
740 power-domains
741 interconnects
742
743
744 interconnect-n
745 dmas = <&gpi_d
746 <&gpi_d
747 dma-names = "t
748 status = "disa
749 };
750
751 i2c1: i2c@884000 {
752 compatible = "
753 reg = <0 0x008
754 clock-names =
755 clocks = <&gcc
756 pinctrl-names
757 pinctrl-0 = <&
758 interrupts = <
759 #address-cells
760 #size-cells =
761 power-domains
762 interconnects
763
764
765 interconnect-n
766 dmas = <&gpi_d
767 <&gpi_d
768 dma-names = "t
769 status = "disa
770 };
771
772 i2c2: i2c@888000 {
773 compatible = "
774 reg = <0 0x008
775 clock-names =
776 clocks = <&gcc
777 pinctrl-names
778 pinctrl-0 = <&
779 interrupts = <
780 #address-cells
781 #size-cells =
782 power-domains
783 interconnects
784
785
786 interconnect-n
787 dmas = <&gpi_d
788 <&gpi_d
789 dma-names = "t
790 status = "disa
791 };
792
793 i2c3: i2c@88c000 {
794 compatible = "
795 reg = <0 0x008
796 clock-names =
797 clocks = <&gcc
798 pinctrl-names
799 pinctrl-0 = <&
800 interrupts = <
801 #address-cells
802 #size-cells =
803 power-domains
804 interconnects
805
806
807 interconnect-n
808 dmas = <&gpi_d
809 <&gpi_d
810 dma-names = "t
811 status = "disa
812 };
813
814 i2c4: i2c@890000 {
815 compatible = "
816 reg = <0 0x008
817 clock-names =
818 clocks = <&gcc
819 pinctrl-names
820 pinctrl-0 = <&
821 interrupts = <
822 #address-cells
823 #size-cells =
824 power-domains
825 interconnects
826
827
828 interconnect-n
829 dmas = <&gpi_d
830 <&gpi_d
831 dma-names = "t
832 status = "disa
833 };
834
835 i2c5: i2c@894000 {
836 compatible = "
837 reg = <0 0x008
838 clock-names =
839 clocks = <&gcc
840 pinctrl-names
841 pinctrl-0 = <&
842 interrupts = <
843 #address-cells
844 #size-cells =
845 power-domains
846 interconnects
847
848
849 interconnect-n
850 dmas = <&gpi_d
851 <&gpi_d
852 dma-names = "t
853 status = "disa
854 };
855
856 i2c6: i2c@898000 {
857 compatible = "
858 reg = <0 0x008
859 clock-names =
860 clocks = <&gcc
861 pinctrl-names
862 pinctrl-0 = <&
863 interrupts = <
864 #address-cells
865 #size-cells =
866 power-domains
867 interconnects
868
869
870 interconnect-n
871 dmas = <&gpi_d
872 <&gpi_d
873 dma-names = "t
874 status = "disa
875 };
876
877 i2c7: i2c@89c000 {
878 compatible = "
879 reg = <0 0x008
880 clock-names =
881 clocks = <&gcc
882 pinctrl-names
883 pinctrl-0 = <&
884 interrupts = <
885 #address-cells
886 #size-cells =
887 power-domains
888 interconnects
889
890
891 interconnect-n
892 dmas = <&gpi_d
893 <&gpi_d
894 dma-names = "t
895 status = "disa
896 };
897 };
898
899 gpi_dma1: dma-controller@a0000
900 #dma-cells = <3>;
901 compatible = "qcom,sdm
902 reg = <0 0x00a00000 0
903 interrupts = <GIC_SPI
904 <GIC_SPI
905 <GIC_SPI
906 <GIC_SPI
907 <GIC_SPI
908 <GIC_SPI
909 <GIC_SPI
910 <GIC_SPI
911 <GIC_SPI
912 <GIC_SPI
913 <GIC_SPI
914 <GIC_SPI
915 <GIC_SPI
916 dma-channels = <13>;
917 dma-channel-mask = <0x
918 iommus = <&apps_smmu 0
919 status = "disabled";
920 };
921
922 qupv3_id_1: geniqup@ac0000 {
923 compatible = "qcom,gen
924 reg = <0 0x00ac0000 0
925 clock-names = "m-ahb",
926 clocks = <&gcc GCC_QUP
927 <&gcc GCC_QUP
928 iommus = <&apps_smmu 0
929 #address-cells = <2>;
930 #size-cells = <2>;
931 ranges;
932 interconnects = <&aggr
933 interconnect-names = "
934 status = "disabled";
935
936 i2c8: i2c@a80000 {
937 compatible = "
938 reg = <0 0x00a
939 clock-names =
940 clocks = <&gcc
941 pinctrl-names
942 pinctrl-0 = <&
943 interrupts = <
944 #address-cells
945 #size-cells =
946 power-domains
947 interconnects
948
949
950 interconnect-n
951 dmas = <&gpi_d
952 <&gpi_d
953 dma-names = "t
954 status = "disa
955 };
956
957 i2c9: i2c@a84000 {
958 compatible = "
959 reg = <0 0x00a
960 clock-names =
961 clocks = <&gcc
962 pinctrl-names
963 pinctrl-0 = <&
964 interrupts = <
965 #address-cells
966 #size-cells =
967 power-domains
968 interconnects
969
970
971 interconnect-n
972 dmas = <&gpi_d
973 <&gpi_d
974 dma-names = "t
975 status = "disa
976 };
977
978 i2c10: i2c@a88000 {
979 compatible = "
980 reg = <0 0x00a
981 clock-names =
982 clocks = <&gcc
983 pinctrl-names
984 pinctrl-0 = <&
985 interrupts = <
986 #address-cells
987 #size-cells =
988 power-domains
989 interconnects
990
991
992 interconnect-n
993 dmas = <&gpi_d
994 <&gpi_d
995 dma-names = "t
996 status = "disa
997 };
998
999 i2c11: i2c@a8c000 {
1000 compatible =
1001 reg = <0 0x00
1002 clock-names =
1003 clocks = <&gc
1004 pinctrl-names
1005 pinctrl-0 = <
1006 interrupts =
1007 #address-cell
1008 #size-cells =
1009 power-domains
1010 interconnects
1011
1012
1013 interconnect-
1014 dmas = <&gpi_
1015 <&gpi_
1016 dma-names = "
1017 status = "dis
1018 };
1019
1020 i2c12: i2c@a90000 {
1021 compatible =
1022 reg = <0 0x00
1023 clock-names =
1024 clocks = <&gc
1025 pinctrl-names
1026 pinctrl-0 = <
1027 interrupts =
1028 #address-cell
1029 #size-cells =
1030 power-domains
1031 interconnects
1032
1033
1034 interconnect-
1035 dmas = <&gpi_
1036 <&gpi_
1037 dma-names = "
1038 status = "dis
1039 };
1040
1041 i2c13: i2c@a94000 {
1042 compatible =
1043 reg = <0 0x00
1044 clock-names =
1045 clocks = <&gc
1046 pinctrl-names
1047 pinctrl-0 = <
1048 interrupts =
1049 #address-cell
1050 #size-cells =
1051 power-domains
1052 interconnects
1053
1054
1055 interconnect-
1056 dmas = <&gpi_
1057 <&gpi_
1058 dma-names = "
1059 status = "dis
1060 };
1061
1062 i2c14: i2c@a98000 {
1063 compatible =
1064 reg = <0 0x00
1065 clock-names =
1066 clocks = <&gc
1067 pinctrl-names
1068 pinctrl-0 = <
1069 interrupts =
1070 #address-cell
1071 #size-cells =
1072 power-domains
1073 interconnects
1074
1075
1076 interconnect-
1077 dmas = <&gpi_
1078 <&gpi_
1079 dma-names = "
1080 status = "dis
1081 };
1082
1083 i2c15: i2c@a9c000 {
1084 compatible =
1085 reg = <0 0x00
1086 clock-names =
1087 clocks = <&gc
1088 pinctrl-names
1089 pinctrl-0 = <
1090 interrupts =
1091 #address-cell
1092 #size-cells =
1093 power-domains
1094 interconnects
1095
1096
1097 interconnect-
1098 dmas = <&gpi_
1099 <&gpi_
1100 dma-names = "
1101 status = "dis
1102 };
1103 };
1104
1105 mem_noc: interconnect@1380000
1106 compatible = "qcom,sd
1107 reg = <0 0x01380000 0
1108 #interconnect-cells =
1109 qcom,bcm-voters = <&a
1110 };
1111
1112 dc_noc: interconnect@14e0000
1113 compatible = "qcom,sd
1114 reg = <0 0x014e0000 0
1115 #interconnect-cells =
1116 qcom,bcm-voters = <&a
1117 };
1118
1119 config_noc: interconnect@1500
1120 compatible = "qcom,sd
1121 reg = <0 0x01500000 0
1122 #interconnect-cells =
1123 qcom,bcm-voters = <&a
1124 };
1125
1126 system_noc: interconnect@1620
1127 compatible = "qcom,sd
1128 reg = <0 0x01620000 0
1129 #interconnect-cells =
1130 qcom,bcm-voters = <&a
1131 };
1132
1133 aggre1_noc: interconnect@16e0
1134 compatible = "qcom,sd
1135 reg = <0 0x016e0000 0
1136 #interconnect-cells =
1137 qcom,bcm-voters = <&a
1138 };
1139
1140 aggre2_noc: interconnect@1700
1141 compatible = "qcom,sd
1142 reg = <0 0x01700000 0
1143 #interconnect-cells =
1144 qcom,bcm-voters = <&a
1145 };
1146
1147 mmss_noc: interconnect@174000
1148 compatible = "qcom,sd
1149 reg = <0 0x01740000 0
1150 #interconnect-cells =
1151 qcom,bcm-voters = <&a
1152 };
1153
1154 tcsr_mutex: hwlock@1f40000 {
1155 compatible = "qcom,tc
1156 reg = <0 0x01f40000 0
1157 #hwlock-cells = <1>;
1158 };
1159
1160 tlmm: pinctrl@3400000 {
1161 compatible = "qcom,sd
1162 reg = <0 0x03400000 0
1163 interrupts = <GIC_SPI
1164 gpio-controller;
1165 #gpio-cells = <2>;
1166 interrupt-controller;
1167 #interrupt-cells = <2
1168 gpio-ranges = <&tlmm
1169 wakeup-parent = <&pdc
1170
1171 qup_i2c0_default: qup
1172 pins = "gpio0
1173 function = "q
1174 };
1175
1176 qup_i2c1_default: qup
1177 pins = "gpio1
1178 function = "q
1179 };
1180
1181 qup_i2c2_default: qup
1182 pins = "gpio2
1183 function = "q
1184 };
1185
1186 qup_i2c3_default: qup
1187 pins = "gpio4
1188 function = "q
1189 };
1190
1191 qup_i2c4_default: qup
1192 pins = "gpio8
1193 function = "q
1194 };
1195
1196 qup_i2c5_default: qup
1197 pins = "gpio8
1198 function = "q
1199 };
1200
1201 qup_i2c6_default: qup
1202 pins = "gpio4
1203 function = "q
1204 };
1205
1206 qup_i2c7_default: qup
1207 pins = "gpio9
1208 function = "q
1209 };
1210
1211 qup_i2c8_default: qup
1212 pins = "gpio6
1213 function = "q
1214 };
1215
1216 qup_i2c9_default: qup
1217 pins = "gpio6
1218 function = "q
1219 };
1220
1221 qup_i2c10_default: qu
1222 pins = "gpio5
1223 function = "q
1224 };
1225
1226 qup_i2c11_default: qu
1227 pins = "gpio3
1228 function = "q
1229 };
1230
1231 qup_i2c12_default: qu
1232 pins = "gpio4
1233 function = "q
1234 };
1235
1236 qup_i2c13_default: qu
1237 pins = "gpio1
1238 function = "q
1239 };
1240
1241 qup_i2c14_default: qu
1242 pins = "gpio3
1243 function = "q
1244 };
1245
1246 qup_i2c15_default: qu
1247 pins = "gpio8
1248 function = "q
1249 };
1250
1251 sdc1_state_on: sdc1-o
1252 clk-pins {
1253 pins
1254 bias-
1255 drive
1256 };
1257
1258 cmd-pins {
1259 pins
1260 bias-
1261 drive
1262 };
1263
1264 data-pins {
1265 pins
1266 bias-
1267 drive
1268 };
1269
1270 rclk-pins {
1271 pins
1272 bias-
1273 };
1274 };
1275
1276 sdc1_state_off: sdc1-
1277 clk-pins {
1278 pins
1279 bias-
1280 drive
1281 };
1282
1283 cmd-pins {
1284 pins
1285 bias-
1286 drive
1287 };
1288
1289 data-pins {
1290 pins
1291 bias-
1292 drive
1293 };
1294
1295 rclk-pins {
1296 pins
1297 bias-
1298 };
1299 };
1300 };
1301
1302 usb_1_hsphy: phy@88e2000 {
1303 compatible = "qcom,sd
1304 reg = <0 0x088e2000 0
1305 #phy-cells = <0>;
1306
1307 clocks = <&gcc GCC_US
1308 <&rpmhcc RPM
1309 clock-names = "cfg_ah
1310
1311 resets = <&gcc GCC_QU
1312
1313 nvmem-cells = <&qusb2
1314
1315 status = "disabled";
1316 };
1317
1318 usb_1: usb@a6f8800 {
1319 compatible = "qcom,sd
1320 reg = <0 0x0a6f8800 0
1321 #address-cells = <2>;
1322 #size-cells = <2>;
1323 ranges;
1324 dma-ranges;
1325
1326 clocks = <&gcc GCC_CF
1327 <&gcc GCC_US
1328 <&gcc GCC_AG
1329 <&gcc GCC_US
1330 <&gcc GCC_US
1331 clock-names = "cfg_no
1332 "core",
1333 "iface"
1334 "sleep"
1335 "mock_u
1336
1337 assigned-clocks = <&g
1338 <&g
1339 assigned-clock-rates
1340
1341 interrupts-extended =
1342
1343
1344
1345
1346 interrupt-names = "pw
1347 "hs
1348 "dp
1349 "dm
1350 "ss
1351
1352 power-domains = <&gcc
1353
1354 resets = <&gcc GCC_US
1355
1356 interconnects = <&agg
1357 <&gla
1358 interconnect-names =
1359
1360 status = "disabled";
1361
1362 usb_1_dwc3: usb@a6000
1363 compatible =
1364 reg = <0 0x0a
1365 interrupts =
1366 iommus = <&ap
1367 snps,dis_u2_s
1368 snps,dis_enbl
1369 phys = <&usb_
1370 phy-names = "
1371 };
1372 };
1373
1374 pdc: interrupt-controller@b22
1375 compatible = "qcom,sd
1376 reg = <0 0x0b220000 0
1377 qcom,pdc-ranges = <0
1378 <54
1379 <11
1380 #interrupt-cells = <2
1381 interrupt-parent = <&
1382 interrupt-controller;
1383 };
1384
1385 spmi_bus: spmi@c440000 {
1386 compatible = "qcom,sp
1387 reg = <0 0x0c440000 0
1388 <0 0x0c600000 0
1389 <0 0x0e600000 0
1390 <0 0x0e700000 0
1391 <0 0x0c40a000 0
1392 reg-names = "core", "
1393 interrupt-names = "pe
1394 interrupts = <GIC_SPI
1395 qcom,ee = <0>;
1396 qcom,channel = <0>;
1397 #address-cells = <2>;
1398 #size-cells = <0>;
1399 interrupt-controller;
1400 #interrupt-cells = <4
1401 };
1402
1403 mdss: display-subsystem@ae000
1404 compatible = "qcom,sd
1405 reg = <0 0x0ae00000 0
1406 reg-names = "mdss";
1407
1408 power-domains = <&dis
1409
1410 clocks = <&dispcc DIS
1411 <&dispcc DIS
1412 clock-names = "iface"
1413
1414 interrupts = <GIC_SPI
1415 interrupt-controller;
1416 #interrupt-cells = <1
1417
1418 interconnects = <&mms
1419 <&mms
1420 interconnect-names =
1421
1422 iommus = <&apps_smmu
1423 <&apps_smmu
1424
1425 #address-cells = <2>;
1426 #size-cells = <2>;
1427 ranges;
1428
1429 status = "disabled";
1430
1431 mdss_mdp: display-con
1432 compatible =
1433 reg = <0 0x0a
1434 <0 0x0a
1435 reg-names = "
1436
1437 clocks = <&gc
1438 <&di
1439 <&di
1440 <&di
1441 <&di
1442 clock-names =
1443
1444 assigned-cloc
1445 assigned-cloc
1446 operating-poi
1447 power-domains
1448
1449 interrupt-par
1450 interrupts =
1451
1452 ports {
1453 #addr
1454 #size
1455
1456 port@
1457
1458
1459
1460
1461 };
1462
1463 port@
1464
1465
1466
1467
1468 };
1469 };
1470
1471 mdp_opp_table
1472 compa
1473
1474 opp-1
1475
1476
1477 };
1478
1479 opp-1
1480
1481
1482 };
1483
1484 opp-3
1485
1486
1487 };
1488
1489 opp-4
1490
1491
1492 };
1493 };
1494 };
1495
1496 mdss_dsi0: dsi@ae9400
1497 compatible =
1498
1499 reg = <0 0x0a
1500 reg-names = "
1501
1502 interrupt-par
1503 interrupts =
1504
1505 clocks = <&di
1506 <&di
1507 <&di
1508 <&di
1509 <&di
1510 <&di
1511 clock-names =
1512
1513
1514
1515
1516
1517 assigned-cloc
1518
1519 assigned-cloc
1520
1521
1522 operating-poi
1523 power-domains
1524
1525 phys = <&mdss
1526
1527 #address-cell
1528 #size-cells =
1529
1530 status = "dis
1531
1532 ports {
1533 #addr
1534 #size
1535
1536 port@
1537
1538
1539
1540
1541 };
1542
1543 port@
1544
1545
1546
1547 };
1548 };
1549 };
1550
1551 mdss_dsi0_phy: phy@ae
1552 compatible =
1553 reg = <0 0x0a
1554 <0 0x0a
1555 <0 0x0a
1556 reg-names = "
1557 "
1558 "
1559
1560 #clock-cells
1561 #phy-cells =
1562
1563 clocks = <&di
1564 <&rp
1565 clock-names =
1566
1567 status = "dis
1568 };
1569
1570 mdss_dsi1: dsi@ae9600
1571 compatible =
1572
1573 reg = <0 0x0a
1574 reg-names = "
1575
1576 interrupt-par
1577 interrupts =
1578
1579 clocks = <&di
1580 <&di
1581 <&di
1582 <&di
1583 <&di
1584 <&di
1585 clock-names =
1586
1587
1588
1589
1590
1591 assigned-cloc
1592
1593 assigned-cloc
1594
1595 operating-poi
1596 power-domains
1597
1598 phys = <&mdss
1599
1600 #address-cell
1601 #size-cells =
1602
1603 status = "dis
1604
1605 ports {
1606 #addr
1607 #size
1608
1609 port@
1610
1611
1612
1613
1614 };
1615
1616 port@
1617
1618
1619
1620 };
1621 };
1622 };
1623
1624 mdss_dsi1_phy: phy@ae
1625 compatible =
1626 reg = <0 0x0a
1627 <0 0x0a
1628 <0 0x0a
1629 reg-names = "
1630 "
1631 "
1632
1633 #clock-cells
1634 #phy-cells =
1635
1636 clocks = <&di
1637 <&rp
1638 clock-names =
1639
1640 status = "dis
1641 };
1642 };
1643
1644 dispcc: clock-controller@af00
1645 compatible = "qcom,sd
1646 reg = <0 0x0af00000 0
1647 clocks = <&rpmhcc RPM
1648 <&gcc GCC_DI
1649 <&gcc GCC_DI
1650 <&mdss_dsi0_
1651 <&mdss_dsi0_
1652 <&mdss_dsi1_
1653 <&mdss_dsi1_
1654 <0>,
1655 <0>;
1656 clock-names = "bi_tcx
1657 "gcc_di
1658 "gcc_di
1659 "dsi0_p
1660 "dsi0_p
1661 "dsi1_p
1662 "dsi1_p
1663 "dp_lin
1664 "dp_vco
1665 #clock-cells = <1>;
1666 #reset-cells = <1>;
1667 #power-domain-cells =
1668 };
1669
1670 apps_smmu: iommu@15000000 {
1671 compatible = "qcom,sd
1672 reg = <0 0x15000000 0
1673 #iommu-cells = <2>;
1674 #global-interrupts =
1675 interrupts = <GIC_SPI
1676 <GIC_SPI
1677 <GIC_SPI
1678 <GIC_SPI
1679 <GIC_SPI
1680 <GIC_SPI
1681 <GIC_SPI
1682 <GIC_SPI
1683 <GIC_SPI
1684 <GIC_SPI
1685 <GIC_SPI
1686 <GIC_SPI
1687 <GIC_SPI
1688 <GIC_SPI
1689 <GIC_SPI
1690 <GIC_SPI
1691 <GIC_SPI
1692 <GIC_SPI
1693 <GIC_SPI
1694 <GIC_SPI
1695 <GIC_SPI
1696 <GIC_SPI
1697 <GIC_SPI
1698 <GIC_SPI
1699 <GIC_SPI
1700 <GIC_SPI
1701 <GIC_SPI
1702 <GIC_SPI
1703 <GIC_SPI
1704 <GIC_SPI
1705 <GIC_SPI
1706 <GIC_SPI
1707 <GIC_SPI
1708 <GIC_SPI
1709 <GIC_SPI
1710 <GIC_SPI
1711 <GIC_SPI
1712 <GIC_SPI
1713 <GIC_SPI
1714 <GIC_SPI
1715 <GIC_SPI
1716 <GIC_SPI
1717 <GIC_SPI
1718 <GIC_SPI
1719 <GIC_SPI
1720 <GIC_SPI
1721 <GIC_SPI
1722 <GIC_SPI
1723 <GIC_SPI
1724 <GIC_SPI
1725 <GIC_SPI
1726 <GIC_SPI
1727 <GIC_SPI
1728 <GIC_SPI
1729 <GIC_SPI
1730 <GIC_SPI
1731 <GIC_SPI
1732 <GIC_SPI
1733 <GIC_SPI
1734 <GIC_SPI
1735 <GIC_SPI
1736 <GIC_SPI
1737 <GIC_SPI
1738 <GIC_SPI
1739 <GIC_SPI
1740 };
1741
1742 gladiator_noc: interconnect@1
1743 compatible = "qcom,sd
1744 reg = <0 0x17900000 0
1745 #interconnect-cells =
1746 qcom,bcm-voters = <&a
1747 };
1748
1749 apps_rsc: rsc@179c0000 {
1750 compatible = "qcom,rp
1751 reg = <0 0x179c0000 0
1752 <0 0x179d0000 0
1753 <0 0x179e0000 0
1754 reg-names = "drv-0",
1755 interrupts = <GIC_SPI
1756 <GIC_SPI
1757 <GIC_SPI
1758 label = "apps_rsc";
1759 qcom,tcs-offset = <0x
1760 qcom,drv-id = <2>;
1761 qcom,tcs-config = <AC
1762 <SL
1763 <WA
1764 <CO
1765 power-domains = <&CLU
1766
1767 apps_bcm_voter: bcm-v
1768 compatible =
1769 };
1770
1771 rpmhcc: clock-control
1772 compatible =
1773 #clock-cells
1774 clock-names =
1775 clocks = <&xo
1776 };
1777
1778 rpmhpd: power-control
1779 compatible =
1780 #power-domain
1781 operating-poi
1782
1783 rpmhpd_opp_ta
1784 compa
1785
1786 rpmhp
1787
1788 };
1789
1790 rpmhp
1791
1792 };
1793
1794 rpmhp
1795
1796 };
1797
1798 rpmhp
1799
1800 };
1801
1802 rpmhp
1803
1804 };
1805
1806 rpmhp
1807
1808 };
1809
1810 rpmhp
1811
1812 };
1813
1814 rpmhp
1815
1816 };
1817
1818 rpmhp
1819
1820 };
1821
1822 rpmhp
1823
1824 };
1825 };
1826 };
1827 };
1828
1829 intc: interrupt-controller@17
1830 compatible = "arm,gic
1831 reg = <0 0x17a00000 0
1832 <0 0x17a60000 0
1833 interrupt-controller;
1834 interrupts = <GIC_PPI
1835 #interrupt-cells = <3
1836 };
1837
1838 osm_l3: interconnect@17d41000
1839 compatible = "qcom,sd
1840 reg = <0 0x17d41000 0
1841
1842 clocks = <&rpmhcc RPM
1843 clock-names = "xo", "
1844
1845 #interconnect-cells =
1846 };
1847
1848 cpufreq_hw: cpufreq@17d43000
1849 compatible = "qcom,sd
1850 reg = <0 0x17d43000 0
1851 reg-names = "freq-dom
1852
1853 clocks = <&rpmhcc RPM
1854 clock-names = "xo", "
1855
1856 #freq-domain-cells =
1857 };
1858 };
1859 };
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