1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * SDM845 Samsung S9 (SM-G9600) (starqltechn /
4 *
5 * Copyright (c) 2020, The Linux Foundation. A
6 */
7
8 /dts-v1/;
9
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/regulator/qcom,rpmh-regu
12 #include "sdm845.dtsi"
13
14 / {
15 chassis-type = "handset";
16 model = "Samsung Galaxy S9 SM-G9600";
17 compatible = "samsung,starqltechn", "q
18
19 chosen {
20 #address-cells = <2>;
21 #size-cells = <2>;
22 ranges;
23 framebuffer: framebuffer@9d400
24 compatible = "simple-f
25 reg = <0 0x9d400000 0
26 width = <1440>;
27 height = <2960>;
28 stride = <(1440 * 4)>;
29 format = "a8r8g8b8";
30 };
31 };
32
33 vph_pwr: vph-pwr-regulator {
34 compatible = "regulator-fixed"
35 regulator-name = "vph_pwr";
36 regulator-min-microvolt = <370
37 regulator-max-microvolt = <370
38 };
39
40 /*
41 * Apparently RPMh does not provide su
42 * is always-on; model it as a fixed r
43 */
44 vreg_s4a_1p8: pm8998-smps4 {
45 compatible = "regulator-fixed"
46 regulator-name = "vreg_s4a_1p8
47
48 regulator-min-microvolt = <180
49 regulator-max-microvolt = <180
50
51 regulator-always-on;
52 regulator-boot-on;
53
54 vin-supply = <&vph_pwr>;
55 };
56
57 reserved-memory {
58 memory@9d400000 {
59 reg = <0x0 0x9d400000
60 no-map;
61 };
62
63 memory@a1300000 {
64 compatible = "ramoops"
65 reg = <0x0 0xa1300000
66 record-size = <0x40000
67 console-size = <0x4000
68 ftrace-size = <0x40000
69 pmsg-size = <0x40000>;
70 };
71 };
72 };
73
74
75 &apps_rsc {
76 regulators-0 {
77 compatible = "qcom,pm8998-rpmh
78 qcom,pmic-id = "a";
79
80 vdd-s1-supply = <&vph_pwr>;
81 vdd-s2-supply = <&vph_pwr>;
82 vdd-s3-supply = <&vph_pwr>;
83 vdd-s4-supply = <&vph_pwr>;
84 vdd-s5-supply = <&vph_pwr>;
85 vdd-s6-supply = <&vph_pwr>;
86 vdd-s7-supply = <&vph_pwr>;
87 vdd-s8-supply = <&vph_pwr>;
88 vdd-s9-supply = <&vph_pwr>;
89 vdd-s10-supply = <&vph_pwr>;
90 vdd-s11-supply = <&vph_pwr>;
91 vdd-s12-supply = <&vph_pwr>;
92 vdd-s13-supply = <&vph_pwr>;
93 vdd-l1-l27-supply = <&vreg_s7a
94 vdd-l2-l8-l17-supply = <&vreg_
95 vdd-l3-l11-supply = <&vreg_s7a
96 vdd-l4-l5-supply = <&vreg_s7a_
97 vdd-l6-supply = <&vph_pwr>;
98 vdd-l7-l12-l14-l15-supply = <&
99 vdd-l26-supply = <&vreg_s3a_1p
100 vin-lvs-1-2-supply = <&vreg_s4
101
102 vreg_s2a_1p125: smps2 {
103 regulator-min-microvol
104 regulator-max-microvol
105 };
106
107 vreg_s3a_1p35: smps3 {
108 regulator-min-microvol
109 regulator-max-microvol
110 };
111
112 vreg_s5a_2p04: smps5 {
113 regulator-min-microvol
114 regulator-max-microvol
115 };
116
117 vreg_s7a_1p025: smps7 {
118 regulator-min-microvol
119 regulator-max-microvol
120 };
121
122 vdd_qusb_hs0:
123 vdda_hp_pcie_core:
124 vdda_mipi_csi0_0p9:
125 vdda_mipi_csi1_0p9:
126 vdda_mipi_csi2_0p9:
127 vdda_mipi_dsi0_pll:
128 vdda_mipi_dsi1_pll:
129 vdda_qlink_lv:
130 vdda_qlink_lv_ck:
131 vdda_qrefs_0p875:
132 vdda_pcie_core:
133 vdda_pll_cc_ebi01:
134 vdda_pll_cc_ebi23:
135 vdda_sp_sensor:
136 vdda_ufs1_core:
137 vdda_ufs2_core:
138 vdda_usb1_ss_core:
139 vdda_usb2_ss_core:
140 vreg_l1a_0p875: ldo1 {
141 regulator-min-microvol
142 regulator-max-microvol
143 regulator-initial-mode
144 };
145
146 vddpx_10:
147 vreg_l2a_1p2: ldo2 {
148 regulator-min-microvol
149 regulator-max-microvol
150 regulator-initial-mode
151 regulator-always-on;
152 };
153
154 vreg_l3a_1p0: ldo3 {
155 regulator-min-microvol
156 regulator-max-microvol
157 regulator-initial-mode
158 };
159
160 vdd_wcss_cx:
161 vdd_wcss_mx:
162 vdda_wcss_pll:
163 vreg_l5a_0p8: ldo5 {
164 regulator-min-microvol
165 regulator-max-microvol
166 regulator-initial-mode
167 };
168
169 vddpx_13:
170 vreg_l6a_1p8: ldo6 {
171 regulator-min-microvol
172 regulator-max-microvol
173 regulator-initial-mode
174 };
175
176 vreg_l7a_1p8: ldo7 {
177 regulator-min-microvol
178 regulator-max-microvol
179 regulator-initial-mode
180 };
181
182 vreg_l8a_1p2: ldo8 {
183 regulator-min-microvol
184 regulator-max-microvol
185 regulator-initial-mode
186 };
187
188 vreg_l9a_1p8: ldo9 {
189 regulator-min-microvol
190 regulator-max-microvol
191 regulator-initial-mode
192 };
193
194 vreg_l10a_1p8: ldo10 {
195 regulator-min-microvol
196 regulator-max-microvol
197 regulator-initial-mode
198 };
199
200 vreg_l11a_1p0: ldo11 {
201 regulator-min-microvol
202 regulator-max-microvol
203 regulator-initial-mode
204 };
205
206 vdd_qfprom:
207 vdd_qfprom_sp:
208 vdda_apc1_cs_1p8:
209 vdda_gfx_cs_1p8:
210 vdda_qrefs_1p8:
211 vdda_qusb_hs0_1p8:
212 vddpx_11:
213 vreg_l12a_1p8: ldo12 {
214 regulator-min-microvol
215 regulator-max-microvol
216 regulator-initial-mode
217 };
218
219 vddpx_2:
220 vreg_l13a_2p95: ldo13 {
221 regulator-min-microvol
222 regulator-max-microvol
223 regulator-initial-mode
224 };
225
226 vreg_l14a_1p88: ldo14 {
227 regulator-min-microvol
228 regulator-max-microvol
229 regulator-initial-mode
230 };
231
232 vreg_l15a_1p8: ldo15 {
233 regulator-min-microvol
234 regulator-max-microvol
235 regulator-initial-mode
236 };
237
238 vreg_l16a_2p7: ldo16 {
239 regulator-min-microvol
240 regulator-max-microvol
241 regulator-initial-mode
242 };
243
244 vreg_l17a_1p3: ldo17 {
245 regulator-min-microvol
246 regulator-max-microvol
247 regulator-initial-mode
248 };
249
250 vreg_l18a_2p7: ldo18 {
251 regulator-min-microvol
252 regulator-max-microvol
253 regulator-initial-mode
254 };
255
256 vreg_l19a_3p0: ldo19 {
257 regulator-min-microvol
258 regulator-max-microvol
259 regulator-initial-mode
260 };
261
262 vreg_l20a_2p95: ldo20 {
263 regulator-min-microvol
264 regulator-max-microvol
265 regulator-initial-mode
266 };
267
268 vreg_l21a_2p95: ldo21 {
269 regulator-min-microvol
270 regulator-max-microvol
271 regulator-initial-mode
272 };
273
274 vreg_l22a_2p85: ldo22 {
275 regulator-min-microvol
276 regulator-max-microvol
277 regulator-initial-mode
278 };
279
280 vreg_l23a_3p3: ldo23 {
281 regulator-min-microvol
282 regulator-max-microvol
283 regulator-initial-mode
284 };
285
286 vdda_qusb_hs0_3p1:
287 vreg_l24a_3p075: ldo24 {
288 regulator-min-microvol
289 regulator-max-microvol
290 regulator-initial-mode
291 };
292
293 vreg_l25a_3p3: ldo25 {
294 regulator-min-microvol
295 regulator-max-microvol
296 regulator-initial-mode
297 };
298
299 vdda_hp_pcie_1p2:
300 vdda_hv_ebi0:
301 vdda_hv_ebi1:
302 vdda_hv_ebi2:
303 vdda_hv_ebi3:
304 vdda_mipi_csi_1p25:
305 vdda_mipi_dsi0_1p2:
306 vdda_mipi_dsi1_1p2:
307 vdda_pcie_1p2:
308 vdda_ufs1_1p2:
309 vdda_ufs2_1p2:
310 vdda_usb1_ss_1p2:
311 vdda_usb2_ss_1p2:
312 vreg_l26a_1p2: ldo26 {
313 regulator-min-microvol
314 regulator-max-microvol
315 regulator-initial-mode
316 };
317
318 vreg_l28a_3p0: ldo28 {
319 regulator-min-microvol
320 regulator-max-microvol
321 regulator-initial-mode
322 };
323
324 vreg_lvs1a_1p8: lvs1 {
325 regulator-min-microvol
326 regulator-max-microvol
327 };
328
329 vreg_lvs2a_1p8: lvs2 {
330 regulator-min-microvol
331 regulator-max-microvol
332 };
333 };
334
335 regulators-1 {
336 compatible = "qcom,pm8005-rpmh
337 qcom,pmic-id = "c";
338
339 vdd-s1-supply = <&vph_pwr>;
340 vdd-s2-supply = <&vph_pwr>;
341 vdd-s3-supply = <&vph_pwr>;
342 vdd-s4-supply = <&vph_pwr>;
343
344 vreg_s3c_0p6: smps3 {
345 regulator-min-microvol
346 regulator-max-microvol
347 };
348 };
349 };
350
351 &gcc {
352 protected-clocks = <GCC_QSPI_CORE_CLK>
353 <GCC_QSPI_CORE
354 <GCC_QSPI_CNOC
355 <GCC_LPASS_Q6_
356 <GCC_LPASS_SWA
357 };
358
359 &i2c10 {
360 clock-frequency = <400000>;
361 status = "okay";
362 };
363
364 &qupv3_id_1 {
365 status = "okay";
366 };
367
368 &uart9 {
369 status = "okay";
370 };
371
372 &ufs_mem_hc {
373 reset-gpios = <&tlmm 150 GPIO_ACTIVE_L
374 vcc-supply = <&vreg_l20a_2p95>;
375 vcc-max-microamp = <600000>;
376 status = "okay";
377 };
378
379 &ufs_mem_phy {
380 vdda-phy-supply = <&vdda_ufs1_core>;
381 vdda-pll-supply = <&vdda_ufs1_1p2>;
382 status = "okay";
383 };
384
385 &sdhc_2 {
386 pinctrl-names = "default";
387 pinctrl-0 = <&sdc2_clk_state &sdc2_cmd
388 cd-gpios = <&tlmm 126 GPIO_ACTIVE_LOW>
389 vmmc-supply = <&vreg_l21a_2p95>;
390 vqmmc-supply = <&vddpx_2>;
391 status = "okay";
392 };
393
394 &usb_1 {
395 status = "okay";
396 };
397
398 &usb_1_dwc3 {
399 /* Until we have Type C hooked up we'l
400 dr_mode = "peripheral";
401 };
402
403 &usb_1_hsphy {
404 vdd-supply = <&vdda_usb1_ss_core>;
405 vdda-pll-supply = <&vdda_qusb_hs0_1p8>
406 vdda-phy-dpdm-supply = <&vdda_qusb_hs0
407
408 qcom,imp-res-offset-value = <8>;
409 qcom,hstx-trim-value = <QUSB2_V2_HSTX_
410 qcom,preemphasis-level = <QUSB2_V2_PRE
411 qcom,preemphasis-width = <QUSB2_V2_PRE
412 status = "okay";
413 };
414
415 &usb_1_qmpphy {
416 vdda-phy-supply = <&vdda_usb1_ss_1p2>;
417 vdda-pll-supply = <&vdda_usb1_ss_core>
418 status = "okay";
419 };
420
421 &wifi {
422 vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>
423 vdd-1.8-xo-supply = <&vreg_l7a_1p8>;
424 vdd-1.3-rfa-supply = <&vreg_l17a_1p3>;
425 vdd-3.3-ch0-supply = <&vreg_l25a_3p3>;
426 status = "okay";
427 };
428
429 &tlmm {
430 gpio-reserved-ranges = <0 4>, <27 4>,
431
432 sdc2_clk_state: sdc2-clk-state {
433 pins = "sdc2_clk";
434 bias-disable;
435
436 /*
437 * It seems that mmc_test repo
438 * strength is not 16 on clk,
439 */
440 drive-strength = <16>;
441 };
442
443 sdc2_cmd_state: sdc2-cmd-state {
444 pins = "sdc2_cmd";
445 bias-pull-up;
446 drive-strength = <16>;
447 };
448
449 sdc2_data_state: sdc2-data-state {
450 pins = "sdc2_data";
451 bias-pull-up;
452 drive-strength = <16>;
453 };
454
455 sd_card_det_n_state: sd-card-det-n-sta
456 pins = "gpio126";
457 function = "gpio";
458 bias-pull-up;
459 };
460 };
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