1 // SPDX-License-Identifier: BSD-3-Clause
2 /*
3 * SDX75 SoC device tree source
4 *
5 * Copyright (c) 2023 Qualcomm Innovation Cent
6 *
7 */
8
9 #include <dt-bindings/clock/qcom,rpmh.h>
10 #include <dt-bindings/clock/qcom,sdx75-gcc.h>
11 #include <dt-bindings/dma/qcom-gpi.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interconnect/qcom,icc.h>
14 #include <dt-bindings/interconnect/qcom,sdx75.
15 #include <dt-bindings/interrupt-controller/arm
16 #include <dt-bindings/mailbox/qcom-ipcc.h>
17 #include <dt-bindings/power/qcom,rpmhpd.h>
18 #include <dt-bindings/power/qcom-rpmpd.h>
19 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
20
21 / {
22 #address-cells = <2>;
23 #size-cells = <2>;
24 interrupt-parent = <&intc>;
25
26 chosen: chosen { };
27
28 clocks {
29 xo_board: xo-board {
30 compatible = "fixed-cl
31 clock-frequency = <768
32 #clock-cells = <0>;
33 };
34
35 sleep_clk: sleep-clk {
36 compatible = "fixed-cl
37 clock-frequency = <320
38 #clock-cells = <0>;
39 };
40 };
41
42 cpus {
43 #address-cells = <2>;
44 #size-cells = <0>;
45
46 CPU0: cpu@0 {
47 device_type = "cpu";
48 compatible = "arm,cort
49 reg = <0x0 0x0>;
50 clocks = <&cpufreq_hw
51 enable-method = "psci"
52 power-domains = <&CPU_
53 power-domain-names = "
54 qcom,freq-domain = <&c
55 capacity-dmips-mhz = <
56 dynamic-power-coeffici
57 next-level-cache = <&L
58
59 L2_0: l2-cache {
60 compatible = "
61 cache-level =
62 cache-unified;
63 next-level-cac
64 L3_0: l3-cache
65 compat
66 cache-
67 cache-
68 };
69 };
70 };
71
72 CPU1: cpu@100 {
73 device_type = "cpu";
74 compatible = "arm,cort
75 reg = <0x0 0x100>;
76 clocks = <&cpufreq_hw
77 enable-method = "psci"
78 power-domains = <&CPU_
79 power-domain-names = "
80 qcom,freq-domain = <&c
81 capacity-dmips-mhz = <
82 dynamic-power-coeffici
83 next-level-cache = <&L
84
85 L2_100: l2-cache {
86 compatible = "
87 cache-level =
88 cache-unified;
89 next-level-cac
90 };
91 };
92
93 CPU2: cpu@200 {
94 device_type = "cpu";
95 compatible = "arm,cort
96 reg = <0x0 0x200>;
97 clocks = <&cpufreq_hw
98 enable-method = "psci"
99 power-domains = <&CPU_
100 power-domain-names = "
101 qcom,freq-domain = <&c
102 capacity-dmips-mhz = <
103 dynamic-power-coeffici
104 next-level-cache = <&L
105
106 L2_200: l2-cache {
107 compatible = "
108 cache-level =
109 cache-unified;
110 next-level-cac
111 };
112 };
113
114 CPU3: cpu@300 {
115 device_type = "cpu";
116 compatible = "arm,cort
117 reg = <0x0 0x300>;
118 clocks = <&cpufreq_hw
119 enable-method = "psci"
120 power-domains = <&CPU_
121 power-domain-names = "
122 qcom,freq-domain = <&c
123 capacity-dmips-mhz = <
124 dynamic-power-coeffici
125 next-level-cache = <&L
126
127 L2_300: l2-cache {
128 compatible = "
129 cache-level =
130 cache-unified;
131 next-level-cac
132 };
133 };
134
135 cpu-map {
136 cluster0 {
137 core0 {
138 cpu =
139 };
140
141 core1 {
142 cpu =
143 };
144
145 core2 {
146 cpu =
147 };
148
149 core3 {
150 cpu =
151 };
152 };
153 };
154
155 idle-states {
156 entry-method = "psci";
157
158 CPU_OFF: cpu-sleep-0 {
159 compatible = "
160 entry-latency-
161 exit-latency-u
162 min-residency-
163 arm,psci-suspe
164 local-timer-st
165 };
166
167 CPU_RAIL_OFF: cpu-rail
168 compatible = "
169 entry-latency-
170 exit-latency-u
171 min-residency-
172 arm,psci-suspe
173 local-timer-st
174 };
175
176 };
177
178 domain-idle-states {
179 CLUSTER_SLEEP_0: clust
180 compatible = "
181 arm,psci-suspe
182 entry-latency-
183 exit-latency-u
184 min-residency-
185 };
186
187 CLUSTER_SLEEP_1: clust
188 compatible = "
189 arm,psci-suspe
190 entry-latency-
191 exit-latency-u
192 min-residency-
193 };
194
195 CLUSTER_SLEEP_2: clust
196 compatible = "
197 arm,psci-suspe
198 entry-latency-
199 exit-latency-u
200 min-residency-
201 };
202 };
203 };
204
205 firmware {
206 scm: scm {
207 compatible = "qcom,scm
208 };
209 };
210
211 clk_virt: interconnect-0 {
212 compatible = "qcom,sdx75-clk-v
213 #interconnect-cells = <2>;
214 qcom,bcm-voters = <&apps_bcm_v
215 clocks = <&rpmhcc RPMH_QPIC_CL
216 };
217
218 mc_virt: interconnect-1 {
219 compatible = "qcom,sdx75-mc-vi
220 #interconnect-cells = <2>;
221 qcom,bcm-voters = <&apps_bcm_v
222 };
223
224 memory@80000000 {
225 device_type = "memory";
226 reg = <0x0 0x80000000 0x0 0x0>
227 };
228
229 pmu {
230 compatible = "arm,cortex-a55-p
231 interrupts = <GIC_PPI 7 IRQ_TY
232 };
233
234 psci {
235 compatible = "arm,psci-1.0";
236 method = "smc";
237
238 CPU_PD0: power-domain-cpu0 {
239 #power-domain-cells =
240 power-domains = <&CLUS
241 domain-idle-states = <
242 };
243
244 CPU_PD1: power-domain-cpu1 {
245 #power-domain-cells =
246 power-domains = <&CLUS
247 domain-idle-states = <
248 };
249
250 CPU_PD2: power-domain-cpu2 {
251 #power-domain-cells =
252 power-domains = <&CLUS
253 domain-idle-states = <
254 };
255
256 CPU_PD3: power-domain-cpu3 {
257 #power-domain-cells =
258 power-domains = <&CLUS
259 domain-idle-states = <
260 };
261
262 CLUSTER_PD: power-domain-cpu-c
263 #power-domain-cells =
264 domain-idle-states = <
265 };
266 };
267
268 reserved-memory {
269 #address-cells = <2>;
270 #size-cells = <2>;
271 ranges;
272
273 gunyah_hyp_mem: gunyah-hyp@800
274 reg = <0x0 0x80000000
275 no-map;
276 };
277
278 hyp_elf_package_mem: hyp-elf-p
279 reg = <0x0 0x80800000
280 no-map;
281 };
282
283 access_control_db_mem: access-
284 reg = <0x0 0x81380000
285 no-map;
286 };
287
288 qteetz_mem: qteetz@814e0000 {
289 reg = <0x0 0x814e0000
290 no-map;
291 };
292
293 trusted_apps_mem: trusted-apps
294 reg = <0x0 0x81780000
295 no-map;
296 };
297
298 xbl_ramdump_mem: xbl-ramdump@8
299 reg = <0x0 0x87a00000
300 no-map;
301 };
302
303 cpucp_fw_mem: cpucp-fw@87c0000
304 reg = <0x0 0x87c00000
305 no-map;
306 };
307
308 xbl_dtlog_mem: xbl-dtlog@87d00
309 reg = <0x0 0x87d00000
310 no-map;
311 };
312
313 xbl_sc_mem: xbl-sc@87d40000 {
314 reg = <0x0 0x87d40000
315 no-map;
316 };
317
318 modem_efs_shared_mem: modem-ef
319 reg = <0x0 0x87d80000
320 no-map;
321 };
322
323 aop_image_mem: aop-image@87e00
324 reg = <0x0 0x87e00000
325 no-map;
326 };
327
328 smem_mem: smem@87e20000 {
329 reg = <0x0 0x87e20000
330 no-map;
331 };
332
333 aop_cmd_db_mem: aop-cmd-db@87e
334 compatible = "qcom,cmd
335 reg = <0x0 0x87ee0000
336 no-map;
337 };
338
339 aop_config_mem: aop-config@87f
340 reg = <0x0 0x87f00000
341 no-map;
342 };
343
344 ipa_fw_mem: ipa-fw@87f20000 {
345 reg = <0x0 0x87f20000
346 no-map;
347 };
348
349 secdata_mem: secdata@87f30000
350 reg = <0x0 0x87f30000
351 no-map;
352 };
353
354 tme_crashdump_mem: tme-crashdu
355 reg = <0x0 0x87f31000
356 no-map;
357 };
358
359 tme_log_mem: tme-log@87f71000
360 reg = <0x0 0x87f71000
361 no-map;
362 };
363
364 uefi_log_mem: uefi-log@87f7500
365 reg = <0x0 0x87f75000
366 no-map;
367 };
368
369 qdss_mem: qdss@88500000 {
370 reg = <0x0 0x88500000
371 no-map;
372 };
373
374 qlink_logging_mem: qlink-loggi
375 reg = <0x0 0x88800000
376 no-map;
377 };
378
379 audio_heap_mem: audio-heap@88b
380 compatible = "shared-d
381 reg = <0x0 0x88b00000
382 no-map;
383 };
384
385 mpss_dsm_mem_2: mpss-dsm-2@88f
386 reg = <0x0 0x88f00000
387 no-map;
388 };
389
390 mpss_dsm_mem: mpss-dsm@8b40000
391 reg = <0x0 0x8b400000
392 no-map;
393 };
394
395 q6_mpss_dtb_mem: q6-mpss-dtb@8
396 reg = <0x0 0x8df80000
397 no-map;
398 };
399
400 mpssadsp_mem: mpssadsp@8e00000
401 reg = <0x0 0x8e000000
402 no-map;
403 };
404
405 gunyah_trace_buffer_mem: gunya
406 reg = <0x0 0xbdb00000
407 no-map;
408 };
409
410 smmu_debug_buf_mem: smmu-debug
411 reg = <0x0 0xbfb00000
412 no-map;
413 };
414
415 hyp_smmu_s2_pt_mem: hyp-smmu-s
416 reg = <0x0 0xbfc00000
417 no-map;
418 };
419 };
420
421 smp2p-modem {
422 compatible = "qcom,smp2p";
423 qcom,smem = <435>, <428>;
424 interrupts-extended = <&ipcc I
425 I
426 I
427 mboxes = <&ipcc IPCC_CLIENT_MP
428 IPCC_MPROC_SIG
429
430 qcom,local-pid = <0>;
431 qcom,remote-pid = <1>;
432
433 smp2p_modem_out: master-kernel
434 qcom,entry-name = "mas
435 #qcom,smem-state-cells
436 };
437
438 smp2p_modem_in: slave-kernel {
439 qcom,entry-name = "sla
440 interrupt-controller;
441 #interrupt-cells = <2>
442 };
443
444 ipa_smp2p_out: ipa-ap-to-modem
445 qcom,entry-name = "ipa
446 #qcom,smem-state-cells
447 };
448
449 ipa_smp2p_in: ipa-modem-to-ap
450 qcom,entry-name = "ipa
451 interrupt-controller;
452 #interrupt-cells = <2>
453 };
454 };
455
456 smem: smem {
457 compatible = "qcom,smem";
458 memory-region = <&smem_mem>;
459 hwlocks = <&tcsr_mutex 3>;
460 };
461
462 soc: soc@0 {
463 compatible = "simple-bus";
464 #address-cells = <2>;
465 #size-cells = <2>;
466 ranges = <0 0 0 0 0x10 0>;
467 dma-ranges = <0 0 0 0 0x10 0>;
468
469 gcc: clock-controller@80000 {
470 compatible = "qcom,sdx
471 reg = <0x0 0x0080000 0
472 clocks = <&rpmhcc RPMH
473 <&sleep_clk>,
474 <0>,
475 <0>,
476 <0>,
477 <0>,
478 <0>,
479 <0>,
480 <0>,
481 <0>,
482 <0>,
483 <0>,
484 <0>,
485 <0>,
486 <0>;
487 #clock-cells = <1>;
488 #reset-cells = <1>;
489 #power-domain-cells =
490 };
491
492 ipcc: mailbox@408000 {
493 compatible = "qcom,sdx
494 reg = <0 0x00408000 0
495 interrupts = <GIC_SPI
496 interrupt-controller;
497 #interrupt-cells = <3>
498 #mbox-cells = <2>;
499 };
500
501 gpi_dma: dma-controller@900000
502 compatible = "qcom,sdx
503 reg = <0x0 0x00900000
504 #dma-cells = <3>;
505 interrupts = <GIC_SPI
506 <GIC_SPI
507 <GIC_SPI
508 <GIC_SPI
509 <GIC_SPI
510 <GIC_SPI
511 <GIC_SPI
512 <GIC_SPI
513 <GIC_SPI
514 <GIC_SPI
515 <GIC_SPI
516 <GIC_SPI
517 dma-channels = <12>;
518 dma-channel-mask = <0x
519 iommus = <&apps_smmu 0
520 status = "disabled";
521 };
522
523 qupv3_id_0: geniqup@9c0000 {
524 compatible = "qcom,gen
525 reg = <0x0 0x009c0000
526 clocks = <&gcc GCC_QUP
527 <&gcc GCC_QUP
528 clock-names = "m-ahb",
529 "s-ahb";
530 iommus = <&apps_smmu 0
531 interconnects = <&clk_
532 &clk_
533 interconnect-names = "
534 #address-cells = <2>;
535 #size-cells = <2>;
536 ranges;
537 status = "disabled";
538
539 i2c0: i2c@980000 {
540 compatible = "
541 reg = <0x0 0x0
542 clocks = <&gcc
543 clock-names =
544 interrupts = <
545 #address-cells
546 #size-cells =
547 pinctrl-0 = <&
548 pinctrl-names
549 interconnects
550
551
552
553
554
555 interconnect-n
556 dmas = <&gpi_d
557 <&gpi_d
558 dma-names = "t
559 status = "disa
560 };
561
562 spi0: spi@980000 {
563 compatible = "
564 reg = <0x0 0x0
565 clocks = <&gcc
566 clock-names =
567 interrupts = <
568 #address-cells
569 #size-cells =
570 pinctrl-0 = <&
571 pinctrl-names
572 interconnects
573
574
575
576
577
578 interconnect-n
579 dmas = <&gpi_d
580 <&gpi_d
581 dma-names = "t
582 status = "disa
583 };
584
585 uart1: serial@984000 {
586 compatible = "
587 reg = <0x0 0x0
588 clocks = <&gcc
589 clock-names =
590 interconnects
591
592
593
594 interconnect-n
595
596 interrupts = <
597 pinctrl-0 = <&
598 pinctrl-1 = <&
599 pinctrl-names
600
601 status = "disa
602 };
603
604 i2c2: i2c@988000 {
605 compatible = "
606 reg = <0x0 0x0
607 clocks = <&gcc
608 clock-names =
609 interrupts = <
610 #address-cells
611 #size-cells =
612 pinctrl-0 = <&
613 pinctrl-names
614 interconnects
615
616
617
618
619
620 interconnect-n
621 dmas = <&gpi_d
622 <&gpi_d
623 dma-names = "t
624 status = "disa
625 };
626
627 spi2: spi@988000 {
628 compatible = "
629 reg = <0x0 0x0
630 clocks = <&gcc
631 clock-names =
632 interrupts = <
633 #address-cells
634 #size-cells =
635 pinctrl-0 = <&
636 pinctrl-names
637 interconnects
638
639
640
641
642
643 interconnect-n
644 dmas = <&gpi_d
645 <&gpi_d
646 dma-names = "t
647 status = "disa
648 };
649
650 i2c3: i2c@98c000 {
651 compatible = "
652 reg = <0x0 0x0
653 clocks = <&gcc
654 clock-names =
655 interrupts = <
656 #address-cells
657 #size-cells =
658 pinctrl-0 = <&
659 pinctrl-names
660 interconnects
661
662
663
664
665
666 interconnect-n
667 dmas = <&gpi_d
668 <&gpi_d
669 dma-names = "t
670 status = "disa
671 };
672
673 spi3: spi@98c000 {
674 compatible = "
675 reg = <0x0 0x0
676 clocks = <&gcc
677 clock-names =
678 interrupts = <
679 #address-cells
680 #size-cells =
681 pinctrl-0 = <&
682 pinctrl-names
683 interconnects
684
685
686
687
688
689 interconnect-n
690 dmas = <&gpi_d
691 <&gpi_d
692 dma-names = "t
693 status = "disa
694 };
695
696 uart4: serial@990000 {
697 compatible = "
698 reg = <0x0 0x0
699 clocks = <&gcc
700 clock-names =
701 interrupts = <
702 pinctrl-0 = <&
703 pinctrl-names
704 interconnects
705
706
707
708 interconnect-n
709 status = "disa
710 };
711
712 i2c5: i2c@994000 {
713 compatible = "
714 reg = <0x0 0x0
715 clocks = <&gcc
716 clock-names =
717 interrupts = <
718 #address-cells
719 #size-cells =
720 pinctrl-0 = <&
721 pinctrl-names
722 interconnects
723
724
725
726
727
728 interconnect-n
729 dmas = <&gpi_d
730 <&gpi_d
731 dma-names = "t
732 status = "disa
733 };
734
735 i2c6: i2c@998000 {
736 compatible = "
737 reg = <0x0 0x0
738 clocks = <&gcc
739 clock-names =
740 interrupts = <
741 #address-cells
742 #size-cells =
743 pinctrl-0 = <&
744 pinctrl-names
745 interconnects
746
747
748
749
750
751 interconnect-n
752 dmas = <&gpi_d
753 <&gpi_d
754 dma-names = "t
755 status = "disa
756 };
757
758 spi6: spi@998000 {
759 compatible = "
760 reg = <0x0 0x0
761 clocks = <&gcc
762 clock-names =
763 interrupts = <
764 #address-cells
765 #size-cells =
766 pinctrl-0 = <&
767 pinctrl-names
768 interconnects
769
770
771
772
773
774 interconnect-n
775 dmas = <&gpi_d
776 <&gpi_d
777 dma-names = "t
778 status = "disa
779 };
780
781 i2c7: i2c@99c000 {
782 compatible = "
783 reg = <0x0 0x0
784 clocks = <&gcc
785 clock-names =
786 interrupts = <
787 #address-cells
788 #size-cells =
789 pinctrl-0 = <&
790 pinctrl-names
791 interconnects
792
793
794
795
796
797 interconnect-n
798 dmas = <&gpi_d
799 <&gpi_d
800 dma-names = "t
801 status = "disa
802 };
803
804 spi7: spi@99c000 {
805 compatible = "
806 reg = <0x0 0x0
807 clocks = <&gcc
808 clock-names =
809 interrupts = <
810 #address-cells
811 #size-cells =
812 pinctrl-0 = <&
813 pinctrl-names
814 interconnects
815
816
817
818
819
820 interconnect-n
821 dmas = <&gpi_d
822 <&gpi_d
823 dma-names = "t
824 status = "disa
825 };
826 };
827
828 usb_hsphy: phy@ff4000 {
829 compatible = "qcom,sdx
830 reg = <0x0 0x00ff4000
831 #phy-cells = <0>;
832
833 clocks = <&rpmhcc RPMH
834 clock-names = "ref";
835
836 resets = <&gcc GCC_QUS
837
838 status = "disabled";
839 };
840
841 usb_qmpphy: phy@ff6000 {
842 compatible = "qcom,sdx
843 reg = <0x0 0x00ff6000
844
845 clocks = <&gcc GCC_USB
846 <&gcc GCC_USB
847 <&gcc GCC_USB
848 <&gcc GCC_USB
849 clock-names = "aux",
850 "ref",
851 "cfg_ahb
852 "pipe";
853
854 power-domains = <&gcc
855
856 resets = <&gcc GCC_USB
857 <&gcc GCC_USB
858 reset-names = "phy",
859 "phy_phy
860
861 #clock-cells = <0>;
862 clock-output-names = "
863
864 #phy-cells = <0>;
865
866 status = "disabled";
867 };
868
869 system_noc: interconnect@16400
870 compatible = "qcom,sdx
871 reg = <0x0 0x01640000
872 #interconnect-cells =
873 qcom,bcm-voters = <&ap
874 };
875
876 pcie_anoc: interconnect@16c000
877 compatible = "qcom,sdx
878 reg = <0x0 0x016c0000
879 #interconnect-cells =
880 qcom,bcm-voters = <&ap
881 };
882
883 tcsr_mutex: hwlock@1f40000 {
884 compatible = "qcom,tcs
885 reg = <0x0 0x01f40000
886 #hwlock-cells = <1>;
887 };
888
889 tcsr: syscon@1fc0000 {
890 compatible = "qcom,sdx
891 reg = <0x0 0x01fc0000
892 };
893
894 remoteproc_mpss: remoteproc@40
895 compatible = "qcom,sdx
896 reg = <0 0x04080000 0
897
898 interrupts-extended =
899
900
901
902
903
904 interrupt-names = "wdo
905 "fat
906 "rea
907 "han
908 "sto
909 "shu
910
911 clocks = <&rpmhcc RPMH
912 clock-names = "xo";
913
914 power-domains = <&rpmh
915 <&rpmh
916 power-domain-names = "
917 "
918
919 memory-region = <&mpss
920 <&mpss
921 <&qlin
922
923 qcom,qmp = <&aoss_qmp>
924
925 qcom,smem-states = <&s
926 qcom,smem-state-names
927
928 status = "disabled";
929
930 glink-edge {
931 interrupts-ext
932
933
934 mboxes = <&ipc
935
936 label = "mpss"
937 qcom,remote-pi
938 };
939 };
940
941 sdhc: mmc@8804000 {
942 compatible = "qcom,sdx
943 reg = <0x0 0x08804000
944
945 interrupts = <GIC_SPI
946 <GIC_SPI
947 interrupt-names = "hc_
948 "pwr
949
950 clocks = <&gcc GCC_SDC
951 <&gcc GCC_SDC
952 <&rpmhcc RPMH
953 clock-names = "iface",
954 "core",
955 "xo";
956 iommus = <&apps_smmu 0
957 qcom,dll-config = <0x0
958 qcom,ddr-config = <0x8
959 power-domains = <&rpmh
960 operating-points-v2 =
961
962 interconnects = <&syst
963 <&gem_
964 interconnect-names = "
965 "
966 bus-width = <4>;
967 dma-coherent;
968
969 /* Forbid SDR104/SDR50
970 sdhci-caps-mask = <0x3
971
972 status = "disabled";
973
974 sdhc1_opp_table: opp-t
975 compatible = "
976
977 opp-100000000
978 opp-hz
979 requir
980 };
981
982 opp-384000000
983 opp-hz
984 requir
985 };
986 };
987 };
988
989 usb: usb@a6f8800 {
990 compatible = "qcom,sdx
991 reg = <0x0 0x0a6f8800
992 #address-cells = <2>;
993 #size-cells = <2>;
994 ranges;
995
996 clocks = <&gcc GCC_USB
997 <&gcc GCC_USB
998 <&gcc GCC_USB
999 <&gcc GCC_USB
1000 <&gcc GCC_US
1001 clock-names = "cfg_no
1002 "core",
1003 "iface"
1004 "sleep"
1005 "mock_u
1006
1007 assigned-clocks = <&g
1008 <&g
1009 assigned-clock-rates
1010
1011 interrupts-extended =
1012
1013
1014
1015 interrupt-names = "hs
1016 "ss
1017 "dm
1018 "dp
1019
1020 power-domains = <&gcc
1021
1022 resets = <&gcc GCC_US
1023
1024 interconnects = <&sys
1025 &mc_
1026 <&gem
1027 &sys
1028 interconnect-names =
1029
1030
1031 status = "disabled";
1032
1033 usb_dwc3: usb@a600000
1034 compatible =
1035 reg = <0x0 0x
1036 interrupts =
1037 iommus = <&ap
1038 snps,dis_u2_s
1039 snps,dis_enbl
1040 phys = <&usb_
1041 <&usb_
1042 phy-names = "
1043 "
1044
1045 ports {
1046 #addr
1047 #size
1048
1049 port@
1050
1051
1052
1053
1054 };
1055
1056 port@
1057
1058
1059
1060
1061 };
1062 };
1063 };
1064 };
1065
1066 pdc: interrupt-controller@b22
1067 compatible = "qcom,sd
1068 reg = <0x0 0xb220000
1069 <0x0 0x174000f0
1070 qcom,pdc-ranges = <0
1071 <52
1072 <84
1073 #interrupt-cells = <2
1074 interrupt-parent = <&
1075 interrupt-controller;
1076 };
1077
1078 aoss_qmp: power-controller@c3
1079 compatible = "qcom,sd
1080 reg = <0 0x0c310000 0
1081 interrupt-parent = <&
1082 interrupts-extended =
1083
1084 mboxes = <&ipcc IPCC_
1085
1086 #clock-cells = <0>;
1087 };
1088
1089 spmi_bus: spmi@c400000 {
1090 compatible = "qcom,sp
1091 reg = <0x0 0x0c400000
1092 <0x0 0x0c500000
1093 <0x0 0x0c440000
1094 <0x0 0x0c4c0000
1095 <0x0 0x0c42d000
1096 reg-names = "core",
1097 "chnls",
1098 "obsrvr",
1099 "intr",
1100 "cnfg";
1101 interrupts-extended =
1102 interrupt-names = "pe
1103 qcom,ee = <0>;
1104 qcom,channel = <0>;
1105 qcom,bus-id = <0>;
1106 #address-cells = <2>;
1107 #size-cells = <0>;
1108 interrupt-controller;
1109 #interrupt-cells = <4
1110 };
1111
1112 tlmm: pinctrl@f000000 {
1113 compatible = "qcom,sd
1114 reg = <0x0 0x0f000000
1115 interrupts = <GIC_SPI
1116 gpio-controller;
1117 #gpio-cells = <2>;
1118 gpio-ranges = <&tlmm
1119 interrupt-controller;
1120 #interrupt-cells = <2
1121 wakeup-parent = <&pdc
1122
1123 qup_i2c0_data_clk: qu
1124 /* SDA, SCL *
1125 pins = "gpio8
1126 function = "q
1127 drive-strengt
1128 bias-pull-up;
1129 };
1130
1131 qup_i2c2_data_clk: qu
1132 /* SDA, SCL *
1133 pins = "gpio1
1134 function = "q
1135 drive-strengt
1136 bias-pull-up;
1137 };
1138
1139 qup_i2c3_data_clk: qu
1140 /* SDA, SCL *
1141 pins = "gpio5
1142 function = "q
1143 drive-strengt
1144 bias-pull-up;
1145 };
1146
1147 qup_i2c5_data_clk: qu
1148 /* SDA, SCL *
1149 pins = "gpio1
1150 function = "q
1151 drive-strengt
1152 bias-pull-up;
1153 };
1154
1155 qup_i2c6_data_clk: qu
1156 /* SDA, SCL *
1157 pins = "gpio1
1158 function = "q
1159 drive-strengt
1160 bias-pull-up;
1161 };
1162
1163 qup_i2c7_data_clk: qu
1164 /* SDA, SCL *
1165 pins = "gpio1
1166 function = "q
1167 drive-strengt
1168 bias-pull-up;
1169 };
1170
1171 qup_spi0_cs: qup-spi0
1172 pins = "gpio1
1173 function = "q
1174 drive-strengt
1175 bias-pull-dow
1176 };
1177
1178 qup_spi0_data_clk: qu
1179 /* MISO, MOSI
1180 pins = "gpio8
1181 function = "q
1182 drive-strengt
1183 bias-pull-dow
1184 };
1185
1186 qup_spi2_cs: qup-spi2
1187 pins = "gpio1
1188 function = "q
1189 drive-strengt
1190 bias-pull-dow
1191 };
1192
1193 qup_spi2_data_clk: qu
1194 /* MISO, MOSI
1195 pins = "gpio1
1196 function = "q
1197 drive-strengt
1198 bias-pull-dow
1199 };
1200
1201 qup_spi3_cs: qup-spi3
1202 pins = "gpio5
1203 function = "q
1204 drive-strengt
1205 bias-pull-dow
1206 };
1207
1208 qup_spi3_data_clk: qu
1209 /* MISO, MOSI
1210 pins = "gpio5
1211 function = "q
1212 drive-strengt
1213 bias-pull-dow
1214 };
1215
1216 qup_spi6_cs: qup-spi6
1217 pins = "gpio1
1218 function = "q
1219 drive-strengt
1220 bias-pull-dow
1221 };
1222
1223 qup_spi6_data_clk: qu
1224 /* MISO, MOSI
1225 pins = "gpio1
1226 function = "q
1227 drive-strengt
1228 bias-pull-dow
1229 };
1230
1231 qup_spi7_cs: qup-spi7
1232 pins = "gpio1
1233 function = "q
1234 drive-strengt
1235 bias-pull-dow
1236 };
1237
1238 qup_spi7_data_clk: qu
1239 /* MISO, MOSI
1240 pins = "gpio1
1241 function = "q
1242 drive-strengt
1243 bias-pull-dow
1244 };
1245
1246 qup_uart4_cts_rts: qu
1247 /* CTS, RTS *
1248 pins = "gpio5
1249 function = "q
1250 drive-strengt
1251 bias-pull-dow
1252 };
1253
1254 qup_uart4_default: qu
1255 /* TX, RX */
1256 pins = "gpio5
1257 function = "q
1258 drive-strengt
1259 bias-pull-up;
1260 };
1261
1262 qupv3_se1_2uart_activ
1263 tx-pins {
1264 pins
1265 funct
1266 drive
1267 bias-
1268 };
1269
1270 rx-pins {
1271 pins
1272 funct
1273 drive
1274 bias-
1275 };
1276 };
1277
1278 qupv3_se1_2uart_sleep
1279 pins = "gpio1
1280 function = "g
1281 drive-strengt
1282 bias-pull-dow
1283 };
1284
1285 sdc1_default: sdc1-de
1286 clk-pins {
1287 pins
1288 drive
1289 bias-
1290 };
1291
1292 cmd-pins {
1293 pins
1294 drive
1295 bias-
1296 };
1297
1298 data-pins {
1299 pins
1300 drive
1301 bias-
1302 };
1303 };
1304
1305 sdc1_sleep: sdc1-slee
1306 clk-pins {
1307 pins
1308 drive
1309 bias-
1310 };
1311
1312 cmd-pins {
1313 pins
1314 drive
1315 bias-
1316 };
1317
1318 data-pins {
1319 pins
1320 drive
1321 bias-
1322 };
1323 };
1324 };
1325
1326 apps_smmu: iommu@15000000 {
1327 compatible = "qcom,sd
1328 reg = <0x0 0x15000000
1329 #iommu-cells = <2>;
1330 #global-interrupts =
1331 dma-coherent;
1332 interrupts = <GIC_SPI
1333 <GIC_SPI
1334 <GIC_SPI
1335 <GIC_SPI
1336 <GIC_SPI
1337 <GIC_SPI
1338 <GIC_SPI
1339 <GIC_SPI
1340 <GIC_SPI
1341 <GIC_SPI
1342 <GIC_SPI
1343 <GIC_SPI
1344 <GIC_SPI
1345 <GIC_SPI
1346 <GIC_SPI
1347 <GIC_SPI
1348 <GIC_SPI
1349 <GIC_SPI
1350 <GIC_SPI
1351 <GIC_SPI
1352 <GIC_SPI
1353 <GIC_SPI
1354 <GIC_SPI
1355 <GIC_SPI
1356 <GIC_SPI
1357 <GIC_SPI
1358 <GIC_SPI
1359 <GIC_SPI
1360 <GIC_SPI
1361 <GIC_SPI
1362 <GIC_SPI
1363 <GIC_SPI
1364 <GIC_SPI
1365 };
1366
1367 intc: interrupt-controller@17
1368 compatible = "arm,gic
1369 #interrupt-cells = <3
1370 interrupt-controller;
1371 #redistributor-region
1372 redistributor-stride
1373 reg = <0x0 0x17200000
1374 <0x0 0x17260000
1375 interrupts = <GIC_PPI
1376 };
1377
1378 timer@17420000 {
1379 compatible = "arm,arm
1380 reg = <0x0 0x17420000
1381 #address-cells = <1>;
1382 #size-cells = <1>;
1383 ranges = <0 0 0 0x200
1384
1385 frame@17421000 {
1386 reg = <0x1742
1387 <0x1742
1388 frame-number
1389 interrupts =
1390
1391 };
1392
1393 frame@17423000 {
1394 reg = <0x1742
1395 frame-number
1396 interrupts =
1397 status = "dis
1398 };
1399
1400 frame@17425000 {
1401 reg = <0x1742
1402 frame-number
1403 interrupts =
1404 status = "dis
1405 };
1406
1407 frame@17427000 {
1408 reg = <0x1742
1409 frame-number
1410 interrupts =
1411 status = "dis
1412 };
1413
1414 frame@17429000 {
1415 reg = <0x1742
1416 frame-number
1417 interrupts =
1418 status = "dis
1419 };
1420
1421 frame@1742b000 {
1422 reg = <0x1742
1423 frame-number
1424 interrupts =
1425 status = "dis
1426 };
1427
1428 frame@1742d000 {
1429 reg = <0x1742
1430 frame-number
1431 interrupts =
1432 status = "dis
1433 };
1434 };
1435
1436 apps_rsc: rsc@17a00000 {
1437 label = "apps_rsc";
1438 compatible = "qcom,rp
1439 reg = <0x0 0x17a00000
1440 <0x0 0x17a10000
1441 <0x0 0x17a20000
1442 reg-names = "drv-0",
1443 interrupts = <GIC_SPI
1444 <GIC_SPI
1445 <GIC_SPI
1446
1447 power-domains = <&CLU
1448 qcom,tcs-offset = <0x
1449 qcom,drv-id = <2>;
1450 qcom,tcs-config = <AC
1451 <SL
1452 <WA
1453 <CO
1454
1455 apps_bcm_voter: bcm-v
1456 compatible =
1457 };
1458
1459 rpmhcc: clock-control
1460 compatible =
1461 clocks = <&xo
1462 clock-names =
1463 #clock-cells
1464 };
1465
1466 rpmhpd: power-control
1467 compatible =
1468 #power-domain
1469 operating-poi
1470
1471 rpmhpd_opp_ta
1472 compa
1473
1474 rpmhp
1475
1476 };
1477
1478 rpmhp
1479
1480 };
1481
1482 rpmhp
1483
1484 };
1485
1486 rpmhp
1487
1488 };
1489
1490 rpmhp
1491
1492 };
1493
1494 rpmhp
1495
1496 };
1497
1498 rpmhp
1499
1500 };
1501
1502 rpmhp
1503
1504 };
1505
1506 rpmhp
1507
1508 };
1509
1510 rpmhp
1511
1512 };
1513 };
1514 };
1515 };
1516
1517 cpufreq_hw: cpufreq@17d91000
1518 compatible = "qcom,sd
1519 reg = <0x0 0x17d91000
1520 reg-names = "freq-dom
1521 clocks = <&rpmhcc RPM
1522 <&gcc GPLL0>
1523 clock-names = "xo",
1524 "altern
1525 interrupts = <GIC_SPI
1526 interrupt-names = "dc
1527 #freq-domain-cells =
1528 #clock-cells = <1>;
1529 };
1530
1531 dc_noc: interconnect@190e0000
1532 compatible = "qcom,sd
1533 reg = <0x0 0x190e0000
1534 #interconnect-cells =
1535 qcom,bcm-voters = <&a
1536 };
1537
1538 gem_noc: interconnect@1910000
1539 compatible = "qcom,sd
1540 reg = <0x0 0x19100000
1541 #interconnect-cells =
1542 qcom,bcm-voters = <&a
1543 };
1544 };
1545
1546 timer {
1547 compatible = "arm,armv8-timer
1548 interrupts = <GIC_PPI 13 (GIC
1549 <GIC_PPI 14 (GIC
1550 <GIC_PPI 11 (GIC
1551 <GIC_PPI 12 (GIC
1552 };
1553 };
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