1 // SPDX-License-Identifier: BSD-3-Clause
2 /*
3 * Copyright (c) 2023, Qualcomm Innovation Cen
4 */
5
6 #include <dt-bindings/clock/qcom,rpmh.h>
7 #include <dt-bindings/clock/qcom,sm4450-gcc.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm
10 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
11
12 / {
13 interrupt-parent = <&intc>;
14
15 #address-cells = <2>;
16 #size-cells = <2>;
17
18 chosen { };
19
20 clocks {
21 xo_board: xo-board {
22 compatible = "fixed-cl
23 clock-frequency = <768
24 #clock-cells = <0>;
25 };
26
27 sleep_clk: sleep-clk {
28 compatible = "fixed-cl
29 clock-frequency = <320
30 #clock-cells = <0>;
31 };
32
33 bi_tcxo_div2: bi-tcxo-div2-clk
34 #clock-cells = <0>;
35 compatible = "fixed-fa
36 clocks = <&rpmhcc RPMH
37 clock-mult = <1>;
38 clock-div = <2>;
39 };
40 };
41
42 cpus {
43 #address-cells = <2>;
44 #size-cells = <0>;
45
46 CPU0: cpu@0 {
47 device_type = "cpu";
48 compatible = "arm,cort
49 reg = <0x0 0x0>;
50 clocks = <&cpufreq_hw
51 enable-method = "psci"
52 next-level-cache = <&L
53 power-domains = <&CPU_
54 power-domain-names = "
55 qcom,freq-domain = <&c
56 #cooling-cells = <2>;
57
58 L2_0: l2-cache {
59 compatible = "
60 cache-level =
61 cache-unified;
62 next-level-cac
63
64 L3_0: l3-cache
65 compat
66 cache-
67 cache-
68 };
69 };
70 };
71
72 CPU1: cpu@100 {
73 device_type = "cpu";
74 compatible = "arm,cort
75 reg = <0x0 0x100>;
76 clocks = <&cpufreq_hw
77 enable-method = "psci"
78 next-level-cache = <&L
79 power-domains = <&CPU_
80 power-domain-names = "
81 qcom,freq-domain = <&c
82 #cooling-cells = <2>;
83
84 L2_100: l2-cache {
85 compatible = "
86 cache-level =
87 cache-unified;
88 next-level-cac
89 };
90 };
91
92 CPU2: cpu@200 {
93 device_type = "cpu";
94 compatible = "arm,cort
95 reg = <0x0 0x200>;
96 clocks = <&cpufreq_hw
97 enable-method = "psci"
98 next-level-cache = <&L
99 power-domains = <&CPU_
100 power-domain-names = "
101 qcom,freq-domain = <&c
102 #cooling-cells = <2>;
103
104 L2_200: l2-cache {
105 compatible = "
106 cache-level =
107 cache-unified;
108 next-level-cac
109 };
110 };
111
112 CPU3: cpu@300 {
113 device_type = "cpu";
114 compatible = "arm,cort
115 reg = <0x0 0x300>;
116 clocks = <&cpufreq_hw
117 enable-method = "psci"
118 next-level-cache = <&L
119 power-domains = <&CPU_
120 power-domain-names = "
121 qcom,freq-domain = <&c
122 #cooling-cells = <2>;
123
124 L2_300: l2-cache {
125 compatible = "
126 cache-level =
127 cache-unified;
128 next-level-cac
129 };
130 };
131
132 CPU4: cpu@400 {
133 device_type = "cpu";
134 compatible = "arm,cort
135 reg = <0x0 0x400>;
136 clocks = <&cpufreq_hw
137 enable-method = "psci"
138 next-level-cache = <&L
139 power-domains = <&CPU_
140 power-domain-names = "
141 qcom,freq-domain = <&c
142 #cooling-cells = <2>;
143
144 L2_400: l2-cache {
145 compatible = "
146 cache-level =
147 cache-unified;
148 next-level-cac
149 };
150 };
151
152 CPU5: cpu@500 {
153 device_type = "cpu";
154 compatible = "arm,cort
155 reg = <0x0 0x500>;
156 clocks = <&cpufreq_hw
157 enable-method = "psci"
158 next-level-cache = <&L
159 power-domains = <&CPU_
160 power-domain-names = "
161 qcom,freq-domain = <&c
162 #cooling-cells = <2>;
163
164 L2_500: l2-cache {
165 compatible = "
166 cache-level =
167 cache-unified;
168 next-level-cac
169 };
170 };
171
172 CPU6: cpu@600 {
173 device_type = "cpu";
174 compatible = "arm,cort
175 reg = <0x0 0x600>;
176 clocks = <&cpufreq_hw
177 enable-method = "psci"
178 next-level-cache = <&L
179 power-domains = <&CPU_
180 power-domain-names = "
181 qcom,freq-domain = <&c
182 #cooling-cells = <2>;
183
184 L2_600: l2-cache {
185 compatible = "
186 cache-level =
187 cache-unified;
188 next-level-cac
189 };
190 };
191
192 CPU7: cpu@700 {
193 device_type = "cpu";
194 compatible = "arm,cort
195 reg = <0x0 0x700>;
196 clocks = <&cpufreq_hw
197 enable-method = "psci"
198 next-level-cache = <&L
199 power-domains = <&CPU_
200 power-domain-names = "
201 qcom,freq-domain = <&c
202 #cooling-cells = <2>;
203
204 L2_700: l2-cache {
205 compatible = "
206 cache-level =
207 cache-unified;
208 next-level-cac
209 };
210 };
211
212 cpu-map {
213 cluster0 {
214 core0 {
215 cpu =
216 };
217
218 core1 {
219 cpu =
220 };
221
222 core2 {
223 cpu =
224 };
225
226 core3 {
227 cpu =
228 };
229
230 core4 {
231 cpu =
232 };
233
234 core5 {
235 cpu =
236 };
237
238 core6 {
239 cpu =
240 };
241
242 core7 {
243 cpu =
244 };
245 };
246 };
247
248 idle-states {
249 entry-method = "psci";
250
251 LITTLE_CPU_SLEEP_0: cp
252 compatible = "
253 arm,psci-suspe
254 entry-latency-
255 exit-latency-u
256 min-residency-
257 local-timer-st
258 };
259
260 BIG_CPU_SLEEP_0: cpu-s
261 compatible = "
262 arm,psci-suspe
263 entry-latency-
264 exit-latency-u
265 min-residency-
266 local-timer-st
267 };
268 };
269
270 domain-idle-states {
271 CLUSTER_SLEEP_0: clust
272 compatible = "
273 arm,psci-suspe
274 entry-latency-
275 exit-latency-u
276 min-residency-
277 };
278
279 CLUSTER_SLEEP_1: clust
280 compatible = "
281 arm,psci-suspe
282 entry-latency-
283 exit-latency-u
284 min-residency-
285 };
286 };
287 };
288
289 memory@a0000000 {
290 device_type = "memory";
291 /* We expect the bootloader to
292 reg = <0x0 0xa0000000 0x0 0x0>
293 };
294
295 pmu-a55 {
296 compatible = "arm,cortex-a55-p
297 interrupts = <GIC_PPI 7 IRQ_TY
298 };
299
300 pmu-a78 {
301 compatible = "arm,cortex-a78-p
302 interrupts = <GIC_PPI 7 IRQ_TY
303 };
304
305 psci {
306 compatible = "arm,psci-1.0";
307 method = "smc";
308
309 CPU_PD0: power-domain-cpu0 {
310 #power-domain-cells =
311 power-domains = <&CLUS
312 domain-idle-states = <
313 };
314
315 CPU_PD1: power-domain-cpu1 {
316 #power-domain-cells =
317 power-domains = <&CLUS
318 domain-idle-states = <
319 };
320
321 CPU_PD2: power-domain-cpu2 {
322 #power-domain-cells =
323 power-domains = <&CLUS
324 domain-idle-states = <
325 };
326
327 CPU_PD3: power-domain-cpu3 {
328 #power-domain-cells =
329 power-domains = <&CLUS
330 domain-idle-states = <
331 };
332
333 CPU_PD4: power-domain-cpu4 {
334 #power-domain-cells =
335 power-domains = <&CLUS
336 domain-idle-states = <
337 };
338
339 CPU_PD5: power-domain-cpu5 {
340 #power-domain-cells =
341 power-domains = <&CLUS
342 domain-idle-states = <
343 };
344
345 CPU_PD6: power-domain-cpu6 {
346 #power-domain-cells =
347 power-domains = <&CLUS
348 domain-idle-states = <
349 };
350
351 CPU_PD7: power-domain-cpu7 {
352 #power-domain-cells =
353 power-domains = <&CLUS
354 domain-idle-states = <
355 };
356
357 CLUSTER_PD: power-domain-cpu-c
358 #power-domain-cells =
359 domain-idle-states = <
360 };
361 };
362
363 reserved_memory: reserved-memory {
364 #address-cells = <2>;
365 #size-cells = <2>;
366 ranges;
367
368 aop_cmd_db_mem: cmd-db@8086000
369 compatible = "qcom,cmd
370 reg = <0x0 0x80860000
371 no-map;
372 };
373 };
374
375 soc: soc@0 {
376 #address-cells = <2>;
377 #size-cells = <2>;
378 ranges = <0 0 0 0 0x10 0>;
379 dma-ranges = <0 0 0 0 0x10 0>;
380 compatible = "simple-bus";
381
382 gcc: clock-controller@100000 {
383 compatible = "qcom,sm4
384 reg = <0x0 0x00100000
385 #clock-cells = <1>;
386 #reset-cells = <1>;
387 #power-domain-cells =
388 clocks = <&rpmhcc RPMH
389 <&sleep_clk>,
390 <0>,
391 <0>,
392 <0>,
393 <0>;
394 };
395
396 qupv3_id_0: geniqup@ac0000 {
397 compatible = "qcom,gen
398 reg = <0x0 0x00ac0000
399 ranges;
400 clocks = <&gcc GCC_QUP
401 <&gcc GCC_QUP
402 clock-names = "m-ahb",
403 #address-cells = <2>;
404 #size-cells = <2>;
405 status = "disabled";
406
407 uart7: serial@a88000 {
408 compatible = "
409 reg = <0x0 0x0
410 clocks = <&gcc
411 clock-names =
412 interrupts = <
413 pinctrl-0 = <&
414 pinctrl-names
415 status = "disa
416 };
417 };
418
419 tcsr_mutex: hwlock@1f40000 {
420 compatible = "qcom,tcs
421 reg = <0x0 0x01f40000
422 #hwlock-cells = <1>;
423 };
424
425 pdc: interrupt-controller@b220
426 compatible = "qcom,sm4
427 reg = <0 0x0b220000 0
428 qcom,pdc-ranges = <0 4
429 <125
430 #interrupt-cells = <2>
431 interrupt-parent = <&i
432 interrupt-controller;
433 };
434
435 tlmm: pinctrl@f100000 {
436 compatible = "qcom,sm4
437 reg = <0x0 0x0f100000
438 interrupts = <GIC_SPI
439 gpio-controller;
440 #gpio-cells = <2>;
441 interrupt-controller;
442 #interrupt-cells = <2>
443 gpio-ranges = <&tlmm 0
444 wakeup-parent = <&pdc>
445
446 qup_uart7_rx: qup-uart
447 pins = "gpio23
448 function = "qu
449 drive-strength
450 bias-disable;
451 };
452
453 qup_uart7_tx: qup-uart
454 pins = "gpio22
455 function = "qu
456 drive-strength
457 bias-disable;
458 };
459 };
460
461 intc: interrupt-controller@172
462 compatible = "arm,gic-
463 reg = <0x0 0x17200000
464 <0x0 0x17260000
465 interrupts = <GIC_PPI
466 #interrupt-cells = <3>
467 interrupt-controller;
468 #redistributor-regions
469 redistributor-stride =
470 };
471
472 timer@17420000 {
473 compatible = "arm,armv
474 reg = <0x0 0x17420000
475 ranges = <0 0 0 0x2000
476 #address-cells = <1>;
477 #size-cells = <1>;
478
479 frame@17421000 {
480 reg = <0x17421
481 <0x17422
482 frame-number =
483 interrupts = <
484 <
485 };
486
487 frame@17423000 {
488 reg = <0x17423
489 frame-number =
490 interrupts = <
491 status = "disa
492 };
493
494 frame@17425000 {
495 reg = <0x17425
496 frame-number =
497 interrupts = <
498 status = "disa
499 };
500
501 frame@17427000 {
502 reg = <0x17427
503 frame-number =
504 interrupts = <
505 status = "disa
506 };
507
508 frame@17429000 {
509 reg = <0x17429
510 frame-number =
511 interrupts = <
512 status = "disa
513 };
514
515 frame@1742b000 {
516 reg = <0x1742b
517 frame-number =
518 interrupts = <
519 status = "disa
520 };
521
522 frame@1742d000 {
523 reg = <0x1742d
524 frame-number =
525 interrupts = <
526 status = "disa
527 };
528 };
529
530 apps_rsc: rsc@17a00000 {
531 compatible = "qcom,rpm
532 reg = <0x0 0x17a00000
533 <0x0 0x17a10000
534 <0x0 0x17a20000
535 reg-names = "drv-0", "
536 interrupts = <GIC_SPI
537 <GIC_SPI
538 <GIC_SPI
539 label = "apps_rsc";
540 qcom,tcs-offset = <0xd
541 qcom,drv-id = <2>;
542 qcom,tcs-config = <ACT
543 <WAK
544 power-domains = <&CLUS
545
546 apps_bcm_voter: bcm-vo
547 compatible = "
548 };
549
550 rpmhcc: clock-controll
551 compatible = "
552 #clock-cells =
553 clocks = <&xo_
554 clock-names =
555 };
556 };
557
558 cpufreq_hw: cpufreq@17d91000 {
559 compatible = "qcom,sm4
560 reg = <0 0x17d91000 0
561 <0 0x17d92000 0
562 reg-names = "freq-doma
563 clocks = <&bi_tcxo_div
564 clock-names = "xo", "a
565 interrupts = <GIC_SPI
566 <GIC_SPI
567 interrupt-names = "dcv
568 #freq-domain-cells = <
569 #clock-cells = <1>;
570 };
571 };
572
573 timer {
574 compatible = "arm,armv8-timer"
575 interrupts = <GIC_PPI 13 (GIC_
576 <GIC_PPI 14 (GIC_
577 <GIC_PPI 11 (GIC_
578 <GIC_PPI 10 (GIC_
579 };
580 };
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