1 // SPDX-License-Identifier: BSD-3-Clause
2 /*
3 * Copyright (c) 2023, Qualcomm Innovation Cen
4 */
5
6 #include <dt-bindings/clock/qcom,rpmh.h>
7 #include <dt-bindings/clock/qcom,sm4450-camcc.
8 #include <dt-bindings/clock/qcom,sm4450-dispcc
9 #include <dt-bindings/clock/qcom,sm4450-gcc.h>
10 #include <dt-bindings/clock/qcom,sm4450-gpucc.
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/arm
13 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
14
15 / {
16 interrupt-parent = <&intc>;
17
18 #address-cells = <2>;
19 #size-cells = <2>;
20
21 chosen { };
22
23 clocks {
24 xo_board: xo-board {
25 compatible = "fixed-cl
26 clock-frequency = <768
27 #clock-cells = <0>;
28 };
29
30 sleep_clk: sleep-clk {
31 compatible = "fixed-cl
32 clock-frequency = <320
33 #clock-cells = <0>;
34 };
35
36 bi_tcxo_div2: bi-tcxo-div2-clk
37 #clock-cells = <0>;
38 compatible = "fixed-fa
39 clocks = <&rpmhcc RPMH
40 clock-mult = <1>;
41 clock-div = <2>;
42 };
43 };
44
45 cpus {
46 #address-cells = <2>;
47 #size-cells = <0>;
48
49 CPU0: cpu@0 {
50 device_type = "cpu";
51 compatible = "arm,cort
52 reg = <0x0 0x0>;
53 clocks = <&cpufreq_hw
54 enable-method = "psci"
55 next-level-cache = <&L
56 power-domains = <&CPU_
57 power-domain-names = "
58 qcom,freq-domain = <&c
59 #cooling-cells = <2>;
60
61 L2_0: l2-cache {
62 compatible = "
63 cache-level =
64 cache-unified;
65 next-level-cac
66
67 L3_0: l3-cache
68 compat
69 cache-
70 cache-
71 };
72 };
73 };
74
75 CPU1: cpu@100 {
76 device_type = "cpu";
77 compatible = "arm,cort
78 reg = <0x0 0x100>;
79 clocks = <&cpufreq_hw
80 enable-method = "psci"
81 next-level-cache = <&L
82 power-domains = <&CPU_
83 power-domain-names = "
84 qcom,freq-domain = <&c
85 #cooling-cells = <2>;
86
87 L2_100: l2-cache {
88 compatible = "
89 cache-level =
90 cache-unified;
91 next-level-cac
92 };
93 };
94
95 CPU2: cpu@200 {
96 device_type = "cpu";
97 compatible = "arm,cort
98 reg = <0x0 0x200>;
99 clocks = <&cpufreq_hw
100 enable-method = "psci"
101 next-level-cache = <&L
102 power-domains = <&CPU_
103 power-domain-names = "
104 qcom,freq-domain = <&c
105 #cooling-cells = <2>;
106
107 L2_200: l2-cache {
108 compatible = "
109 cache-level =
110 cache-unified;
111 next-level-cac
112 };
113 };
114
115 CPU3: cpu@300 {
116 device_type = "cpu";
117 compatible = "arm,cort
118 reg = <0x0 0x300>;
119 clocks = <&cpufreq_hw
120 enable-method = "psci"
121 next-level-cache = <&L
122 power-domains = <&CPU_
123 power-domain-names = "
124 qcom,freq-domain = <&c
125 #cooling-cells = <2>;
126
127 L2_300: l2-cache {
128 compatible = "
129 cache-level =
130 cache-unified;
131 next-level-cac
132 };
133 };
134
135 CPU4: cpu@400 {
136 device_type = "cpu";
137 compatible = "arm,cort
138 reg = <0x0 0x400>;
139 clocks = <&cpufreq_hw
140 enable-method = "psci"
141 next-level-cache = <&L
142 power-domains = <&CPU_
143 power-domain-names = "
144 qcom,freq-domain = <&c
145 #cooling-cells = <2>;
146
147 L2_400: l2-cache {
148 compatible = "
149 cache-level =
150 cache-unified;
151 next-level-cac
152 };
153 };
154
155 CPU5: cpu@500 {
156 device_type = "cpu";
157 compatible = "arm,cort
158 reg = <0x0 0x500>;
159 clocks = <&cpufreq_hw
160 enable-method = "psci"
161 next-level-cache = <&L
162 power-domains = <&CPU_
163 power-domain-names = "
164 qcom,freq-domain = <&c
165 #cooling-cells = <2>;
166
167 L2_500: l2-cache {
168 compatible = "
169 cache-level =
170 cache-unified;
171 next-level-cac
172 };
173 };
174
175 CPU6: cpu@600 {
176 device_type = "cpu";
177 compatible = "arm,cort
178 reg = <0x0 0x600>;
179 clocks = <&cpufreq_hw
180 enable-method = "psci"
181 next-level-cache = <&L
182 power-domains = <&CPU_
183 power-domain-names = "
184 qcom,freq-domain = <&c
185 #cooling-cells = <2>;
186
187 L2_600: l2-cache {
188 compatible = "
189 cache-level =
190 cache-unified;
191 next-level-cac
192 };
193 };
194
195 CPU7: cpu@700 {
196 device_type = "cpu";
197 compatible = "arm,cort
198 reg = <0x0 0x700>;
199 clocks = <&cpufreq_hw
200 enable-method = "psci"
201 next-level-cache = <&L
202 power-domains = <&CPU_
203 power-domain-names = "
204 qcom,freq-domain = <&c
205 #cooling-cells = <2>;
206
207 L2_700: l2-cache {
208 compatible = "
209 cache-level =
210 cache-unified;
211 next-level-cac
212 };
213 };
214
215 cpu-map {
216 cluster0 {
217 core0 {
218 cpu =
219 };
220
221 core1 {
222 cpu =
223 };
224
225 core2 {
226 cpu =
227 };
228
229 core3 {
230 cpu =
231 };
232
233 core4 {
234 cpu =
235 };
236
237 core5 {
238 cpu =
239 };
240
241 core6 {
242 cpu =
243 };
244
245 core7 {
246 cpu =
247 };
248 };
249 };
250
251 idle-states {
252 entry-method = "psci";
253
254 LITTLE_CPU_SLEEP_0: cp
255 compatible = "
256 arm,psci-suspe
257 entry-latency-
258 exit-latency-u
259 min-residency-
260 local-timer-st
261 };
262
263 BIG_CPU_SLEEP_0: cpu-s
264 compatible = "
265 arm,psci-suspe
266 entry-latency-
267 exit-latency-u
268 min-residency-
269 local-timer-st
270 };
271 };
272
273 domain-idle-states {
274 CLUSTER_SLEEP_0: clust
275 compatible = "
276 arm,psci-suspe
277 entry-latency-
278 exit-latency-u
279 min-residency-
280 };
281
282 CLUSTER_SLEEP_1: clust
283 compatible = "
284 arm,psci-suspe
285 entry-latency-
286 exit-latency-u
287 min-residency-
288 };
289 };
290 };
291
292 memory@a0000000 {
293 device_type = "memory";
294 /* We expect the bootloader to
295 reg = <0x0 0xa0000000 0x0 0x0>
296 };
297
298 pmu-a55 {
299 compatible = "arm,cortex-a55-p
300 interrupts = <GIC_PPI 7 IRQ_TY
301 };
302
303 pmu-a78 {
304 compatible = "arm,cortex-a78-p
305 interrupts = <GIC_PPI 7 IRQ_TY
306 };
307
308 psci {
309 compatible = "arm,psci-1.0";
310 method = "smc";
311
312 CPU_PD0: power-domain-cpu0 {
313 #power-domain-cells =
314 power-domains = <&CLUS
315 domain-idle-states = <
316 };
317
318 CPU_PD1: power-domain-cpu1 {
319 #power-domain-cells =
320 power-domains = <&CLUS
321 domain-idle-states = <
322 };
323
324 CPU_PD2: power-domain-cpu2 {
325 #power-domain-cells =
326 power-domains = <&CLUS
327 domain-idle-states = <
328 };
329
330 CPU_PD3: power-domain-cpu3 {
331 #power-domain-cells =
332 power-domains = <&CLUS
333 domain-idle-states = <
334 };
335
336 CPU_PD4: power-domain-cpu4 {
337 #power-domain-cells =
338 power-domains = <&CLUS
339 domain-idle-states = <
340 };
341
342 CPU_PD5: power-domain-cpu5 {
343 #power-domain-cells =
344 power-domains = <&CLUS
345 domain-idle-states = <
346 };
347
348 CPU_PD6: power-domain-cpu6 {
349 #power-domain-cells =
350 power-domains = <&CLUS
351 domain-idle-states = <
352 };
353
354 CPU_PD7: power-domain-cpu7 {
355 #power-domain-cells =
356 power-domains = <&CLUS
357 domain-idle-states = <
358 };
359
360 CLUSTER_PD: power-domain-cpu-c
361 #power-domain-cells =
362 domain-idle-states = <
363 };
364 };
365
366 reserved_memory: reserved-memory {
367 #address-cells = <2>;
368 #size-cells = <2>;
369 ranges;
370
371 aop_cmd_db_mem: cmd-db@8086000
372 compatible = "qcom,cmd
373 reg = <0x0 0x80860000
374 no-map;
375 };
376 };
377
378 soc: soc@0 {
379 #address-cells = <2>;
380 #size-cells = <2>;
381 ranges = <0 0 0 0 0x10 0>;
382 dma-ranges = <0 0 0 0 0x10 0>;
383 compatible = "simple-bus";
384
385 gcc: clock-controller@100000 {
386 compatible = "qcom,sm4
387 reg = <0x0 0x00100000
388 #clock-cells = <1>;
389 #reset-cells = <1>;
390 #power-domain-cells =
391 clocks = <&rpmhcc RPMH
392 <&sleep_clk>,
393 <0>,
394 <0>,
395 <0>,
396 <0>;
397 };
398
399 qupv3_id_0: geniqup@ac0000 {
400 compatible = "qcom,gen
401 reg = <0x0 0x00ac0000
402 ranges;
403 clocks = <&gcc GCC_QUP
404 <&gcc GCC_QUP
405 clock-names = "m-ahb",
406 #address-cells = <2>;
407 #size-cells = <2>;
408 status = "disabled";
409
410 uart7: serial@a88000 {
411 compatible = "
412 reg = <0x0 0x0
413 clocks = <&gcc
414 clock-names =
415 interrupts = <
416 pinctrl-0 = <&
417 pinctrl-names
418 status = "disa
419 };
420 };
421
422 tcsr_mutex: hwlock@1f40000 {
423 compatible = "qcom,tcs
424 reg = <0x0 0x01f40000
425 #hwlock-cells = <1>;
426 };
427
428 gpucc: clock-controller@3d9000
429 compatible = "qcom,sm4
430 reg = <0x0 0x03d90000
431 clocks = <&rpmhcc RPMH
432 <&gcc GCC_GPU
433 <&gcc GCC_GPU
434 #clock-cells = <1>;
435 #reset-cells = <1>;
436 #power-domain-cells =
437 };
438
439 camcc: clock-controller@ade000
440 compatible = "qcom,sm4
441 reg = <0x0 0x0ade0000
442 clocks = <&rpmhcc RPMH
443 <&gcc GCC_CAM
444 #clock-cells = <1>;
445 #reset-cells = <1>;
446 #power-domain-cells =
447 };
448
449 dispcc: clock-controller@af000
450 compatible = "qcom,sm4
451 reg = <0x0 0x0af00000
452 clocks = <&rpmhcc RPMH
453 <&rpmhcc RPMH
454 <&gcc GCC_DIS
455 <&sleep_clk>,
456 <0>,
457 <0>;
458 #clock-cells = <1>;
459 #reset-cells = <1>;
460 #power-domain-cells =
461 };
462
463 pdc: interrupt-controller@b220
464 compatible = "qcom,sm4
465 reg = <0 0x0b220000 0
466 qcom,pdc-ranges = <0 4
467 <125
468 #interrupt-cells = <2>
469 interrupt-parent = <&i
470 interrupt-controller;
471 };
472
473 tlmm: pinctrl@f100000 {
474 compatible = "qcom,sm4
475 reg = <0x0 0x0f100000
476 interrupts = <GIC_SPI
477 gpio-controller;
478 #gpio-cells = <2>;
479 interrupt-controller;
480 #interrupt-cells = <2>
481 gpio-ranges = <&tlmm 0
482 wakeup-parent = <&pdc>
483
484 qup_uart7_rx: qup-uart
485 pins = "gpio23
486 function = "qu
487 drive-strength
488 bias-disable;
489 };
490
491 qup_uart7_tx: qup-uart
492 pins = "gpio22
493 function = "qu
494 drive-strength
495 bias-disable;
496 };
497 };
498
499 intc: interrupt-controller@172
500 compatible = "arm,gic-
501 reg = <0x0 0x17200000
502 <0x0 0x17260000
503 interrupts = <GIC_PPI
504 #interrupt-cells = <3>
505 interrupt-controller;
506 #redistributor-regions
507 redistributor-stride =
508 };
509
510 timer@17420000 {
511 compatible = "arm,armv
512 reg = <0x0 0x17420000
513 ranges = <0 0 0 0x2000
514 #address-cells = <1>;
515 #size-cells = <1>;
516
517 frame@17421000 {
518 reg = <0x17421
519 <0x17422
520 frame-number =
521 interrupts = <
522 <
523 };
524
525 frame@17423000 {
526 reg = <0x17423
527 frame-number =
528 interrupts = <
529 status = "disa
530 };
531
532 frame@17425000 {
533 reg = <0x17425
534 frame-number =
535 interrupts = <
536 status = "disa
537 };
538
539 frame@17427000 {
540 reg = <0x17427
541 frame-number =
542 interrupts = <
543 status = "disa
544 };
545
546 frame@17429000 {
547 reg = <0x17429
548 frame-number =
549 interrupts = <
550 status = "disa
551 };
552
553 frame@1742b000 {
554 reg = <0x1742b
555 frame-number =
556 interrupts = <
557 status = "disa
558 };
559
560 frame@1742d000 {
561 reg = <0x1742d
562 frame-number =
563 interrupts = <
564 status = "disa
565 };
566 };
567
568 apps_rsc: rsc@17a00000 {
569 compatible = "qcom,rpm
570 reg = <0x0 0x17a00000
571 <0x0 0x17a10000
572 <0x0 0x17a20000
573 reg-names = "drv-0", "
574 interrupts = <GIC_SPI
575 <GIC_SPI
576 <GIC_SPI
577 label = "apps_rsc";
578 qcom,tcs-offset = <0xd
579 qcom,drv-id = <2>;
580 qcom,tcs-config = <ACT
581 <WAK
582 power-domains = <&CLUS
583
584 apps_bcm_voter: bcm-vo
585 compatible = "
586 };
587
588 rpmhcc: clock-controll
589 compatible = "
590 #clock-cells =
591 clocks = <&xo_
592 clock-names =
593 };
594 };
595
596 cpufreq_hw: cpufreq@17d91000 {
597 compatible = "qcom,sm4
598 reg = <0 0x17d91000 0
599 <0 0x17d92000 0
600 reg-names = "freq-doma
601 clocks = <&bi_tcxo_div
602 clock-names = "xo", "a
603 interrupts = <GIC_SPI
604 <GIC_SPI
605 interrupt-names = "dcv
606 #freq-domain-cells = <
607 #clock-cells = <1>;
608 };
609 };
610
611 timer {
612 compatible = "arm,armv8-timer"
613 interrupts = <GIC_PPI 13 (GIC_
614 <GIC_PPI 14 (GIC_
615 <GIC_PPI 11 (GIC_
616 <GIC_PPI 10 (GIC_
617 };
618 };
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