1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3
2 /*
3 * Copyright (c) 2021, Iskren Chernev <iskren.c
4 */
5
6 #include <dt-bindings/clock/qcom,gcc-sm6115.h>
7 #include <dt-bindings/clock/qcom,sm6115-dispcc
8 #include <dt-bindings/clock/qcom,sm6115-gpucc.
9 #include <dt-bindings/clock/qcom,rpmcc.h>
10 #include <dt-bindings/dma/qcom-gpi.h>
11 #include <dt-bindings/firmware/qcom,scm.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interconnect/qcom,rpm-ic
14 #include <dt-bindings/interconnect/qcom,sm6115
15 #include <dt-bindings/interrupt-controller/arm
16 #include <dt-bindings/power/qcom-rpmpd.h>
17 #include <dt-bindings/thermal/thermal.h>
18
19 / {
20 interrupt-parent = <&intc>;
21
22 #address-cells = <2>;
23 #size-cells = <2>;
24
25 chosen { };
26
27 clocks {
28 xo_board: xo-board {
29 compatible = "fixed-cl
30 #clock-cells = <0>;
31 };
32
33 sleep_clk: sleep-clk {
34 compatible = "fixed-cl
35 #clock-cells = <0>;
36 };
37 };
38
39 cpus {
40 #address-cells = <2>;
41 #size-cells = <0>;
42
43 CPU0: cpu@0 {
44 device_type = "cpu";
45 compatible = "qcom,kry
46 reg = <0x0 0x0>;
47 clocks = <&cpufreq_hw
48 capacity-dmips-mhz = <
49 dynamic-power-coeffici
50 enable-method = "psci"
51 next-level-cache = <&L
52 qcom,freq-domain = <&c
53 power-domains = <&CPU_
54 power-domain-names = "
55 L2_0: l2-cache {
56 compatible = "
57 cache-level =
58 cache-unified;
59 };
60 };
61
62 CPU1: cpu@1 {
63 device_type = "cpu";
64 compatible = "qcom,kry
65 reg = <0x0 0x1>;
66 clocks = <&cpufreq_hw
67 capacity-dmips-mhz = <
68 dynamic-power-coeffici
69 enable-method = "psci"
70 next-level-cache = <&L
71 qcom,freq-domain = <&c
72 power-domains = <&CPU_
73 power-domain-names = "
74 };
75
76 CPU2: cpu@2 {
77 device_type = "cpu";
78 compatible = "qcom,kry
79 reg = <0x0 0x2>;
80 clocks = <&cpufreq_hw
81 capacity-dmips-mhz = <
82 dynamic-power-coeffici
83 enable-method = "psci"
84 next-level-cache = <&L
85 qcom,freq-domain = <&c
86 power-domains = <&CPU_
87 power-domain-names = "
88 };
89
90 CPU3: cpu@3 {
91 device_type = "cpu";
92 compatible = "qcom,kry
93 reg = <0x0 0x3>;
94 clocks = <&cpufreq_hw
95 capacity-dmips-mhz = <
96 dynamic-power-coeffici
97 enable-method = "psci"
98 next-level-cache = <&L
99 qcom,freq-domain = <&c
100 power-domains = <&CPU_
101 power-domain-names = "
102 };
103
104 CPU4: cpu@100 {
105 device_type = "cpu";
106 compatible = "qcom,kry
107 reg = <0x0 0x100>;
108 clocks = <&cpufreq_hw
109 enable-method = "psci"
110 capacity-dmips-mhz = <
111 dynamic-power-coeffici
112 next-level-cache = <&L
113 qcom,freq-domain = <&c
114 power-domains = <&CPU_
115 power-domain-names = "
116 L2_1: l2-cache {
117 compatible = "
118 cache-level =
119 cache-unified;
120 };
121 };
122
123 CPU5: cpu@101 {
124 device_type = "cpu";
125 compatible = "qcom,kry
126 reg = <0x0 0x101>;
127 clocks = <&cpufreq_hw
128 capacity-dmips-mhz = <
129 dynamic-power-coeffici
130 enable-method = "psci"
131 next-level-cache = <&L
132 qcom,freq-domain = <&c
133 power-domains = <&CPU_
134 power-domain-names = "
135 };
136
137 CPU6: cpu@102 {
138 device_type = "cpu";
139 compatible = "qcom,kry
140 reg = <0x0 0x102>;
141 clocks = <&cpufreq_hw
142 capacity-dmips-mhz = <
143 dynamic-power-coeffici
144 enable-method = "psci"
145 next-level-cache = <&L
146 qcom,freq-domain = <&c
147 power-domains = <&CPU_
148 power-domain-names = "
149 };
150
151 CPU7: cpu@103 {
152 device_type = "cpu";
153 compatible = "qcom,kry
154 reg = <0x0 0x103>;
155 clocks = <&cpufreq_hw
156 capacity-dmips-mhz = <
157 dynamic-power-coeffici
158 enable-method = "psci"
159 next-level-cache = <&L
160 qcom,freq-domain = <&c
161 power-domains = <&CPU_
162 power-domain-names = "
163 };
164
165 cpu-map {
166 cluster0 {
167 core0 {
168 cpu =
169 };
170
171 core1 {
172 cpu =
173 };
174
175 core2 {
176 cpu =
177 };
178
179 core3 {
180 cpu =
181 };
182 };
183
184 cluster1 {
185 core0 {
186 cpu =
187 };
188
189 core1 {
190 cpu =
191 };
192
193 core2 {
194 cpu =
195 };
196
197 core3 {
198 cpu =
199 };
200 };
201 };
202
203 idle-states {
204 entry-method = "psci";
205
206 LITTLE_CPU_SLEEP_0: cp
207 compatible = "
208 idle-state-nam
209 arm,psci-suspe
210 entry-latency-
211 exit-latency-u
212 min-residency-
213 local-timer-st
214 };
215
216 BIG_CPU_SLEEP_0: cpu-s
217 compatible = "
218 idle-state-nam
219 arm,psci-suspe
220 entry-latency-
221 exit-latency-u
222 min-residency-
223 local-timer-st
224 };
225 };
226
227 domain-idle-states {
228 CLUSTER_0_SLEEP_0: clu
229 /* GDHS */
230 compatible = "
231 arm,psci-suspe
232 entry-latency-
233 exit-latency-u
234 min-residency-
235 };
236
237 CLUSTER_0_SLEEP_1: clu
238 /* Power Colla
239 compatible = "
240 arm,psci-suspe
241 entry-latency-
242 exit-latency-u
243 min-residency-
244 };
245
246 CLUSTER_1_SLEEP_0: clu
247 /* GDHS */
248 compatible = "
249 arm,psci-suspe
250 entry-latency-
251 exit-latency-u
252 min-residency-
253 };
254
255 CLUSTER_1_SLEEP_1: clu
256 /* Power Colla
257 compatible = "
258 arm,psci-suspe
259 entry-latency-
260 exit-latency-u
261 min-residency-
262 };
263 };
264 };
265
266 firmware {
267 scm: scm {
268 compatible = "qcom,scm
269 #reset-cells = <1>;
270 interconnects = <&syst
271 &bimc
272 };
273 };
274
275 memory@80000000 {
276 device_type = "memory";
277 /* We expect the bootloader to
278 reg = <0 0x80000000 0 0>;
279 };
280
281 qup_opp_table: opp-table-qup {
282 compatible = "operating-points
283
284 opp-75000000 {
285 opp-hz = /bits/ 64 <75
286 required-opps = <&rpmp
287 };
288
289 opp-100000000 {
290 opp-hz = /bits/ 64 <10
291 required-opps = <&rpmp
292 };
293
294 opp-128000000 {
295 opp-hz = /bits/ 64 <12
296 required-opps = <&rpmp
297 };
298 };
299
300 pmu {
301 compatible = "arm,armv8-pmuv3"
302 interrupts = <GIC_PPI 6 IRQ_TY
303 };
304
305 psci {
306 compatible = "arm,psci-1.0";
307 method = "smc";
308
309 CPU_PD0: power-domain-cpu0 {
310 #power-domain-cells =
311 power-domains = <&CLUS
312 domain-idle-states = <
313 };
314
315 CPU_PD1: power-domain-cpu1 {
316 #power-domain-cells =
317 power-domains = <&CLUS
318 domain-idle-states = <
319 };
320
321 CPU_PD2: power-domain-cpu2 {
322 #power-domain-cells =
323 power-domains = <&CLUS
324 domain-idle-states = <
325 };
326
327 CPU_PD3: power-domain-cpu3 {
328 #power-domain-cells =
329 power-domains = <&CLUS
330 domain-idle-states = <
331 };
332
333 CPU_PD4: power-domain-cpu4 {
334 #power-domain-cells =
335 power-domains = <&CLUS
336 domain-idle-states = <
337 };
338
339 CPU_PD5: power-domain-cpu5 {
340 #power-domain-cells =
341 power-domains = <&CLUS
342 domain-idle-states = <
343 };
344
345 CPU_PD6: power-domain-cpu6 {
346 #power-domain-cells =
347 power-domains = <&CLUS
348 domain-idle-states = <
349 };
350
351 CPU_PD7: power-domain-cpu7 {
352 #power-domain-cells =
353 power-domains = <&CLUS
354 domain-idle-states = <
355 };
356
357 CLUSTER_0_PD: power-domain-cpu
358 #power-domain-cells =
359 domain-idle-states = <
360 };
361
362 CLUSTER_1_PD: power-domain-cpu
363 #power-domain-cells =
364 domain-idle-states = <
365 };
366 };
367
368 rpm: remoteproc {
369 compatible = "qcom,sm6115-rpm-
370
371 glink-edge {
372 compatible = "qcom,gli
373
374 interrupts = <GIC_SPI
375 qcom,rpm-msg-ram = <&r
376 mboxes = <&apcs_glb 0>
377
378 rpm_requests: rpm-requ
379 compatible = "
380 qcom,glink-cha
381
382 rpmcc: clock-c
383 compat
384 clocks
385 clock-
386 #clock
387 };
388
389 rpmpd: power-c
390 compat
391 #power
392 operat
393
394 rpmpd_
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428 };
429 };
430 };
431 };
432 };
433
434 reserved_memory: reserved-memory {
435 #address-cells = <2>;
436 #size-cells = <2>;
437 ranges;
438
439 hyp_mem: memory@45700000 {
440 reg = <0x0 0x45700000
441 no-map;
442 };
443
444 xbl_aop_mem: memory@45e00000 {
445 reg = <0x0 0x45e00000
446 no-map;
447 };
448
449 sec_apps_mem: memory@45fff000
450 reg = <0x0 0x45fff000
451 no-map;
452 };
453
454 smem_mem: memory@46000000 {
455 compatible = "qcom,sme
456 reg = <0x0 0x46000000
457 no-map;
458
459 hwlocks = <&tcsr_mutex
460 qcom,rpm-msg-ram = <&r
461 };
462
463 cdsp_sec_mem: memory@46200000
464 reg = <0x0 0x46200000
465 no-map;
466 };
467
468 pil_modem_mem: memory@4ab00000
469 reg = <0x0 0x4ab00000
470 no-map;
471 };
472
473 pil_video_mem: memory@51400000
474 reg = <0x0 0x51400000
475 no-map;
476 };
477
478 wlan_msa_mem: memory@51900000
479 reg = <0x0 0x51900000
480 no-map;
481 };
482
483 pil_cdsp_mem: memory@51a00000
484 reg = <0x0 0x51a00000
485 no-map;
486 };
487
488 pil_adsp_mem: memory@53800000
489 reg = <0x0 0x53800000
490 no-map;
491 };
492
493 pil_ipa_fw_mem: memory@5610000
494 reg = <0x0 0x56100000
495 no-map;
496 };
497
498 pil_ipa_gsi_mem: memory@561100
499 reg = <0x0 0x56110000
500 no-map;
501 };
502
503 pil_gpu_mem: memory@56115000 {
504 reg = <0x0 0x56115000
505 no-map;
506 };
507
508 cont_splash_memory: memory@5c0
509 reg = <0x0 0x5c000000
510 no-map;
511 };
512
513 dfps_data_memory: memory@5cf00
514 reg = <0x0 0x5cf00000
515 no-map;
516 };
517
518 removed_mem: memory@60000000 {
519 reg = <0x0 0x60000000
520 no-map;
521 };
522
523 rmtfs_mem: memory@89b01000 {
524 compatible = "qcom,rmt
525 reg = <0x0 0x89b01000
526 no-map;
527
528 qcom,client-id = <1>;
529 qcom,vmid = <QCOM_SCM_
530 };
531 };
532
533 smp2p-adsp {
534 compatible = "qcom,smp2p";
535 qcom,smem = <443>, <429>;
536
537 interrupts = <GIC_SPI 279 IRQ_
538
539 mboxes = <&apcs_glb 10>;
540
541 qcom,local-pid = <0>;
542 qcom,remote-pid = <2>;
543
544 adsp_smp2p_out: master-kernel
545 qcom,entry-name = "mas
546 #qcom,smem-state-cells
547 };
548
549 adsp_smp2p_in: slave-kernel {
550 qcom,entry-name = "sla
551
552 interrupt-controller;
553 #interrupt-cells = <2>
554 };
555 };
556
557 smp2p-cdsp {
558 compatible = "qcom,smp2p";
559 qcom,smem = <94>, <432>;
560
561 interrupts = <GIC_SPI 263 IRQ_
562
563 mboxes = <&apcs_glb 30>;
564
565 qcom,local-pid = <0>;
566 qcom,remote-pid = <5>;
567
568 cdsp_smp2p_out: master-kernel
569 qcom,entry-name = "mas
570 #qcom,smem-state-cells
571 };
572
573 cdsp_smp2p_in: slave-kernel {
574 qcom,entry-name = "sla
575
576 interrupt-controller;
577 #interrupt-cells = <2>
578 };
579 };
580
581 smp2p-mpss {
582 compatible = "qcom,smp2p";
583 qcom,smem = <435>, <428>;
584
585 interrupts = <GIC_SPI 70 IRQ_T
586
587 mboxes = <&apcs_glb 14>;
588
589 qcom,local-pid = <0>;
590 qcom,remote-pid = <1>;
591
592 modem_smp2p_out: master-kernel
593 qcom,entry-name = "mas
594 #qcom,smem-state-cells
595 };
596
597 modem_smp2p_in: slave-kernel {
598 qcom,entry-name = "sla
599
600 interrupt-controller;
601 #interrupt-cells = <2>
602 };
603 };
604
605 soc: soc@0 {
606 compatible = "simple-bus";
607 #address-cells = <2>;
608 #size-cells = <2>;
609 ranges = <0 0 0 0 0x10 0>;
610 dma-ranges = <0 0 0 0 0x10 0>;
611
612 tcsr_mutex: hwlock@340000 {
613 compatible = "qcom,tcs
614 reg = <0x0 0x00340000
615 #hwlock-cells = <1>;
616 };
617
618 tcsr_regs: syscon@3c0000 {
619 compatible = "qcom,sm6
620 reg = <0x0 0x003c0000
621 };
622
623 tlmm: pinctrl@500000 {
624 compatible = "qcom,sm6
625 reg = <0x0 0x00500000
626 <0x0 0x00900000
627 <0x0 0x00d00000
628 reg-names = "west", "s
629 interrupts = <GIC_SPI
630 gpio-controller;
631 gpio-ranges = <&tlmm 0
632 #gpio-cells = <2>;
633 interrupt-controller;
634 #interrupt-cells = <2>
635
636 qup_i2c0_default: qup-
637 pins = "gpio0"
638 function = "qu
639 drive-strength
640 bias-pull-up;
641 };
642
643 qup_i2c1_default: qup-
644 pins = "gpio4"
645 function = "qu
646 drive-strength
647 bias-pull-up;
648 };
649
650 qup_i2c2_default: qup-
651 pins = "gpio6"
652 function = "qu
653 drive-strength
654 bias-pull-up;
655 };
656
657 qup_i2c3_default: qup-
658 pins = "gpio8"
659 function = "qu
660 drive-strength
661 bias-pull-up;
662 };
663
664 qup_i2c4_default: qup-
665 pins = "gpio12
666 function = "qu
667 drive-strength
668 bias-pull-up;
669 };
670
671 qup_i2c5_default: qup-
672 pins = "gpio14
673 function = "qu
674 drive-strength
675 bias-pull-up;
676 };
677
678 qup_spi0_default: qup-
679 pins = "gpio0"
680 function = "qu
681 drive-strength
682 bias-pull-up;
683 };
684
685 qup_spi1_default: qup-
686 pins = "gpio4"
687 function = "qu
688 drive-strength
689 bias-pull-up;
690 };
691
692 qup_spi2_default: qup-
693 pins = "gpio6"
694 function = "qu
695 drive-strength
696 bias-pull-up;
697 };
698
699 qup_spi3_default: qup-
700 pins = "gpio8"
701 function = "qu
702 drive-strength
703 bias-pull-up;
704 };
705
706 qup_spi4_default: qup-
707 pins = "gpio12
708 function = "qu
709 drive-strength
710 bias-pull-up;
711 };
712
713 qup_spi5_default: qup-
714 pins = "gpio14
715 function = "qu
716 drive-strength
717 bias-pull-up;
718 };
719
720 sdc1_state_on: sdc1-on
721 clk-pins {
722 pins =
723 bias-d
724 drive-
725 };
726
727 cmd-pins {
728 pins =
729 bias-p
730 drive-
731 };
732
733 data-pins {
734 pins =
735 bias-p
736 drive-
737 };
738
739 rclk-pins {
740 pins =
741 bias-p
742 };
743 };
744
745 sdc1_state_off: sdc1-o
746 clk-pins {
747 pins =
748 bias-d
749 drive-
750 };
751
752 cmd-pins {
753 pins =
754 bias-p
755 drive-
756 };
757
758 data-pins {
759 pins =
760 bias-p
761 drive-
762 };
763
764 rclk-pins {
765 pins =
766 bias-p
767 };
768 };
769
770 sdc2_state_on: sdc2-on
771 clk-pins {
772 pins =
773 bias-d
774 drive-
775 };
776
777 cmd-pins {
778 pins =
779 bias-p
780 drive-
781 };
782
783 data-pins {
784 pins =
785 bias-p
786 drive-
787 };
788 };
789
790 sdc2_state_off: sdc2-o
791 clk-pins {
792 pins =
793 bias-d
794 drive-
795 };
796
797 cmd-pins {
798 pins =
799 bias-p
800 drive-
801 };
802
803 data-pins {
804 pins =
805 bias-p
806 drive-
807 };
808 };
809 };
810
811 gcc: clock-controller@1400000
812 compatible = "qcom,gcc
813 reg = <0x0 0x01400000
814 clocks = <&rpmcc RPM_S
815 clock-names = "bi_tcxo
816 #clock-cells = <1>;
817 #reset-cells = <1>;
818 #power-domain-cells =
819 };
820
821 usb_hsphy: phy@1613000 {
822 compatible = "qcom,sm6
823 reg = <0x0 0x01613000
824 #phy-cells = <0>;
825
826 clocks = <&gcc GCC_AHB
827 clock-names = "cfg_ahb
828
829 resets = <&gcc GCC_QUS
830 nvmem-cells = <&qusb2_
831
832 status = "disabled";
833 };
834
835 cryptobam: dma-controller@1b04
836 compatible = "qcom,bam
837 reg = <0x0 0x01b04000
838 interrupts = <GIC_SPI
839 clocks = <&rpmcc RPM_S
840 clock-names = "bam_clk
841 #dma-cells = <1>;
842 qcom,ee = <0>;
843 qcom,controlled-remote
844 iommus = <&apps_smmu 0
845 <&apps_smmu 0
846 <&apps_smmu 0
847 <&apps_smmu 0
848 <&apps_smmu 0
849 };
850
851 crypto: crypto@1b3a000 {
852 compatible = "qcom,sm6
853 reg = <0x0 0x01b3a000
854 clocks = <&rpmcc RPM_S
855 clock-names = "core";
856
857 dmas = <&cryptobam 6>,
858 dma-names = "rx", "tx"
859 iommus = <&apps_smmu 0
860 <&apps_smmu 0
861 <&apps_smmu 0
862 <&apps_smmu 0
863 <&apps_smmu 0
864 };
865
866 usb_qmpphy: phy@1615000 {
867 compatible = "qcom,sm6
868 reg = <0x0 0x01615000
869
870 clocks = <&gcc GCC_AHB
871 <&gcc GCC_USB
872 <&gcc GCC_USB
873 <&gcc GCC_USB
874 clock-names = "cfg_ahb
875 "ref",
876 "com_aux
877 "pipe";
878
879 resets = <&gcc GCC_USB
880 <&gcc GCC_USB
881 reset-names = "phy", "
882
883 #clock-cells = <0>;
884 clock-output-names = "
885
886 #phy-cells = <0>;
887 orientation-switch;
888
889 qcom,tcsr-reg = <&tcsr
890
891 status = "disabled";
892
893 ports {
894 #address-cells
895 #size-cells =
896
897 port@0 {
898 reg =
899
900 usb_qm
901 };
902 };
903
904 port@1 {
905 reg =
906
907 usb_qm
908
909 };
910 };
911 };
912 };
913
914 system_noc: interconnect@18800
915 compatible = "qcom,sm6
916 reg = <0x0 0x01880000
917 clocks = <&gcc GCC_SYS
918 <&gcc GCC_SYS
919 <&gcc GCC_SYS
920 <&rpmcc RPM_S
921 clock-names = "cpu_axi
922 "ufs_axi
923 "usb_axi
924 "ipa";
925 #interconnect-cells =
926
927 clk_virt: interconnect
928 compatible = "
929 #interconnect-
930 };
931
932 mmrt_virt: interconnec
933 compatible = "
934 #interconnect-
935 };
936
937 mmnrt_virt: interconne
938 compatible = "
939 #interconnect-
940 };
941 };
942
943 config_noc: interconnect@19000
944 compatible = "qcom,sm6
945 reg = <0x0 0x01900000
946 clocks = <&gcc GCC_CFG
947 clock-names = "usb_axi
948 #interconnect-cells =
949 };
950
951 qfprom@1b40000 {
952 compatible = "qcom,sm6
953 reg = <0x0 0x01b40000
954 #address-cells = <1>;
955 #size-cells = <1>;
956
957 qusb2_hstx_trim: hstx-
958 reg = <0x25b 0
959 bits = <1 4>;
960 };
961
962 gpu_speed_bin: gpu-spe
963 reg = <0x6006
964 bits = <5 8>;
965 };
966 };
967
968 rng: rng@1b53000 {
969 compatible = "qcom,prn
970 reg = <0x0 0x01b53000
971 clocks = <&gcc GCC_PRN
972 clock-names = "core";
973 };
974
975 pmu@1b8e300 {
976 compatible = "qcom,sm6
977 reg = <0x0 0x01b8e300
978 interrupts = <GIC_SPI
979
980 operating-points-v2 =
981 interconnects = <&bimc
982 &bimc
983
984 cpu_bwmon_opp_table: o
985 compatible = "
986
987 opp-0 {
988 opp-pe
989 };
990
991 opp-1 {
992 opp-pe
993 };
994
995 opp-2 {
996 opp-pe
997 };
998
999 opp-3 {
1000 opp-p
1001 };
1002
1003 opp-4 {
1004 opp-p
1005 };
1006
1007 opp-5 {
1008 opp-p
1009 };
1010
1011 opp-6 {
1012 opp-p
1013 };
1014
1015 opp-7 {
1016 opp-p
1017 };
1018
1019 opp-8 {
1020 opp-p
1021 };
1022
1023 opp-9 {
1024 opp-p
1025 };
1026 };
1027 };
1028
1029 spmi_bus: spmi@1c40000 {
1030 compatible = "qcom,sp
1031 reg = <0x0 0x01c40000
1032 <0x0 0x01e00000
1033 <0x0 0x03e00000
1034 <0x0 0x03f00000
1035 <0x0 0x01c0a000
1036 reg-names = "core", "
1037 interrupt-names = "pe
1038 interrupts = <GIC_SPI
1039 qcom,ee = <0>;
1040 qcom,channel = <0>;
1041 #address-cells = <2>;
1042 #size-cells = <0>;
1043 interrupt-controller;
1044 #interrupt-cells = <4
1045 };
1046
1047 tsens0: thermal-sensor@441100
1048 compatible = "qcom,sm
1049 reg = <0x0 0x04411000
1050 <0x0 0x04410000
1051 #qcom,sensors = <16>;
1052 interrupts = <GIC_SPI
1053 <GIC_SPI
1054 interrupt-names = "up
1055 #thermal-sensor-cells
1056 };
1057
1058 bimc: interconnect@4480000 {
1059 compatible = "qcom,sm
1060 reg = <0x0 0x04480000
1061 #interconnect-cells =
1062 };
1063
1064 rpm_msg_ram: sram@45f0000 {
1065 compatible = "qcom,rp
1066 reg = <0x0 0x045f0000
1067 };
1068
1069 sram@4690000 {
1070 compatible = "qcom,rp
1071 reg = <0x0 0x04690000
1072 };
1073
1074 sdhc_1: mmc@4744000 {
1075 compatible = "qcom,sm
1076 reg = <0x0 0x04744000
1077 <0x0 0x04745000
1078 <0x0 0x04748000
1079 reg-names = "hc", "cq
1080
1081 interrupts = <GIC_SPI
1082 <GIC_SPI
1083 interrupt-names = "hc
1084
1085 clocks = <&gcc GCC_SD
1086 <&gcc GCC_SD
1087 <&rpmcc RPM_
1088 <&gcc GCC_SD
1089 clock-names = "iface"
1090
1091 resets = <&gcc GCC_SD
1092
1093 power-domains = <&rpm
1094 operating-points-v2 =
1095 iommus = <&apps_smmu
1096 interconnects = <&sys
1097 &bim
1098 <&bim
1099 &con
1100 interconnect-names =
1101
1102
1103 bus-width = <8>;
1104 status = "disabled";
1105
1106 sdhc1_opp_table: opp-
1107 compatible =
1108
1109 opp-100000000
1110 opp-h
1111 requi
1112 opp-p
1113 opp-a
1114 };
1115
1116 opp-192000000
1117 opp-h
1118 requi
1119 opp-p
1120 opp-a
1121 };
1122
1123 opp-384000000
1124 opp-h
1125 requi
1126 opp-p
1127 opp-a
1128 };
1129 };
1130 };
1131
1132 sdhc_2: mmc@4784000 {
1133 compatible = "qcom,sm
1134 reg = <0x0 0x04784000
1135 reg-names = "hc";
1136
1137 interrupts = <GIC_SPI
1138 <GIC_SPI
1139 interrupt-names = "hc
1140
1141 clocks = <&gcc GCC_SD
1142 <&gcc GCC_SD
1143 <&rpmcc RPM_
1144 clock-names = "iface"
1145
1146 power-domains = <&rpm
1147 operating-points-v2 =
1148 iommus = <&apps_smmu
1149 resets = <&gcc GCC_SD
1150 interconnects = <&sys
1151 &bim
1152 <&bim
1153 &con
1154 interconnect-names =
1155
1156
1157 bus-width = <4>;
1158 qcom,dll-config = <0x
1159 qcom,ddr-config = <0x
1160 status = "disabled";
1161
1162 sdhc2_opp_table: opp-
1163 compatible =
1164
1165 opp-100000000
1166 opp-h
1167 requi
1168 opp-p
1169 opp-a
1170 };
1171
1172 opp-202000000
1173 opp-h
1174 requi
1175 opp-p
1176 opp-a
1177 };
1178 };
1179 };
1180
1181 ufs_mem_hc: ufs@4804000 {
1182 compatible = "qcom,sm
1183 reg = <0x0 0x04804000
1184 reg-names = "std", "i
1185 interrupts = <GIC_SPI
1186 phys = <&ufs_mem_phy>
1187 phy-names = "ufsphy";
1188 lanes-per-direction =
1189 #reset-cells = <1>;
1190 resets = <&gcc GCC_UF
1191 reset-names = "rst";
1192
1193 power-domains = <&gcc
1194 iommus = <&apps_smmu
1195
1196 clocks = <&gcc GCC_UF
1197 <&gcc GCC_SY
1198 <&gcc GCC_UF
1199 <&gcc GCC_UF
1200 <&rpmcc RPM_
1201 <&gcc GCC_UF
1202 <&gcc GCC_UF
1203 <&gcc GCC_UF
1204 clock-names = "core_c
1205 "bus_ag
1206 "iface_
1207 "core_c
1208 "ref_cl
1209 "tx_lan
1210 "rx_lan
1211 "ice_co
1212
1213 freq-table-hz = <5000
1214 <0 0>
1215 <0 0>
1216 <3750
1217 <0 0>
1218 <0 0>
1219 <0 0>
1220 <7500
1221
1222 status = "disabled";
1223 };
1224
1225 ufs_mem_phy: phy@4807000 {
1226 compatible = "qcom,sm
1227 reg = <0x0 0x04807000
1228
1229 clocks = <&rpmcc RPM_
1230 <&gcc GCC_UF
1231 <&gcc GCC_UF
1232 clock-names = "ref",
1233 "ref_au
1234 "qref";
1235
1236 power-domains = <&gcc
1237
1238 resets = <&ufs_mem_hc
1239 reset-names = "ufsphy
1240
1241 #phy-cells = <0>;
1242
1243 status = "disabled";
1244 };
1245
1246 gpi_dma0: dma-controller@4a00
1247 compatible = "qcom,sm
1248 reg = <0x0 0x04a00000
1249 interrupts = <GIC_SPI
1250 <GIC_SPI
1251 <GIC_SPI
1252 <GIC_SPI
1253 <GIC_SPI
1254 <GIC_SPI
1255 <GIC_SPI
1256 <GIC_SPI
1257 <GIC_SPI
1258 <GIC_SPI
1259 dma-channels = <10>;
1260 dma-channel-mask = <0
1261 iommus = <&apps_smmu
1262 #dma-cells = <3>;
1263 status = "disabled";
1264 };
1265
1266 qupv3_id_0: geniqup@4ac0000 {
1267 compatible = "qcom,ge
1268 reg = <0x0 0x04ac0000
1269 clock-names = "m-ahb"
1270 clocks = <&gcc GCC_QU
1271 <&gcc GCC_QU
1272 #address-cells = <2>;
1273 #size-cells = <2>;
1274 iommus = <&apps_smmu
1275 ranges;
1276 status = "disabled";
1277
1278 i2c0: i2c@4a80000 {
1279 compatible =
1280 reg = <0x0 0x
1281 clock-names =
1282 clocks = <&gc
1283 pinctrl-names
1284 pinctrl-0 = <
1285 interrupts =
1286 dmas = <&gpi_
1287 <&gpi_
1288 dma-names = "
1289 interconnects
1290
1291
1292
1293
1294
1295 interconnect-
1296
1297
1298 #address-cell
1299 #size-cells =
1300 status = "dis
1301 };
1302
1303 spi0: spi@4a80000 {
1304 compatible =
1305 reg = <0x0 0x
1306 clock-names =
1307 clocks = <&gc
1308 pinctrl-names
1309 pinctrl-0 = <
1310 interrupts =
1311 dmas = <&gpi_
1312 <&gpi_
1313 dma-names = "
1314 interconnects
1315
1316
1317
1318
1319
1320 interconnect-
1321
1322
1323 #address-cell
1324 #size-cells =
1325 status = "dis
1326 };
1327
1328 i2c1: i2c@4a84000 {
1329 compatible =
1330 reg = <0x0 0x
1331 clock-names =
1332 clocks = <&gc
1333 pinctrl-names
1334 pinctrl-0 = <
1335 interrupts =
1336 dmas = <&gpi_
1337 <&gpi_
1338 dma-names = "
1339 interconnects
1340
1341
1342
1343
1344
1345 interconnect-
1346
1347
1348 #address-cell
1349 #size-cells =
1350 status = "dis
1351 };
1352
1353 spi1: spi@4a84000 {
1354 compatible =
1355 reg = <0x0 0x
1356 clock-names =
1357 clocks = <&gc
1358 pinctrl-names
1359 pinctrl-0 = <
1360 interrupts =
1361 dmas = <&gpi_
1362 <&gpi_
1363 dma-names = "
1364 interconnects
1365
1366
1367
1368
1369
1370 interconnect-
1371
1372
1373 #address-cell
1374 #size-cells =
1375 status = "dis
1376 };
1377
1378 i2c2: i2c@4a88000 {
1379 compatible =
1380 reg = <0x0 0x
1381 clock-names =
1382 clocks = <&gc
1383 pinctrl-names
1384 pinctrl-0 = <
1385 interrupts =
1386 dmas = <&gpi_
1387 <&gpi_
1388 dma-names = "
1389 interconnects
1390
1391
1392
1393
1394
1395 interconnect-
1396
1397
1398 #address-cell
1399 #size-cells =
1400 status = "dis
1401 };
1402
1403 spi2: spi@4a88000 {
1404 compatible =
1405 reg = <0x0 0x
1406 clock-names =
1407 clocks = <&gc
1408 pinctrl-names
1409 pinctrl-0 = <
1410 interrupts =
1411 dmas = <&gpi_
1412 <&gpi_
1413 dma-names = "
1414 interconnects
1415
1416
1417
1418
1419
1420 interconnect-
1421
1422
1423 #address-cell
1424 #size-cells =
1425 status = "dis
1426 };
1427
1428 i2c3: i2c@4a8c000 {
1429 compatible =
1430 reg = <0x0 0x
1431 clock-names =
1432 clocks = <&gc
1433 pinctrl-names
1434 pinctrl-0 = <
1435 interrupts =
1436 dmas = <&gpi_
1437 <&gpi_
1438 dma-names = "
1439 interconnects
1440
1441
1442
1443
1444
1445 interconnect-
1446
1447
1448 #address-cell
1449 #size-cells =
1450 status = "dis
1451 };
1452
1453 spi3: spi@4a8c000 {
1454 compatible =
1455 reg = <0x0 0x
1456 clock-names =
1457 clocks = <&gc
1458 pinctrl-names
1459 pinctrl-0 = <
1460 interrupts =
1461 dmas = <&gpi_
1462 <&gpi_
1463 dma-names = "
1464 interconnects
1465
1466
1467
1468
1469
1470 interconnect-
1471
1472
1473 #address-cell
1474 #size-cells =
1475 status = "dis
1476 };
1477
1478 uart3: serial@4a8c000
1479 compatible =
1480 reg = <0x0 0x
1481 interrupts-ex
1482 clocks = <&gc
1483 clock-names =
1484 power-domains
1485 operating-poi
1486 interconnects
1487
1488
1489
1490 interconnect-
1491
1492 status = "dis
1493 };
1494
1495 i2c4: i2c@4a90000 {
1496 compatible =
1497 reg = <0x0 0x
1498 clock-names =
1499 clocks = <&gc
1500 pinctrl-names
1501 pinctrl-0 = <
1502 interrupts =
1503 dmas = <&gpi_
1504 <&gpi_
1505 dma-names = "
1506 interconnects
1507
1508
1509
1510
1511
1512 interconnect-
1513
1514
1515 #address-cell
1516 #size-cells =
1517 status = "dis
1518 };
1519
1520 spi4: spi@4a90000 {
1521 compatible =
1522 reg = <0x0 0x
1523 clock-names =
1524 clocks = <&gc
1525 pinctrl-names
1526 pinctrl-0 = <
1527 interrupts =
1528 dmas = <&gpi_
1529 <&gpi_
1530 dma-names = "
1531 interconnects
1532
1533
1534
1535
1536
1537 interconnect-
1538
1539
1540 #address-cell
1541 #size-cells =
1542 status = "dis
1543 };
1544
1545 uart4: serial@4a90000
1546 compatible =
1547 reg = <0x0 0x
1548 clock-names =
1549 clocks = <&gc
1550 interrupts =
1551 interconnects
1552
1553
1554
1555 interconnect-
1556
1557 status = "dis
1558 };
1559
1560 i2c5: i2c@4a94000 {
1561 compatible =
1562 reg = <0x0 0x
1563 clock-names =
1564 clocks = <&gc
1565 pinctrl-names
1566 pinctrl-0 = <
1567 interrupts =
1568 dmas = <&gpi_
1569 <&gpi_
1570 dma-names = "
1571 interconnects
1572
1573
1574
1575
1576
1577 interconnect-
1578
1579
1580 #address-cell
1581 #size-cells =
1582 status = "dis
1583 };
1584
1585 spi5: spi@4a94000 {
1586 compatible =
1587 reg = <0x0 0x
1588 clock-names =
1589 clocks = <&gc
1590 pinctrl-names
1591 pinctrl-0 = <
1592 interrupts =
1593 dmas = <&gpi_
1594 <&gpi_
1595 dma-names = "
1596 interconnects
1597
1598
1599
1600
1601
1602 interconnect-
1603
1604
1605 #address-cell
1606 #size-cells =
1607 status = "dis
1608 };
1609 };
1610
1611 usb: usb@4ef8800 {
1612 compatible = "qcom,sm
1613 reg = <0x0 0x04ef8800
1614 #address-cells = <2>;
1615 #size-cells = <2>;
1616 ranges;
1617
1618 clocks = <&gcc GCC_CF
1619 <&gcc GCC_US
1620 <&gcc GCC_SY
1621 <&gcc GCC_US
1622 <&gcc GCC_US
1623 <&gcc GCC_US
1624 clock-names = "cfg_no
1625
1626 assigned-clocks = <&g
1627 <&g
1628 assigned-clock-rates
1629
1630 interrupts = <GIC_SPI
1631 <GIC_SPI
1632 <GIC_SPI
1633 <GIC_SPI
1634 interrupt-names = "pw
1635 "qu
1636 "hs
1637 "ss
1638
1639 resets = <&gcc GCC_US
1640 power-domains = <&gcc
1641 /* TODO: USB<->IPA p
1642 interconnects = <&sys
1643 &bim
1644 <&bim
1645 &con
1646 interconnect-names =
1647
1648
1649 status = "disabled";
1650
1651 usb_dwc3: usb@4e00000
1652 compatible =
1653 reg = <0x0 0x
1654 interrupts =
1655 phys = <&usb_
1656 phy-names = "
1657 iommus = <&ap
1658 snps,dis_u2_s
1659 snps,dis_enbl
1660 snps,has-lpm-
1661 snps,hird-thr
1662 snps,usb3_lpm
1663 snps,parkmode
1664
1665 usb-role-swit
1666
1667 ports {
1668 #addr
1669 #size
1670
1671 port@
1672
1673
1674
1675
1676 };
1677
1678 port@
1679
1680
1681
1682
1683
1684 };
1685 };
1686 };
1687 };
1688
1689 gpu: gpu@5900000 {
1690 compatible = "qcom,ad
1691 reg = <0x0 0x05900000
1692 reg-names = "kgsl_3d0
1693
1694 /* There's no (real)
1695 clocks = <&gpucc GPU_
1696 <&gpucc GPU_
1697 <&gcc GCC_BI
1698 <&gcc GCC_GP
1699 <&gpucc GPU_
1700 <&gpucc GPU_
1701 clock-names = "core",
1702 "iface"
1703 "mem_if
1704 "alt_me
1705 "gmu",
1706 "xo";
1707
1708 interrupts = <GIC_SPI
1709
1710 iommus = <&adreno_smm
1711 operating-points-v2 =
1712 power-domains = <&rpm
1713 qcom,gmu = <&gmu_wrap
1714
1715 nvmem-cells = <&gpu_s
1716 nvmem-cell-names = "s
1717 #cooling-cells = <2>;
1718
1719 status = "disabled";
1720
1721 zap-shader {
1722 memory-region
1723 };
1724
1725 gpu_opp_table: opp-ta
1726 compatible =
1727
1728 opp-320000000
1729 opp-h
1730 requi
1731 opp-s
1732 };
1733
1734 opp-465000000
1735 opp-h
1736 requi
1737 opp-s
1738 };
1739
1740 opp-600000000
1741 opp-h
1742 requi
1743 opp-s
1744 };
1745
1746 opp-745000000
1747 opp-h
1748 requi
1749 opp-s
1750 };
1751
1752 opp-820000000
1753 opp-h
1754 requi
1755 opp-s
1756 };
1757
1758 opp-900000000
1759 opp-h
1760 requi
1761 opp-s
1762 };
1763
1764 /* Speed bin
1765 opp-950000000
1766 opp-h
1767 requi
1768 opp-s
1769 };
1770
1771 opp-980000000
1772 opp-h
1773 requi
1774 opp-s
1775 };
1776 };
1777 };
1778
1779 gmu_wrapper: gmu@596a000 {
1780 compatible = "qcom,ad
1781 reg = <0x0 0x0596a000
1782 reg-names = "gmu";
1783 power-domains = <&gpu
1784 <&gpu
1785 power-domain-names =
1786 };
1787
1788 gpucc: clock-controller@59900
1789 compatible = "qcom,sm
1790 reg = <0x0 0x05990000
1791 clocks = <&rpmcc RPM_
1792 <&gcc GCC_GP
1793 <&gcc GCC_GP
1794 #clock-cells = <1>;
1795 #reset-cells = <1>;
1796 #power-domain-cells =
1797 };
1798
1799 adreno_smmu: iommu@59a0000 {
1800 compatible = "qcom,sm
1801 "qcom,sm
1802 reg = <0x0 0x059a0000
1803 interrupts = <GIC_SPI
1804 <GIC_SPI
1805 <GIC_SPI
1806 <GIC_SPI
1807 <GIC_SPI
1808 <GIC_SPI
1809 <GIC_SPI
1810 <GIC_SPI
1811 <GIC_SPI
1812
1813 clocks = <&gcc GCC_GP
1814 <&gpucc GPU_
1815 <&gcc GCC_GP
1816 clock-names = "mem",
1817 "hlos",
1818 "iface"
1819 power-domains = <&gpu
1820
1821 #global-interrupts =
1822 #iommu-cells = <2>;
1823 };
1824
1825 mdss: display-subsystem@5e000
1826 compatible = "qcom,sm
1827 reg = <0x0 0x05e00000
1828 reg-names = "mdss";
1829
1830 power-domains = <&dis
1831
1832 clocks = <&gcc GCC_DI
1833 <&gcc GCC_DI
1834 <&dispcc DIS
1835
1836 interrupts = <GIC_SPI
1837 interrupt-controller;
1838 #interrupt-cells = <1
1839
1840 iommus = <&apps_smmu
1841 <&apps_smmu
1842
1843 interconnects = <&mmr
1844 &bim
1845 <&bim
1846 &con
1847 interconnect-names =
1848
1849
1850 #address-cells = <2>;
1851 #size-cells = <2>;
1852 ranges;
1853
1854 status = "disabled";
1855
1856 mdp: display-controll
1857 compatible =
1858 reg = <0x0 0x
1859 <0x0 0x
1860 reg-names = "
1861
1862 clocks = <&gc
1863 <&di
1864 <&di
1865 <&di
1866 <&di
1867 <&di
1868 clock-names =
1869
1870
1871
1872
1873
1874
1875 operating-poi
1876 power-domains
1877
1878 interrupt-par
1879 interrupts =
1880
1881 ports {
1882 #addr
1883 #size
1884
1885 port@
1886
1887
1888
1889
1890 };
1891 };
1892
1893 mdp_opp_table
1894 compa
1895
1896 opp-1
1897
1898
1899 };
1900
1901 opp-1
1902
1903
1904 };
1905
1906 opp-2
1907
1908
1909 };
1910
1911 opp-3
1912
1913
1914 };
1915
1916 opp-3
1917
1918
1919 };
1920 };
1921 };
1922
1923 mdss_dsi0: dsi@5e9400
1924 compatible =
1925 reg = <0x0 0x
1926 reg-names = "
1927
1928 interrupt-par
1929 interrupts =
1930
1931 clocks = <&di
1932 <&di
1933 <&di
1934 <&di
1935 <&di
1936 <&gc
1937 clock-names =
1938
1939
1940
1941
1942
1943
1944 assigned-cloc
1945
1946 assigned-cloc
1947
1948 operating-poi
1949 power-domains
1950 phys = <&mdss
1951
1952 #address-cell
1953 #size-cells =
1954
1955 status = "dis
1956
1957 ports {
1958 #addr
1959 #size
1960
1961 port@
1962
1963
1964
1965
1966 };
1967
1968 port@
1969
1970
1971
1972 };
1973 };
1974
1975 dsi_opp_table
1976 compa
1977
1978 opp-1
1979
1980
1981 };
1982
1983 opp-1
1984
1985
1986 };
1987
1988 opp-1
1989
1990
1991 };
1992 };
1993 };
1994
1995 mdss_dsi0_phy: phy@5e
1996 compatible =
1997 reg = <0x0 0x
1998 <0x0 0x
1999 <0x0 0x
2000 reg-names = "
2001 "
2002 "
2003
2004 #clock-cells
2005 #phy-cells =
2006
2007 clocks = <&di
2008 <&rp
2009 clock-names =
2010
2011 status = "dis
2012 };
2013 };
2014
2015 dispcc: clock-controller@5f00
2016 compatible = "qcom,sm
2017 reg = <0x0 0x05f00000
2018 clocks = <&rpmcc RPM_
2019 <&sleep_clk>
2020 <&mdss_dsi0_
2021 <&mdss_dsi0_
2022 <&gcc GCC_DI
2023 #clock-cells = <1>;
2024 #reset-cells = <1>;
2025 #power-domain-cells =
2026 };
2027
2028 remoteproc_mpss: remoteproc@6
2029 compatible = "qcom,sm
2030 reg = <0x0 0x06080000
2031
2032 interrupts-extended =
2033
2034
2035
2036
2037
2038 interrupt-names = "wd
2039 "st
2040
2041 clocks = <&rpmcc RPM_
2042 clock-names = "xo";
2043
2044 power-domains = <&rpm
2045
2046 memory-region = <&pil
2047
2048 qcom,smem-states = <&
2049 qcom,smem-state-names
2050
2051 status = "disabled";
2052
2053 glink-edge {
2054 interrupts =
2055 label = "mpss
2056 qcom,remote-p
2057 mboxes = <&ap
2058 };
2059 };
2060
2061 stm@8002000 {
2062 compatible = "arm,cor
2063 reg = <0x0 0x08002000
2064 <0x0 0x0e280000
2065 reg-names = "stm-base
2066
2067 clocks = <&rpmcc RPM_
2068 clock-names = "apb_pc
2069
2070 status = "disabled";
2071
2072 out-ports {
2073 port {
2074 stm_o
2075
2076 };
2077 };
2078 };
2079 };
2080
2081 cti0: cti@8010000 {
2082 compatible = "arm,cor
2083 reg = <0x0 0x08010000
2084
2085 clocks = <&rpmcc RPM_
2086 clock-names = "apb_pc
2087
2088 status = "disabled";
2089 };
2090
2091 cti1: cti@8011000 {
2092 compatible = "arm,cor
2093 reg = <0x0 0x08011000
2094
2095 clocks = <&rpmcc RPM_
2096 clock-names = "apb_pc
2097
2098 status = "disabled";
2099 };
2100
2101 cti2: cti@8012000 {
2102 compatible = "arm,cor
2103 reg = <0x0 0x08012000
2104
2105 clocks = <&rpmcc RPM_
2106 clock-names = "apb_pc
2107
2108 status = "disabled";
2109 };
2110
2111 cti3: cti@8013000 {
2112 compatible = "arm,cor
2113 reg = <0x0 0x08013000
2114
2115 clocks = <&rpmcc RPM_
2116 clock-names = "apb_pc
2117
2118 status = "disabled";
2119 };
2120
2121 cti4: cti@8014000 {
2122 compatible = "arm,cor
2123 reg = <0x0 0x08014000
2124
2125 clocks = <&rpmcc RPM_
2126 clock-names = "apb_pc
2127
2128 status = "disabled";
2129 };
2130
2131 cti5: cti@8015000 {
2132 compatible = "arm,cor
2133 reg = <0x0 0x08015000
2134
2135 clocks = <&rpmcc RPM_
2136 clock-names = "apb_pc
2137
2138 status = "disabled";
2139 };
2140
2141 cti6: cti@8016000 {
2142 compatible = "arm,cor
2143 reg = <0x0 0x08016000
2144
2145 clocks = <&rpmcc RPM_
2146 clock-names = "apb_pc
2147
2148 status = "disabled";
2149 };
2150
2151 cti7: cti@8017000 {
2152 compatible = "arm,cor
2153 reg = <0x0 0x08017000
2154
2155 clocks = <&rpmcc RPM_
2156 clock-names = "apb_pc
2157
2158 status = "disabled";
2159 };
2160
2161 cti8: cti@8018000 {
2162 compatible = "arm,cor
2163 reg = <0x0 0x08018000
2164
2165 clocks = <&rpmcc RPM_
2166 clock-names = "apb_pc
2167
2168 status = "disabled";
2169 };
2170
2171 cti9: cti@8019000 {
2172 compatible = "arm,cor
2173 reg = <0x0 0x08019000
2174
2175 clocks = <&rpmcc RPM_
2176 clock-names = "apb_pc
2177
2178 status = "disabled";
2179 };
2180
2181 cti10: cti@801a000 {
2182 compatible = "arm,cor
2183 reg = <0x0 0x0801a000
2184
2185 clocks = <&rpmcc RPM_
2186 clock-names = "apb_pc
2187
2188 status = "disabled";
2189 };
2190
2191 cti11: cti@801b000 {
2192 compatible = "arm,cor
2193 reg = <0x0 0x0801b000
2194
2195 clocks = <&rpmcc RPM_
2196 clock-names = "apb_pc
2197
2198 status = "disabled";
2199 };
2200
2201 cti12: cti@801c000 {
2202 compatible = "arm,cor
2203 reg = <0x0 0x0801c000
2204
2205 clocks = <&rpmcc RPM_
2206 clock-names = "apb_pc
2207
2208 status = "disabled";
2209 };
2210
2211 cti13: cti@801d000 {
2212 compatible = "arm,cor
2213 reg = <0x0 0x0801d000
2214
2215 clocks = <&rpmcc RPM_
2216 clock-names = "apb_pc
2217
2218 status = "disabled";
2219 };
2220
2221 cti14: cti@801e000 {
2222 compatible = "arm,cor
2223 reg = <0x0 0x0801e000
2224
2225 clocks = <&rpmcc RPM_
2226 clock-names = "apb_pc
2227
2228 status = "disabled";
2229 };
2230
2231 cti15: cti@801f000 {
2232 compatible = "arm,cor
2233 reg = <0x0 0x0801f000
2234
2235 clocks = <&rpmcc RPM_
2236 clock-names = "apb_pc
2237
2238 status = "disabled";
2239 };
2240
2241 replicator@8046000 {
2242 compatible = "arm,cor
2243 reg = <0x0 0x08046000
2244
2245 clocks = <&rpmcc RPM_
2246 clock-names = "apb_pc
2247
2248 status = "disabled";
2249
2250 out-ports {
2251 port {
2252 repli
2253
2254 };
2255 };
2256 };
2257
2258 in-ports {
2259 port {
2260 repli
2261
2262 };
2263 };
2264 };
2265 };
2266
2267 etf@8047000 {
2268 compatible = "arm,cor
2269 reg = <0x0 0x08047000
2270
2271 clocks = <&rpmcc RPM_
2272 clock-names = "apb_pc
2273
2274 status = "disabled";
2275
2276 in-ports {
2277 port {
2278 etf_i
2279
2280 };
2281 };
2282 };
2283
2284 out-ports {
2285 port {
2286 etf_o
2287
2288 };
2289 };
2290 };
2291 };
2292
2293 etr@8048000 {
2294 compatible = "arm,cor
2295 reg = <0x0 0x08048000
2296
2297 clocks = <&rpmcc RPM_
2298 clock-names = "apb_pc
2299
2300 status = "disabled";
2301
2302 in-ports {
2303 port {
2304 etr_i
2305
2306 };
2307 };
2308 };
2309 };
2310
2311 funnel@8041000 {
2312 compatible = "arm,cor
2313 reg = <0x0 0x08041000
2314
2315 clocks = <&rpmcc RPM_
2316 clock-names = "apb_pc
2317
2318 status = "disabled";
2319
2320 out-ports {
2321 port {
2322 funne
2323
2324 };
2325 };
2326 };
2327
2328 in-ports {
2329 port {
2330 funne
2331
2332 };
2333 };
2334 };
2335 };
2336
2337 funnel@8042000 {
2338 compatible = "arm,cor
2339 reg = <0x0 0x08042000
2340
2341 clocks = <&rpmcc RPM_
2342 clock-names = "apb_pc
2343
2344 status = "disabled";
2345
2346 out-ports {
2347 port {
2348 funne
2349
2350 };
2351 };
2352 };
2353
2354 in-ports {
2355 port {
2356 funne
2357
2358 };
2359 };
2360 };
2361 };
2362
2363 funnel@8045000 {
2364 compatible = "arm,cor
2365 reg = <0x0 0x08045000
2366
2367 clocks = <&rpmcc RPM_
2368 clock-names = "apb_pc
2369
2370 status = "disabled";
2371
2372 out-ports {
2373 port {
2374 merge
2375
2376 };
2377 };
2378 };
2379
2380 in-ports {
2381 #address-cell
2382 #size-cells =
2383
2384 port@0 {
2385 reg =
2386 merge
2387
2388 };
2389 };
2390
2391 port@1 {
2392 reg =
2393 merge
2394
2395 };
2396 };
2397 };
2398 };
2399
2400 etm@9040000 {
2401 compatible = "arm,cor
2402 reg = <0x0 0x09040000
2403
2404 clocks = <&rpmcc RPM_
2405 clock-names = "apb_pc
2406 arm,coresight-loses-c
2407
2408 cpu = <&CPU0>;
2409
2410 status = "disabled";
2411
2412 out-ports {
2413 port {
2414 etm0_
2415
2416 };
2417 };
2418 };
2419 };
2420
2421 etm@9140000 {
2422 compatible = "arm,cor
2423 reg = <0x0 0x09140000
2424
2425 clocks = <&rpmcc RPM_
2426 clock-names = "apb_pc
2427 arm,coresight-loses-c
2428
2429 cpu = <&CPU1>;
2430
2431 status = "disabled";
2432
2433 out-ports {
2434 port {
2435 etm1_
2436
2437 };
2438 };
2439 };
2440 };
2441
2442 etm@9240000 {
2443 compatible = "arm,cor
2444 reg = <0x0 0x09240000
2445
2446 clocks = <&rpmcc RPM_
2447 clock-names = "apb_pc
2448 arm,coresight-loses-c
2449
2450 cpu = <&CPU2>;
2451
2452 status = "disabled";
2453
2454 out-ports {
2455 port {
2456 etm2_
2457
2458 };
2459 };
2460 };
2461 };
2462
2463 etm@9340000 {
2464 compatible = "arm,cor
2465 reg = <0x0 0x09340000
2466
2467 clocks = <&rpmcc RPM_
2468 clock-names = "apb_pc
2469 arm,coresight-loses-c
2470
2471 cpu = <&CPU3>;
2472
2473 status = "disabled";
2474
2475 out-ports {
2476 port {
2477 etm3_
2478
2479 };
2480 };
2481 };
2482 };
2483
2484 etm@9440000 {
2485 compatible = "arm,cor
2486 reg = <0x0 0x09440000
2487
2488 clocks = <&rpmcc RPM_
2489 clock-names = "apb_pc
2490 arm,coresight-loses-c
2491
2492 cpu = <&CPU4>;
2493
2494 status = "disabled";
2495
2496 out-ports {
2497 port {
2498 etm4_
2499
2500 };
2501 };
2502 };
2503 };
2504
2505 etm@9540000 {
2506 compatible = "arm,cor
2507 reg = <0x0 0x09540000
2508
2509 clocks = <&rpmcc RPM_
2510 clock-names = "apb_pc
2511 arm,coresight-loses-c
2512
2513 cpu = <&CPU5>;
2514
2515 status = "disabled";
2516
2517 out-ports {
2518 port {
2519 etm5_
2520
2521 };
2522 };
2523 };
2524 };
2525
2526 etm@9640000 {
2527 compatible = "arm,cor
2528 reg = <0x0 0x09640000
2529
2530 clocks = <&rpmcc RPM_
2531 clock-names = "apb_pc
2532 arm,coresight-loses-c
2533
2534 cpu = <&CPU6>;
2535
2536 status = "disabled";
2537
2538 out-ports {
2539 port {
2540 etm6_
2541
2542 };
2543 };
2544 };
2545 };
2546
2547 etm@9740000 {
2548 compatible = "arm,cor
2549 reg = <0x0 0x09740000
2550
2551 clocks = <&rpmcc RPM_
2552 clock-names = "apb_pc
2553 arm,coresight-loses-c
2554
2555 cpu = <&CPU7>;
2556
2557 status = "disabled";
2558
2559 out-ports {
2560 port {
2561 etm7_
2562
2563 };
2564 };
2565 };
2566 };
2567
2568 funnel@9800000 {
2569 compatible = "arm,cor
2570 reg = <0x0 0x09800000
2571
2572 clocks = <&rpmcc RPM_
2573 clock-names = "apb_pc
2574
2575 status = "disabled";
2576
2577 out-ports {
2578 port {
2579 funne
2580
2581 };
2582 };
2583 };
2584
2585 in-ports {
2586 #address-cell
2587 #size-cells =
2588
2589 port@0 {
2590 reg =
2591 funne
2592
2593 };
2594 };
2595
2596 port@1 {
2597 reg =
2598 funne
2599
2600 };
2601 };
2602
2603 port@2 {
2604 reg =
2605 funne
2606
2607 };
2608 };
2609
2610 port@3 {
2611 reg =
2612 funne
2613
2614 };
2615 };
2616
2617 port@4 {
2618 reg =
2619 funne
2620
2621 };
2622 };
2623
2624 port@5 {
2625 reg =
2626 funne
2627
2628 };
2629 };
2630
2631 port@6 {
2632 reg =
2633 funne
2634
2635 };
2636 };
2637
2638 port@7 {
2639 reg =
2640 funne
2641
2642 };
2643 };
2644 };
2645 };
2646
2647 funnel@9810000 {
2648 compatible = "arm,cor
2649 reg = <0x0 0x09810000
2650
2651 clocks = <&rpmcc RPM_
2652 clock-names = "apb_pc
2653
2654 status = "disabled";
2655
2656 out-ports {
2657 port {
2658 funne
2659
2660 };
2661 };
2662 };
2663
2664 in-ports {
2665 port {
2666 funne
2667
2668 };
2669 };
2670 };
2671 };
2672
2673 remoteproc_adsp: remoteproc@a
2674 compatible = "qcom,sm
2675 reg = <0x0 0x0ab00000
2676
2677 interrupts-extended =
2678
2679
2680
2681
2682 interrupt-names = "wd
2683 "ha
2684
2685 clocks = <&rpmcc RPM_
2686 clock-names = "xo";
2687
2688 power-domains = <&rpm
2689 <&rpm
2690
2691 memory-region = <&pil
2692
2693 qcom,smem-states = <&
2694 qcom,smem-state-names
2695
2696 status = "disabled";
2697
2698 glink-edge {
2699 interrupts =
2700 label = "lpas
2701 qcom,remote-p
2702 mboxes = <&ap
2703
2704 fastrpc {
2705 compa
2706 qcom,
2707 label
2708 qcom,
2709 #addr
2710 #size
2711
2712 compu
2713
2714
2715
2716 };
2717
2718 compu
2719
2720
2721
2722 };
2723
2724 compu
2725
2726
2727
2728 };
2729
2730 compu
2731
2732
2733
2734 };
2735
2736 compu
2737
2738
2739
2740 };
2741 };
2742 };
2743 };
2744
2745 remoteproc_cdsp: remoteproc@b
2746 compatible = "qcom,sm
2747 reg = <0x0 0x0b300000
2748
2749 interrupts-extended =
2750
2751
2752
2753
2754 interrupt-names = "wd
2755 "ha
2756
2757 clocks = <&rpmcc RPM_
2758 clock-names = "xo";
2759
2760 power-domains = <&rpm
2761
2762 memory-region = <&pil
2763
2764 qcom,smem-states = <&
2765 qcom,smem-state-names
2766
2767 status = "disabled";
2768
2769 glink-edge {
2770 interrupts =
2771 label = "cdsp
2772 qcom,remote-p
2773 mboxes = <&ap
2774
2775 fastrpc {
2776 compa
2777 qcom,
2778 label
2779 qcom,
2780 #addr
2781 #size
2782
2783 compu
2784
2785
2786
2787 };
2788
2789 compu
2790
2791
2792
2793 };
2794
2795 compu
2796
2797
2798
2799 };
2800
2801 compu
2802
2803
2804
2805 };
2806
2807 compu
2808
2809
2810
2811 };
2812
2813 compu
2814
2815
2816
2817 };
2818
2819 /* no
2820 };
2821 };
2822 };
2823
2824 apps_smmu: iommu@c600000 {
2825 compatible = "qcom,sm
2826 reg = <0x0 0x0c600000
2827 #iommu-cells = <2>;
2828 #global-interrupts =
2829
2830 interrupts = <GIC_SPI
2831 <GIC_SPI
2832 <GIC_SPI
2833 <GIC_SPI
2834 <GIC_SPI
2835 <GIC_SPI
2836 <GIC_SPI
2837 <GIC_SPI
2838 <GIC_SPI
2839 <GIC_SPI
2840 <GIC_SPI
2841 <GIC_SPI
2842 <GIC_SPI
2843 <GIC_SPI
2844 <GIC_SPI
2845 <GIC_SPI
2846 <GIC_SPI
2847 <GIC_SPI
2848 <GIC_SPI
2849 <GIC_SPI
2850 <GIC_SPI
2851 <GIC_SPI
2852 <GIC_SPI
2853 <GIC_SPI
2854 <GIC_SPI
2855 <GIC_SPI
2856 <GIC_SPI
2857 <GIC_SPI
2858 <GIC_SPI
2859 <GIC_SPI
2860 <GIC_SPI
2861 <GIC_SPI
2862 <GIC_SPI
2863 <GIC_SPI
2864 <GIC_SPI
2865 <GIC_SPI
2866 <GIC_SPI
2867 <GIC_SPI
2868 <GIC_SPI
2869 <GIC_SPI
2870 <GIC_SPI
2871 <GIC_SPI
2872 <GIC_SPI
2873 <GIC_SPI
2874 <GIC_SPI
2875 <GIC_SPI
2876 <GIC_SPI
2877 <GIC_SPI
2878 <GIC_SPI
2879 <GIC_SPI
2880 <GIC_SPI
2881 <GIC_SPI
2882 <GIC_SPI
2883 <GIC_SPI
2884 <GIC_SPI
2885 <GIC_SPI
2886 <GIC_SPI
2887 <GIC_SPI
2888 <GIC_SPI
2889 <GIC_SPI
2890 <GIC_SPI
2891 <GIC_SPI
2892 <GIC_SPI
2893 <GIC_SPI
2894 <GIC_SPI
2895 };
2896
2897 wifi: wifi@c800000 {
2898 compatible = "qcom,wc
2899 reg = <0x0 0x0c800000
2900 reg-names = "membase"
2901 memory-region = <&wla
2902 interrupts = <GIC_SPI
2903 <GIC_SPI
2904 <GIC_SPI
2905 <GIC_SPI
2906 <GIC_SPI
2907 <GIC_SPI
2908 <GIC_SPI
2909 <GIC_SPI
2910 <GIC_SPI
2911 <GIC_SPI
2912 <GIC_SPI
2913 <GIC_SPI
2914 iommus = <&apps_smmu
2915 qcom,msa-fixed-perm;
2916 status = "disabled";
2917 };
2918
2919 watchdog@f017000 {
2920 compatible = "qcom,ap
2921 reg = <0x0 0x0f017000
2922 clocks = <&sleep_clk>
2923 interrupts = <GIC_SPI
2924 };
2925
2926 apcs_glb: mailbox@f111000 {
2927 compatible = "qcom,sm
2928 "qcom,ms
2929 reg = <0x0 0x0f111000
2930
2931 #mbox-cells = <1>;
2932 };
2933
2934 timer@f120000 {
2935 compatible = "arm,arm
2936 reg = <0x0 0x0f120000
2937 #address-cells = <2>;
2938 #size-cells = <1>;
2939 ranges = <0x0 0x0 0x0
2940 clock-frequency = <19
2941
2942 frame@f121000 {
2943 reg = <0x0 0x
2944 frame-number
2945 interrupts =
2946
2947 };
2948
2949 frame@f123000 {
2950 reg = <0x0 0x
2951 frame-number
2952 interrupts =
2953 status = "dis
2954 };
2955
2956 frame@f124000 {
2957 reg = <0x0 0x
2958 frame-number
2959 interrupts =
2960 status = "dis
2961 };
2962
2963 frame@f125000 {
2964 reg = <0x0 0x
2965 frame-number
2966 interrupts =
2967 status = "dis
2968 };
2969
2970 frame@f126000 {
2971 reg = <0x0 0x
2972 frame-number
2973 interrupts =
2974 status = "dis
2975 };
2976
2977 frame@f127000 {
2978 reg = <0x0 0x
2979 frame-number
2980 interrupts =
2981 status = "dis
2982 };
2983
2984 frame@f128000 {
2985 reg = <0x0 0x
2986 frame-number
2987 interrupts =
2988 status = "dis
2989 };
2990 };
2991
2992 intc: interrupt-controller@f2
2993 compatible = "arm,gic
2994 reg = <0x0 0x0f200000
2995 <0x0 0x0f300000
2996 #interrupt-cells = <3
2997 interrupt-controller;
2998 interrupt-parent = <&
2999 #redistributor-region
3000 redistributor-stride
3001 interrupts = <GIC_PPI
3002 };
3003
3004 cpufreq_hw: cpufreq@f521000 {
3005 compatible = "qcom,sm
3006 reg = <0x0 0x0f521000
3007 <0x0 0x0f523000
3008
3009 reg-names = "freq-dom
3010 clocks = <&rpmcc RPM_
3011 clock-names = "xo", "
3012
3013 #freq-domain-cells =
3014 #clock-cells = <1>;
3015 };
3016 };
3017
3018 thermal-zones {
3019 mapss-thermal {
3020 thermal-sensors = <&t
3021
3022 trips {
3023 trip-point0 {
3024 tempe
3025 hyste
3026 type
3027 };
3028
3029 trip-point1 {
3030 tempe
3031 hyste
3032 type
3033 };
3034 };
3035 };
3036
3037 cdsp-hvx-thermal {
3038 thermal-sensors = <&t
3039
3040 trips {
3041 trip-point0 {
3042 tempe
3043 hyste
3044 type
3045 };
3046
3047 trip-point1 {
3048 tempe
3049 hyste
3050 type
3051 };
3052 };
3053 };
3054
3055 wlan-thermal {
3056 thermal-sensors = <&t
3057
3058 trips {
3059 trip-point0 {
3060 tempe
3061 hyste
3062 type
3063 };
3064
3065 trip-point1 {
3066 tempe
3067 hyste
3068 type
3069 };
3070 };
3071 };
3072
3073 camera-thermal {
3074 thermal-sensors = <&t
3075
3076 trips {
3077 trip-point0 {
3078 tempe
3079 hyste
3080 type
3081 };
3082
3083 trip-point1 {
3084 tempe
3085 hyste
3086 type
3087 };
3088 };
3089 };
3090
3091 video-thermal {
3092 thermal-sensors = <&t
3093
3094 trips {
3095 trip-point0 {
3096 tempe
3097 hyste
3098 type
3099 };
3100
3101 trip-point1 {
3102 tempe
3103 hyste
3104 type
3105 };
3106 };
3107 };
3108
3109 modem1-thermal {
3110 thermal-sensors = <&t
3111
3112 trips {
3113 trip-point0 {
3114 tempe
3115 hyste
3116 type
3117 };
3118
3119 trip-point1 {
3120 tempe
3121 hyste
3122 type
3123 };
3124 };
3125 };
3126
3127 cpu4-thermal {
3128 thermal-sensors = <&t
3129
3130 trips {
3131 cpu4_alert0:
3132 tempe
3133 hyste
3134 type
3135 };
3136
3137 cpu4_alert1:
3138 tempe
3139 hyste
3140 type
3141 };
3142
3143 cpu4_crit: cp
3144 tempe
3145 hyste
3146 type
3147 };
3148 };
3149 };
3150
3151 cpu5-thermal {
3152 thermal-sensors = <&t
3153
3154 trips {
3155 cpu5_alert0:
3156 tempe
3157 hyste
3158 type
3159 };
3160
3161 cpu5_alert1:
3162 tempe
3163 hyste
3164 type
3165 };
3166
3167 cpu5_crit: cp
3168 tempe
3169 hyste
3170 type
3171 };
3172 };
3173 };
3174
3175 cpu6-thermal {
3176 thermal-sensors = <&t
3177
3178 trips {
3179 cpu6_alert0:
3180 tempe
3181 hyste
3182 type
3183 };
3184
3185 cpu6_alert1:
3186 tempe
3187 hyste
3188 type
3189 };
3190
3191 cpu6_crit: cp
3192 tempe
3193 hyste
3194 type
3195 };
3196 };
3197 };
3198
3199 cpu7-thermal {
3200 thermal-sensors = <&t
3201
3202 trips {
3203 cpu7_alert0:
3204 tempe
3205 hyste
3206 type
3207 };
3208
3209 cpu7_alert1:
3210 tempe
3211 hyste
3212 type
3213 };
3214
3215 cpu7_crit: cp
3216 tempe
3217 hyste
3218 type
3219 };
3220 };
3221 };
3222
3223 cpu45-thermal {
3224 thermal-sensors = <&t
3225
3226 trips {
3227 cpu45_alert0:
3228 tempe
3229 hyste
3230 type
3231 };
3232
3233 cpu45_alert1:
3234 tempe
3235 hyste
3236 type
3237 };
3238
3239 cpu45_crit: c
3240 tempe
3241 hyste
3242 type
3243 };
3244 };
3245 };
3246
3247 cpu67-thermal {
3248 thermal-sensors = <&t
3249
3250 trips {
3251 cpu67_alert0:
3252 tempe
3253 hyste
3254 type
3255 };
3256
3257 cpu67_alert1:
3258 tempe
3259 hyste
3260 type
3261 };
3262
3263 cpu67_crit: c
3264 tempe
3265 hyste
3266 type
3267 };
3268 };
3269 };
3270
3271 cpu0123-thermal {
3272 thermal-sensors = <&t
3273
3274 trips {
3275 cpu0123_alert
3276 tempe
3277 hyste
3278 type
3279 };
3280
3281 cpu0123_alert
3282 tempe
3283 hyste
3284 type
3285 };
3286
3287 cpu0123_crit:
3288 tempe
3289 hyste
3290 type
3291 };
3292 };
3293 };
3294
3295 modem0-thermal {
3296 thermal-sensors = <&t
3297
3298 trips {
3299 trip-point0 {
3300 tempe
3301 hyste
3302 type
3303 };
3304
3305 trip-point1 {
3306 tempe
3307 hyste
3308 type
3309 };
3310 };
3311 };
3312
3313 display-thermal {
3314 thermal-sensors = <&t
3315
3316 trips {
3317 trip-point0 {
3318 tempe
3319 hyste
3320 type
3321 };
3322
3323 trip-point1 {
3324 tempe
3325 hyste
3326 type
3327 };
3328 };
3329 };
3330
3331 gpu-thermal {
3332 polling-delay-passive
3333
3334 thermal-sensors = <&t
3335
3336 cooling-maps {
3337 map0 {
3338 trip
3339 cooli
3340 };
3341 };
3342
3343 trips {
3344 gpu_alert0: t
3345 tempe
3346 hyste
3347 type
3348 };
3349
3350 trip-point1 {
3351 tempe
3352 hyste
3353 type
3354 };
3355 };
3356 };
3357 };
3358
3359 timer {
3360 compatible = "arm,armv8-timer
3361 interrupts = <GIC_PPI 1 (GIC_
3362 <GIC_PPI 2 (GIC_
3363 <GIC_PPI 3 (GIC_
3364 <GIC_PPI 0 (GIC_
3365 };
3366 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.