1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright (c) 2019 Fuzhou Rockchip Electron
4 *
5 */
6
7 #include <dt-bindings/clock/rk3308-cru.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm
10 #include <dt-bindings/interrupt-controller/irq
11 #include <dt-bindings/pinctrl/rockchip.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h
13 #include <dt-bindings/thermal/thermal.h>
14
15 / {
16 compatible = "rockchip,rk3308";
17
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
21
22 aliases {
23 gpio0 = &gpio0;
24 gpio1 = &gpio1;
25 gpio2 = &gpio2;
26 gpio3 = &gpio3;
27 gpio4 = &gpio4;
28 i2c0 = &i2c0;
29 i2c1 = &i2c1;
30 i2c2 = &i2c2;
31 i2c3 = &i2c3;
32 serial0 = &uart0;
33 serial1 = &uart1;
34 serial2 = &uart2;
35 serial3 = &uart3;
36 serial4 = &uart4;
37 spi0 = &spi0;
38 spi1 = &spi1;
39 spi2 = &spi2;
40 };
41
42 cpus {
43 #address-cells = <2>;
44 #size-cells = <0>;
45
46 cpu0: cpu@0 {
47 device_type = "cpu";
48 compatible = "arm,cort
49 reg = <0x0 0x0>;
50 enable-method = "psci"
51 clocks = <&cru ARMCLK>
52 #cooling-cells = <2>;
53 dynamic-power-coeffici
54 operating-points-v2 =
55 cpu-idle-states = <&CP
56 next-level-cache = <&l
57 };
58
59 cpu1: cpu@1 {
60 device_type = "cpu";
61 compatible = "arm,cort
62 reg = <0x0 0x1>;
63 enable-method = "psci"
64 operating-points-v2 =
65 cpu-idle-states = <&CP
66 next-level-cache = <&l
67 };
68
69 cpu2: cpu@2 {
70 device_type = "cpu";
71 compatible = "arm,cort
72 reg = <0x0 0x2>;
73 enable-method = "psci"
74 operating-points-v2 =
75 cpu-idle-states = <&CP
76 next-level-cache = <&l
77 };
78
79 cpu3: cpu@3 {
80 device_type = "cpu";
81 compatible = "arm,cort
82 reg = <0x0 0x3>;
83 enable-method = "psci"
84 operating-points-v2 =
85 cpu-idle-states = <&CP
86 next-level-cache = <&l
87 };
88
89 idle-states {
90 entry-method = "psci";
91
92 CPU_SLEEP: cpu-sleep {
93 compatible = "
94 local-timer-st
95 arm,psci-suspe
96 entry-latency-
97 exit-latency-u
98 min-residency-
99 };
100 };
101
102 l2: l2-cache {
103 compatible = "cache";
104 cache-level = <2>;
105 cache-unified;
106 };
107 };
108
109 cpu0_opp_table: opp-table-0 {
110 compatible = "operating-points
111 opp-shared;
112
113 opp-408000000 {
114 opp-hz = /bits/ 64 <40
115 opp-microvolt = <95000
116 clock-latency-ns = <40
117 opp-suspend;
118 };
119 opp-600000000 {
120 opp-hz = /bits/ 64 <60
121 opp-microvolt = <95000
122 clock-latency-ns = <40
123 };
124 opp-816000000 {
125 opp-hz = /bits/ 64 <81
126 opp-microvolt = <10250
127 clock-latency-ns = <40
128 };
129 opp-1008000000 {
130 opp-hz = /bits/ 64 <10
131 opp-microvolt = <11250
132 clock-latency-ns = <40
133 };
134 };
135
136 arm-pmu {
137 compatible = "arm,cortex-a35-p
138 interrupts = <GIC_SPI 83 IRQ_T
139 <GIC_SPI 84 IRQ_T
140 <GIC_SPI 85 IRQ_T
141 <GIC_SPI 86 IRQ_T
142 interrupt-affinity = <&cpu0>,
143 };
144
145 mac_clkin: external-mac-clock {
146 compatible = "fixed-clock";
147 clock-frequency = <50000000>;
148 clock-output-names = "mac_clki
149 #clock-cells = <0>;
150 };
151
152 psci {
153 compatible = "arm,psci-1.0";
154 method = "smc";
155 };
156
157 timer {
158 compatible = "arm,armv8-timer"
159 interrupts = <GIC_PPI 13 (GIC_
160 <GIC_PPI 14 (GIC_
161 <GIC_PPI 11 (GIC_
162 <GIC_PPI 10 (GIC_
163 };
164
165 xin24m: xin24m {
166 compatible = "fixed-clock";
167 #clock-cells = <0>;
168 clock-frequency = <24000000>;
169 clock-output-names = "xin24m";
170 };
171
172 grf: grf@ff000000 {
173 compatible = "rockchip,rk3308-
174 reg = <0x0 0xff000000 0x0 0x08
175
176 io_domains: io-domains {
177 compatible = "rockchip
178 status = "disabled";
179 };
180
181 reboot-mode {
182 compatible = "syscon-r
183 offset = <0x500>;
184 mode-bootloader = <BOO
185 mode-loader = <BOOT_BL
186 mode-normal = <BOOT_NO
187 mode-recovery = <BOOT_
188 mode-fastboot = <BOOT_
189 };
190 };
191
192 usb2phy_grf: syscon@ff008000 {
193 compatible = "rockchip,rk3308-
194 reg = <0x0 0xff008000 0x0 0x40
195 #address-cells = <1>;
196 #size-cells = <1>;
197
198 u2phy: usb2phy@100 {
199 compatible = "rockchip
200 reg = <0x100 0x10>;
201 assigned-clocks = <&cr
202 assigned-clock-parents
203 clocks = <&cru SCLK_US
204 clock-names = "phyclk"
205 clock-output-names = "
206 #clock-cells = <0>;
207 status = "disabled";
208
209 u2phy_otg: otg-port {
210 interrupts = <
211 <
212 <
213 interrupt-name
214
215 #phy-cells = <
216 status = "disa
217 };
218
219 u2phy_host: host-port
220 interrupts = <
221 interrupt-name
222 #phy-cells = <
223 status = "disa
224 };
225 };
226 };
227
228 detect_grf: syscon@ff00b000 {
229 compatible = "rockchip,rk3308-
230 reg = <0x0 0xff00b000 0x0 0x10
231 #address-cells = <1>;
232 #size-cells = <1>;
233 };
234
235 core_grf: syscon@ff00c000 {
236 compatible = "rockchip,rk3308-
237 reg = <0x0 0xff00c000 0x0 0x10
238 #address-cells = <1>;
239 #size-cells = <1>;
240 };
241
242 i2c0: i2c@ff040000 {
243 compatible = "rockchip,rk3308-
244 reg = <0x0 0xff040000 0x0 0x10
245 clocks = <&cru SCLK_I2C0>, <&c
246 clock-names = "i2c", "pclk";
247 interrupts = <GIC_SPI 11 IRQ_T
248 pinctrl-names = "default";
249 pinctrl-0 = <&i2c0_xfer>;
250 #address-cells = <1>;
251 #size-cells = <0>;
252 status = "disabled";
253 };
254
255 i2c1: i2c@ff050000 {
256 compatible = "rockchip,rk3308-
257 reg = <0x0 0xff050000 0x0 0x10
258 clocks = <&cru SCLK_I2C1>, <&c
259 clock-names = "i2c", "pclk";
260 interrupts = <GIC_SPI 12 IRQ_T
261 pinctrl-names = "default";
262 pinctrl-0 = <&i2c1_xfer>;
263 #address-cells = <1>;
264 #size-cells = <0>;
265 status = "disabled";
266 };
267
268 i2c2: i2c@ff060000 {
269 compatible = "rockchip,rk3308-
270 reg = <0x0 0xff060000 0x0 0x10
271 clocks = <&cru SCLK_I2C2>, <&c
272 clock-names = "i2c", "pclk";
273 interrupts = <GIC_SPI 13 IRQ_T
274 pinctrl-names = "default";
275 pinctrl-0 = <&i2c2_xfer>;
276 #address-cells = <1>;
277 #size-cells = <0>;
278 status = "disabled";
279 };
280
281 i2c3: i2c@ff070000 {
282 compatible = "rockchip,rk3308-
283 reg = <0x0 0xff070000 0x0 0x10
284 clocks = <&cru SCLK_I2C3>, <&c
285 clock-names = "i2c", "pclk";
286 interrupts = <GIC_SPI 14 IRQ_T
287 pinctrl-names = "default";
288 pinctrl-0 = <&i2c3m0_xfer>;
289 #address-cells = <1>;
290 #size-cells = <0>;
291 status = "disabled";
292 };
293
294 wdt: watchdog@ff080000 {
295 compatible = "rockchip,rk3308-
296 reg = <0x0 0xff080000 0x0 0x10
297 clocks = <&cru PCLK_WDT>;
298 interrupts = <GIC_SPI 10 IRQ_T
299 status = "disabled";
300 };
301
302 uart0: serial@ff0a0000 {
303 compatible = "rockchip,rk3308-
304 reg = <0x0 0xff0a0000 0x0 0x10
305 interrupts = <GIC_SPI 18 IRQ_T
306 clocks = <&cru SCLK_UART0>, <&
307 clock-names = "baudclk", "apb_
308 reg-shift = <2>;
309 reg-io-width = <4>;
310 pinctrl-names = "default";
311 pinctrl-0 = <&uart0_xfer &uart
312 status = "disabled";
313 };
314
315 uart1: serial@ff0b0000 {
316 compatible = "rockchip,rk3308-
317 reg = <0x0 0xff0b0000 0x0 0x10
318 interrupts = <GIC_SPI 19 IRQ_T
319 clocks = <&cru SCLK_UART1>, <&
320 clock-names = "baudclk", "apb_
321 reg-shift = <2>;
322 reg-io-width = <4>;
323 pinctrl-names = "default";
324 pinctrl-0 = <&uart1_xfer &uart
325 status = "disabled";
326 };
327
328 uart2: serial@ff0c0000 {
329 compatible = "rockchip,rk3308-
330 reg = <0x0 0xff0c0000 0x0 0x10
331 interrupts = <GIC_SPI 20 IRQ_T
332 clocks = <&cru SCLK_UART2>, <&
333 clock-names = "baudclk", "apb_
334 reg-shift = <2>;
335 reg-io-width = <4>;
336 pinctrl-names = "default";
337 pinctrl-0 = <&uart2m0_xfer>;
338 status = "disabled";
339 };
340
341 uart3: serial@ff0d0000 {
342 compatible = "rockchip,rk3308-
343 reg = <0x0 0xff0d0000 0x0 0x10
344 interrupts = <GIC_SPI 21 IRQ_T
345 clocks = <&cru SCLK_UART3>, <&
346 clock-names = "baudclk", "apb_
347 reg-shift = <2>;
348 reg-io-width = <4>;
349 pinctrl-names = "default";
350 pinctrl-0 = <&uart3_xfer>;
351 status = "disabled";
352 };
353
354 uart4: serial@ff0e0000 {
355 compatible = "rockchip,rk3308-
356 reg = <0x0 0xff0e0000 0x0 0x10
357 interrupts = <GIC_SPI 22 IRQ_T
358 clocks = <&cru SCLK_UART4>, <&
359 clock-names = "baudclk", "apb_
360 reg-shift = <2>;
361 reg-io-width = <4>;
362 pinctrl-names = "default";
363 pinctrl-0 = <&uart4_xfer &uart
364 status = "disabled";
365 };
366
367 spi0: spi@ff120000 {
368 compatible = "rockchip,rk3308-
369 reg = <0x0 0xff120000 0x0 0x10
370 interrupts = <GIC_SPI 15 IRQ_T
371 #address-cells = <1>;
372 #size-cells = <0>;
373 clocks = <&cru SCLK_SPI0>, <&c
374 clock-names = "spiclk", "apb_p
375 dmas = <&dmac0 0>, <&dmac0 1>;
376 dma-names = "tx", "rx";
377 pinctrl-names = "default";
378 pinctrl-0 = <&spi0_clk &spi0_c
379 status = "disabled";
380 };
381
382 spi1: spi@ff130000 {
383 compatible = "rockchip,rk3308-
384 reg = <0x0 0xff130000 0x0 0x10
385 interrupts = <GIC_SPI 16 IRQ_T
386 #address-cells = <1>;
387 #size-cells = <0>;
388 clocks = <&cru SCLK_SPI1>, <&c
389 clock-names = "spiclk", "apb_p
390 dmas = <&dmac0 2>, <&dmac0 3>;
391 dma-names = "tx", "rx";
392 pinctrl-names = "default";
393 pinctrl-0 = <&spi1_clk &spi1_c
394 status = "disabled";
395 };
396
397 spi2: spi@ff140000 {
398 compatible = "rockchip,rk3308-
399 reg = <0x0 0xff140000 0x0 0x10
400 interrupts = <GIC_SPI 17 IRQ_T
401 #address-cells = <1>;
402 #size-cells = <0>;
403 clocks = <&cru SCLK_SPI2>, <&c
404 clock-names = "spiclk", "apb_p
405 dmas = <&dmac1 16>, <&dmac1 17
406 dma-names = "tx", "rx";
407 pinctrl-names = "default";
408 pinctrl-0 = <&spi2_clk &spi2_c
409 status = "disabled";
410 };
411
412 pwm8: pwm@ff160000 {
413 compatible = "rockchip,rk3308-
414 reg = <0x0 0xff160000 0x0 0x10
415 clocks = <&cru SCLK_PWM2>, <&c
416 clock-names = "pwm", "pclk";
417 pinctrl-names = "default";
418 pinctrl-0 = <&pwm8_pin>;
419 #pwm-cells = <3>;
420 status = "disabled";
421 };
422
423 pwm9: pwm@ff160010 {
424 compatible = "rockchip,rk3308-
425 reg = <0x0 0xff160010 0x0 0x10
426 clocks = <&cru SCLK_PWM2>, <&c
427 clock-names = "pwm", "pclk";
428 pinctrl-names = "default";
429 pinctrl-0 = <&pwm9_pin>;
430 #pwm-cells = <3>;
431 status = "disabled";
432 };
433
434 pwm10: pwm@ff160020 {
435 compatible = "rockchip,rk3308-
436 reg = <0x0 0xff160020 0x0 0x10
437 clocks = <&cru SCLK_PWM2>, <&c
438 clock-names = "pwm", "pclk";
439 pinctrl-names = "default";
440 pinctrl-0 = <&pwm10_pin>;
441 #pwm-cells = <3>;
442 status = "disabled";
443 };
444
445 pwm11: pwm@ff160030 {
446 compatible = "rockchip,rk3308-
447 reg = <0x0 0xff160030 0x0 0x10
448 clocks = <&cru SCLK_PWM2>, <&c
449 clock-names = "pwm", "pclk";
450 pinctrl-names = "default";
451 pinctrl-0 = <&pwm11_pin>;
452 #pwm-cells = <3>;
453 status = "disabled";
454 };
455
456 pwm4: pwm@ff170000 {
457 compatible = "rockchip,rk3308-
458 reg = <0x0 0xff170000 0x0 0x10
459 clocks = <&cru SCLK_PWM1>, <&c
460 clock-names = "pwm", "pclk";
461 pinctrl-names = "default";
462 pinctrl-0 = <&pwm4_pin>;
463 #pwm-cells = <3>;
464 status = "disabled";
465 };
466
467 pwm5: pwm@ff170010 {
468 compatible = "rockchip,rk3308-
469 reg = <0x0 0xff170010 0x0 0x10
470 clocks = <&cru SCLK_PWM1>, <&c
471 clock-names = "pwm", "pclk";
472 pinctrl-names = "default";
473 pinctrl-0 = <&pwm5_pin>;
474 #pwm-cells = <3>;
475 status = "disabled";
476 };
477
478 pwm6: pwm@ff170020 {
479 compatible = "rockchip,rk3308-
480 reg = <0x0 0xff170020 0x0 0x10
481 clocks = <&cru SCLK_PWM1>, <&c
482 clock-names = "pwm", "pclk";
483 pinctrl-names = "default";
484 pinctrl-0 = <&pwm6_pin>;
485 #pwm-cells = <3>;
486 status = "disabled";
487 };
488
489 pwm7: pwm@ff170030 {
490 compatible = "rockchip,rk3308-
491 reg = <0x0 0xff170030 0x0 0x10
492 clocks = <&cru SCLK_PWM1>, <&c
493 clock-names = "pwm", "pclk";
494 pinctrl-names = "default";
495 pinctrl-0 = <&pwm7_pin>;
496 #pwm-cells = <3>;
497 status = "disabled";
498 };
499
500 pwm0: pwm@ff180000 {
501 compatible = "rockchip,rk3308-
502 reg = <0x0 0xff180000 0x0 0x10
503 clocks = <&cru SCLK_PWM0>, <&c
504 clock-names = "pwm", "pclk";
505 pinctrl-names = "default";
506 pinctrl-0 = <&pwm0_pin>;
507 #pwm-cells = <3>;
508 status = "disabled";
509 };
510
511 pwm1: pwm@ff180010 {
512 compatible = "rockchip,rk3308-
513 reg = <0x0 0xff180010 0x0 0x10
514 clocks = <&cru SCLK_PWM0>, <&c
515 clock-names = "pwm", "pclk";
516 pinctrl-names = "default";
517 pinctrl-0 = <&pwm1_pin>;
518 #pwm-cells = <3>;
519 status = "disabled";
520 };
521
522 pwm2: pwm@ff180020 {
523 compatible = "rockchip,rk3308-
524 reg = <0x0 0xff180020 0x0 0x10
525 clocks = <&cru SCLK_PWM0>, <&c
526 clock-names = "pwm", "pclk";
527 pinctrl-names = "default";
528 pinctrl-0 = <&pwm2_pin>;
529 #pwm-cells = <3>;
530 status = "disabled";
531 };
532
533 pwm3: pwm@ff180030 {
534 compatible = "rockchip,rk3308-
535 reg = <0x0 0xff180030 0x0 0x10
536 clocks = <&cru SCLK_PWM0>, <&c
537 clock-names = "pwm", "pclk";
538 pinctrl-names = "default";
539 pinctrl-0 = <&pwm3_pin>;
540 #pwm-cells = <3>;
541 status = "disabled";
542 };
543
544 rktimer: rktimer@ff1a0000 {
545 compatible = "rockchip,rk3288-
546 reg = <0x0 0xff1a0000 0x0 0x20
547 interrupts = <GIC_SPI 25 IRQ_T
548 clocks = <&cru PCLK_TIMER>, <&
549 clock-names = "pclk", "timer";
550 };
551
552 saradc: saradc@ff1e0000 {
553 compatible = "rockchip,rk3308-
554 reg = <0x0 0xff1e0000 0x0 0x10
555 interrupts = <GIC_SPI 37 IRQ_T
556 clocks = <&cru SCLK_SARADC>, <
557 clock-names = "saradc", "apb_p
558 #io-channel-cells = <1>;
559 resets = <&cru SRST_SARADC_P>;
560 reset-names = "saradc-apb";
561 status = "disabled";
562 };
563
564 otp: efuse@ff210000 {
565 compatible = "rockchip,rk3308-
566 reg = <0x0 0xff210000 0x0 0x40
567 #address-cells = <1>;
568 #size-cells = <1>;
569 clocks = <&cru SCLK_OTP_USR>,
570 <&cru PCLK_OTP_PHY>;
571 clock-names = "otp", "apb_pclk
572 resets = <&cru SRST_OTP_PHY>;
573 reset-names = "phy";
574
575 cpu_id: id@7 {
576 reg = <0x07 0x10>;
577 };
578
579 cpu_leakage: cpu-leakage@17 {
580 reg = <0x17 0x1>;
581 };
582
583 logic_leakage: logic-leakage@1
584 reg = <0x18 0x1>;
585 };
586 };
587
588 dmac0: dma-controller@ff2c0000 {
589 compatible = "arm,pl330", "arm
590 reg = <0x0 0xff2c0000 0x0 0x40
591 interrupts = <GIC_SPI 0 IRQ_TY
592 <GIC_SPI 1 IRQ_TY
593 arm,pl330-periph-burst;
594 clocks = <&cru ACLK_DMAC0>;
595 clock-names = "apb_pclk";
596 #dma-cells = <1>;
597 };
598
599 dmac1: dma-controller@ff2d0000 {
600 compatible = "arm,pl330", "arm
601 reg = <0x0 0xff2d0000 0x0 0x40
602 interrupts = <GIC_SPI 2 IRQ_TY
603 <GIC_SPI 3 IRQ_TY
604 arm,pl330-periph-burst;
605 clocks = <&cru ACLK_DMAC1>;
606 clock-names = "apb_pclk";
607 #dma-cells = <1>;
608 };
609
610 /*
611 * - can be clock producer or consumer
612 * - up to 8 capture channels and 2 pl
613 * - connected internally to audio cod
614 */
615 i2s_8ch_2: i2s@ff320000 {
616 compatible = "rockchip,rk3308-
617 reg = <0x0 0xff320000 0x0 0x10
618 interrupts = <GIC_SPI 50 IRQ_T
619 clock-names = "mclk_tx", "mclk
620 clocks = <&cru SCLK_I2S2_8CH_T
621 <&cru SCLK_I2S2_8CH_R
622 <&cru HCLK_I2S2_8CH>;
623 dmas = <&dmac1 5>, <&dmac1 4>;
624 dma-names = "rx", "tx";
625 resets = <&cru SRST_I2S2_8CH_T
626 reset-names = "tx-m", "rx-m";
627 rockchip,grf = <&grf>;
628 status = "disabled";
629 };
630
631 /*
632 * - can be clock consumer only
633 * - up to 4 capture channels, no play
634 * - connected internally to audio cod
635 */
636 i2s_8ch_3: i2s@ff330000 {
637 compatible = "rockchip,rk3308-
638 reg = <0x0 0xff330000 0x0 0x10
639 interrupts = <GIC_SPI 51 IRQ_T
640 clock-names = "mclk_tx", "mclk
641 clocks = <&cru SCLK_I2S3_8CH_T
642 <&cru SCLK_I2S3_8CH_R
643 <&cru HCLK_I2S3_8CH>;
644 dmas = <&dmac1 7>;
645 dma-names = "rx";
646 resets = <&cru SRST_I2S3_8CH_T
647 reset-names = "tx-m", "rx-m";
648 rockchip,grf = <&grf>;
649 status = "disabled";
650 };
651
652 i2s_2ch_0: i2s@ff350000 {
653 compatible = "rockchip,rk3308-
654 reg = <0x0 0xff350000 0x0 0x10
655 interrupts = <GIC_SPI 52 IRQ_T
656 clocks = <&cru SCLK_I2S0_2CH>,
657 clock-names = "i2s_clk", "i2s_
658 dmas = <&dmac1 8>, <&dmac1 9>;
659 dma-names = "tx", "rx";
660 resets = <&cru SRST_I2S0_2CH_M
661 reset-names = "reset-m", "rese
662 pinctrl-names = "default";
663 pinctrl-0 = <&i2s_2ch_0_sclk
664 &i2s_2ch_0_lrck
665 &i2s_2ch_0_sdi
666 &i2s_2ch_0_sdo>;
667 status = "disabled";
668 };
669
670 i2s_2ch_1: i2s@ff360000 {
671 compatible = "rockchip,rk3308-
672 reg = <0x0 0xff360000 0x0 0x10
673 interrupts = <GIC_SPI 53 IRQ_T
674 clocks = <&cru SCLK_I2S1_2CH>,
675 clock-names = "i2s_clk", "i2s_
676 dmas = <&dmac1 11>;
677 dma-names = "rx";
678 resets = <&cru SRST_I2S1_2CH_M
679 reset-names = "reset-m", "rese
680 status = "disabled";
681 };
682
683 spdif_tx: spdif-tx@ff3a0000 {
684 compatible = "rockchip,rk3308-
685 reg = <0x0 0xff3a0000 0x0 0x10
686 interrupts = <GIC_SPI 55 IRQ_T
687 clocks = <&cru SCLK_SPDIF_TX>,
688 clock-names = "mclk", "hclk";
689 dmas = <&dmac1 13>;
690 dma-names = "tx";
691 pinctrl-names = "default";
692 pinctrl-0 = <&spdif_out>;
693 status = "disabled";
694 };
695
696 usb20_otg: usb@ff400000 {
697 compatible = "rockchip,rk3308-
698 "snps,dwc2";
699 reg = <0x0 0xff400000 0x0 0x40
700 interrupts = <GIC_SPI 66 IRQ_T
701 clocks = <&cru HCLK_OTG>;
702 clock-names = "otg";
703 dr_mode = "otg";
704 g-np-tx-fifo-size = <16>;
705 g-rx-fifo-size = <280>;
706 g-tx-fifo-size = <256 128 128
707 phys = <&u2phy_otg>;
708 phy-names = "usb2-phy";
709 status = "disabled";
710 };
711
712 usb_host_ehci: usb@ff440000 {
713 compatible = "generic-ehci";
714 reg = <0x0 0xff440000 0x0 0x10
715 interrupts = <GIC_SPI 71 IRQ_T
716 clocks = <&cru HCLK_HOST>, <&c
717 phys = <&u2phy_host>;
718 phy-names = "usb";
719 status = "disabled";
720 };
721
722 usb_host_ohci: usb@ff450000 {
723 compatible = "generic-ohci";
724 reg = <0x0 0xff450000 0x0 0x10
725 interrupts = <GIC_SPI 72 IRQ_T
726 clocks = <&cru HCLK_HOST>, <&c
727 phys = <&u2phy_host>;
728 phy-names = "usb";
729 status = "disabled";
730 };
731
732 sdmmc: mmc@ff480000 {
733 compatible = "rockchip,rk3308-
734 reg = <0x0 0xff480000 0x0 0x40
735 interrupts = <GIC_SPI 76 IRQ_T
736 bus-width = <4>;
737 clocks = <&cru HCLK_SDMMC>, <&
738 <&cru SCLK_SDMMC_DRV>
739 clock-names = "biu", "ciu", "c
740 fifo-depth = <0x100>;
741 max-frequency = <150000000>;
742 pinctrl-names = "default";
743 pinctrl-0 = <&sdmmc_clk &sdmmc
744 status = "disabled";
745 };
746
747 emmc: mmc@ff490000 {
748 compatible = "rockchip,rk3308-
749 reg = <0x0 0xff490000 0x0 0x40
750 interrupts = <GIC_SPI 77 IRQ_T
751 bus-width = <8>;
752 clocks = <&cru HCLK_EMMC>, <&c
753 <&cru SCLK_EMMC_DRV>,
754 clock-names = "biu", "ciu", "c
755 fifo-depth = <0x100>;
756 max-frequency = <150000000>;
757 status = "disabled";
758 };
759
760 sdio: mmc@ff4a0000 {
761 compatible = "rockchip,rk3308-
762 reg = <0x0 0xff4a0000 0x0 0x40
763 interrupts = <GIC_SPI 78 IRQ_T
764 bus-width = <4>;
765 clocks = <&cru HCLK_SDIO>, <&c
766 <&cru SCLK_SDIO_DRV>,
767 clock-names = "biu", "ciu", "c
768 fifo-depth = <0x100>;
769 max-frequency = <150000000>;
770 pinctrl-names = "default";
771 pinctrl-0 = <&sdio_bus4 &sdio_
772 status = "disabled";
773 };
774
775 nfc: nand-controller@ff4b0000 {
776 compatible = "rockchip,rk3308-
777 "rockchip,rv1108-
778 reg = <0x0 0xff4b0000 0x0 0x40
779 interrupts = <GIC_SPI 81 IRQ_T
780 clocks = <&cru HCLK_NANDC>, <&
781 clock-names = "ahb", "nfc";
782 assigned-clocks = <&cru SCLK_N
783 assigned-clock-rates = <150000
784 pinctrl-0 = <&flash_ale &flash
785 &flash_rdn &flash
786 pinctrl-names = "default";
787 status = "disabled";
788 };
789
790 gmac: ethernet@ff4e0000 {
791 compatible = "rockchip,rk3308-
792 reg = <0x0 0xff4e0000 0x0 0x10
793 interrupts = <GIC_SPI 64 IRQ_T
794 interrupt-names = "macirq";
795 clocks = <&cru SCLK_MAC>, <&cr
796 <&cru SCLK_MAC_RX_TX>
797 <&cru SCLK_MAC>, <&cr
798 <&cru PCLK_MAC>, <&cr
799 clock-names = "stmmaceth", "ma
800 "mac_clk_tx", "c
801 "clk_mac_refout"
802 "pclk_mac", "clk
803 phy-mode = "rmii";
804 pinctrl-names = "default";
805 pinctrl-0 = <&rmii_pins &mac_r
806 resets = <&cru SRST_MAC_A>;
807 reset-names = "stmmaceth";
808 rockchip,grf = <&grf>;
809 status = "disabled";
810 };
811
812 sfc: spi@ff4c0000 {
813 compatible = "rockchip,sfc";
814 reg = <0x0 0xff4c0000 0x0 0x40
815 interrupts = <GIC_SPI 82 IRQ_T
816 clocks = <&cru SCLK_SFC>, <&cr
817 clock-names = "clk_sfc", "hclk
818 pinctrl-0 = <&sfc_clk &sfc_cs0
819 pinctrl-names = "default";
820 status = "disabled";
821 };
822
823 cru: clock-controller@ff500000 {
824 compatible = "rockchip,rk3308-
825 reg = <0x0 0xff500000 0x0 0x10
826 clocks = <&xin24m>;
827 clock-names = "xin24m";
828 rockchip,grf = <&grf>;
829 #clock-cells = <1>;
830 #reset-cells = <1>;
831 assigned-clocks = <&cru SCLK_R
832 assigned-clock-rates = <32768>
833 };
834
835 codec: codec@ff560000 {
836 compatible = "rockchip,rk3308-
837 reg = <0x0 0xff560000 0x0 0x10
838 rockchip,grf = <&grf>;
839 clock-names = "mclk_tx", "mclk
840 clocks = <&cru SCLK_I2S2_8CH_T
841 <&cru SCLK_I2S2_8CH_R
842 <&cru PCLK_ACODEC>;
843 reset-names = "codec";
844 resets = <&cru SRST_ACODEC_P>;
845 #sound-dai-cells = <0>;
846 status = "disabled";
847 };
848
849 gic: interrupt-controller@ff580000 {
850 compatible = "arm,gic-400";
851 reg = <0x0 0xff581000 0x0 0x10
852 <0x0 0xff582000 0x0 0x20
853 <0x0 0xff584000 0x0 0x20
854 <0x0 0xff586000 0x0 0x20
855 interrupts = <GIC_PPI 9 IRQ_TY
856 #interrupt-cells = <3>;
857 interrupt-controller;
858 #address-cells = <0>;
859 };
860
861 sram: sram@fff80000 {
862 compatible = "mmio-sram";
863 reg = <0x0 0xfff80000 0x0 0x40
864 ranges = <0 0x0 0xfff80000 0x4
865 #address-cells = <1>;
866 #size-cells = <1>;
867
868 /* reserved for ddr dvfs and s
869 ddr-sram@0 {
870 reg = <0x0 0x8000>;
871 };
872
873 /* reserved for vad audio buff
874 vad_sram: vad-sram@8000 {
875 reg = <0x8000 0x38000>
876 };
877 };
878
879 pinctrl: pinctrl {
880 compatible = "rockchip,rk3308-
881 rockchip,grf = <&grf>;
882 #address-cells = <2>;
883 #size-cells = <2>;
884 ranges;
885
886 gpio0: gpio@ff220000 {
887 compatible = "rockchip
888 reg = <0x0 0xff220000
889 interrupts = <GIC_SPI
890 clocks = <&cru PCLK_GP
891 gpio-controller;
892 #gpio-cells = <2>;
893 interrupt-controller;
894 #interrupt-cells = <2>
895 };
896
897 gpio1: gpio@ff230000 {
898 compatible = "rockchip
899 reg = <0x0 0xff230000
900 interrupts = <GIC_SPI
901 clocks = <&cru PCLK_GP
902 gpio-controller;
903 #gpio-cells = <2>;
904 interrupt-controller;
905 #interrupt-cells = <2>
906 };
907
908 gpio2: gpio@ff240000 {
909 compatible = "rockchip
910 reg = <0x0 0xff240000
911 interrupts = <GIC_SPI
912 clocks = <&cru PCLK_GP
913 gpio-controller;
914 #gpio-cells = <2>;
915 interrupt-controller;
916 #interrupt-cells = <2>
917 };
918
919 gpio3: gpio@ff250000 {
920 compatible = "rockchip
921 reg = <0x0 0xff250000
922 interrupts = <GIC_SPI
923 clocks = <&cru PCLK_GP
924 gpio-controller;
925 #gpio-cells = <2>;
926 interrupt-controller;
927 #interrupt-cells = <2>
928 };
929
930 gpio4: gpio@ff260000 {
931 compatible = "rockchip
932 reg = <0x0 0xff260000
933 interrupts = <GIC_SPI
934 clocks = <&cru PCLK_GP
935 gpio-controller;
936 #gpio-cells = <2>;
937 interrupt-controller;
938 #interrupt-cells = <2>
939 };
940
941 pcfg_pull_up: pcfg-pull-up {
942 bias-pull-up;
943 };
944
945 pcfg_pull_down: pcfg-pull-down
946 bias-pull-down;
947 };
948
949 pcfg_pull_none: pcfg-pull-none
950 bias-disable;
951 };
952
953 pcfg_pull_none_2ma: pcfg-pull-
954 bias-disable;
955 drive-strength = <2>;
956 };
957
958 pcfg_pull_up_2ma: pcfg-pull-up
959 bias-pull-up;
960 drive-strength = <2>;
961 };
962
963 pcfg_pull_up_4ma: pcfg-pull-up
964 bias-pull-up;
965 drive-strength = <4>;
966 };
967
968 pcfg_pull_none_4ma: pcfg-pull-
969 bias-disable;
970 drive-strength = <4>;
971 };
972
973 pcfg_pull_down_4ma: pcfg-pull-
974 bias-pull-down;
975 drive-strength = <4>;
976 };
977
978 pcfg_pull_none_8ma: pcfg-pull-
979 bias-disable;
980 drive-strength = <8>;
981 };
982
983 pcfg_pull_up_8ma: pcfg-pull-up
984 bias-pull-up;
985 drive-strength = <8>;
986 };
987
988 pcfg_pull_none_12ma: pcfg-pull
989 bias-disable;
990 drive-strength = <12>;
991 };
992
993 pcfg_pull_up_12ma: pcfg-pull-u
994 bias-pull-up;
995 drive-strength = <12>;
996 };
997
998 pcfg_pull_none_smt: pcfg-pull-
999 bias-disable;
1000 input-schmitt-enable;
1001 };
1002
1003 pcfg_output_high: pcfg-output
1004 output-high;
1005 };
1006
1007 pcfg_output_low: pcfg-output-
1008 output-low;
1009 };
1010
1011 pcfg_input_high: pcfg-input-h
1012 bias-pull-up;
1013 input-enable;
1014 };
1015
1016 pcfg_input: pcfg-input {
1017 input-enable;
1018 };
1019
1020 emmc {
1021 emmc_clk: emmc-clk {
1022 rockchip,pins
1023 <3 RK
1024 };
1025
1026 emmc_cmd: emmc-cmd {
1027 rockchip,pins
1028 <3 RK
1029 };
1030
1031 emmc_pwren: emmc-pwre
1032 rockchip,pins
1033 <3 RK
1034 };
1035
1036 emmc_rstn: emmc-rstn
1037 rockchip,pins
1038 <3 RK
1039 };
1040
1041 emmc_bus1: emmc-bus1
1042 rockchip,pins
1043 <3 RK
1044 };
1045
1046 emmc_bus4: emmc-bus4
1047 rockchip,pins
1048 <3 RK
1049 <3 RK
1050 <3 RK
1051 <3 RK
1052 };
1053
1054 emmc_bus8: emmc-bus8
1055 rockchip,pins
1056 <3 RK
1057 <3 RK
1058 <3 RK
1059 <3 RK
1060 <3 RK
1061 <3 RK
1062 <3 RK
1063 <3 RK
1064 };
1065 };
1066
1067 flash {
1068 flash_csn0: flash-csn
1069 rockchip,pins
1070 <3 RK
1071 };
1072
1073 flash_rdy: flash-rdy
1074 rockchip,pins
1075 <3 RK
1076 };
1077
1078 flash_ale: flash-ale
1079 rockchip,pins
1080 <3 RK
1081 };
1082
1083 flash_cle: flash-cle
1084 rockchip,pins
1085 <3 RK
1086 };
1087
1088 flash_wrn: flash-wrn
1089 rockchip,pins
1090 <3 RK
1091 };
1092
1093 flash_rdn: flash-rdn
1094 rockchip,pins
1095 <3 RK
1096 };
1097
1098 flash_bus8: flash-bus
1099 rockchip,pins
1100 <3 RK
1101 <3 RK
1102 <3 RK
1103 <3 RK
1104 <3 RK
1105 <3 RK
1106 <3 RK
1107 <3 RK
1108 };
1109 };
1110
1111 sfc {
1112 sfc_bus4: sfc-bus4 {
1113 rockchip,pins
1114 <3 RK
1115 <3 RK
1116 <3 RK
1117 <3 RK
1118 };
1119
1120 sfc_bus2: sfc-bus2 {
1121 rockchip,pins
1122 <3 RK
1123 <3 RK
1124 };
1125
1126 sfc_cs0: sfc-cs0 {
1127 rockchip,pins
1128 <3 RK
1129 };
1130
1131 sfc_clk: sfc-clk {
1132 rockchip,pins
1133 <3 RK
1134 };
1135 };
1136
1137 gmac {
1138 rmii_pins: rmii-pins
1139 rockchip,pins
1140 /* ma
1141 <1 RK
1142 /* ma
1143 <1 RK
1144 /* ma
1145 <1 RK
1146 /* ma
1147 <1 RK
1148 /* ma
1149 <1 RK
1150 /* ma
1151 <1 RK
1152 /* ma
1153 <1 RK
1154 /* ma
1155 <1 RK
1156 /* ma
1157 <1 RK
1158 };
1159
1160 mac_refclk_12ma: mac-
1161 rockchip,pins
1162 <1 RK
1163 };
1164
1165 mac_refclk: mac-refcl
1166 rockchip,pins
1167 <1 RK
1168 };
1169 };
1170
1171 gmac-m1 {
1172 rmiim1_pins: rmiim1-p
1173 rockchip,pins
1174 /* ma
1175 <4 RK
1176 /* ma
1177 <4 RK
1178 /* ma
1179 <4 RK
1180 /* ma
1181 <4 RK
1182 /* ma
1183 <4 RK
1184 /* ma
1185 <4 RK
1186 /* ma
1187 <4 RK
1188 /* ma
1189 <4 RK
1190 /* ma
1191 <4 RK
1192 };
1193
1194 macm1_refclk_12ma: ma
1195 rockchip,pins
1196 <4 RK
1197 };
1198
1199 macm1_refclk: macm1-r
1200 rockchip,pins
1201 <4 RK
1202 };
1203 };
1204
1205 i2c0 {
1206 i2c0_xfer: i2c0-xfer
1207 rockchip,pins
1208 <1 RK
1209 <1 RK
1210 };
1211 };
1212
1213 i2c1 {
1214 i2c1_xfer: i2c1-xfer
1215 rockchip,pins
1216 <0 RK
1217 <0 RK
1218 };
1219 };
1220
1221 i2c2 {
1222 i2c2_xfer: i2c2-xfer
1223 rockchip,pins
1224 <2 RK
1225 <2 RK
1226 };
1227 };
1228
1229 i2c3-m0 {
1230 i2c3m0_xfer: i2c3m0-x
1231 rockchip,pins
1232 <0 RK
1233 <0 RK
1234 };
1235 };
1236
1237 i2c3-m1 {
1238 i2c3m1_xfer: i2c3m1-x
1239 rockchip,pins
1240 <3 RK
1241 <3 RK
1242 };
1243 };
1244
1245 i2c3-m2 {
1246 i2c3m2_xfer: i2c3m2-x
1247 rockchip,pins
1248 <2 RK
1249 <2 RK
1250 };
1251 };
1252
1253 i2s_2ch_0 {
1254 i2s_2ch_0_mclk: i2s-2
1255 rockchip,pins
1256 <4 RK
1257 };
1258
1259 i2s_2ch_0_sclk: i2s-2
1260 rockchip,pins
1261 <4 RK
1262 };
1263
1264 i2s_2ch_0_lrck: i2s-2
1265 rockchip,pins
1266 <4 RK
1267 };
1268
1269 i2s_2ch_0_sdo: i2s-2c
1270 rockchip,pins
1271 <4 RK
1272 };
1273
1274 i2s_2ch_0_sdi: i2s-2c
1275 rockchip,pins
1276 <4 RK
1277 };
1278 };
1279
1280 i2s_8ch_0 {
1281 i2s_8ch_0_mclk: i2s-8
1282 rockchip,pins
1283 <2 RK
1284 };
1285
1286 i2s_8ch_0_sclktx: i2s
1287 rockchip,pins
1288 <2 RK
1289 };
1290
1291 i2s_8ch_0_sclkrx: i2s
1292 rockchip,pins
1293 <2 RK
1294 };
1295
1296 i2s_8ch_0_lrcktx: i2s
1297 rockchip,pins
1298 <2 RK
1299 };
1300
1301 i2s_8ch_0_lrckrx: i2s
1302 rockchip,pins
1303 <2 RK
1304 };
1305
1306 i2s_8ch_0_sdo0: i2s-8
1307 rockchip,pins
1308 <2 RK
1309 };
1310
1311 i2s_8ch_0_sdo1: i2s-8
1312 rockchip,pins
1313 <2 RK
1314 };
1315
1316 i2s_8ch_0_sdo2: i2s-8
1317 rockchip,pins
1318 <2 RK
1319 };
1320
1321 i2s_8ch_0_sdo3: i2s-8
1322 rockchip,pins
1323 <2 RK
1324 };
1325
1326 i2s_8ch_0_sdi0: i2s-8
1327 rockchip,pins
1328 <2 RK
1329 };
1330
1331 i2s_8ch_0_sdi1: i2s-8
1332 rockchip,pins
1333 <2 RK
1334 };
1335
1336 i2s_8ch_0_sdi2: i2s-8
1337 rockchip,pins
1338 <2 RK
1339 };
1340
1341 i2s_8ch_0_sdi3: i2s-8
1342 rockchip,pins
1343 <2 RK
1344 };
1345 };
1346
1347 i2s_8ch_1_m0 {
1348 i2s_8ch_1_m0_mclk: i2
1349 rockchip,pins
1350 <1 RK
1351 };
1352
1353 i2s_8ch_1_m0_sclktx:
1354 rockchip,pins
1355 <1 RK
1356 };
1357
1358 i2s_8ch_1_m0_sclkrx:
1359 rockchip,pins
1360 <1 RK
1361 };
1362
1363 i2s_8ch_1_m0_lrcktx:
1364 rockchip,pins
1365 <1 RK
1366 };
1367
1368 i2s_8ch_1_m0_lrckrx:
1369 rockchip,pins
1370 <1 RK
1371 };
1372
1373 i2s_8ch_1_m0_sdo0: i2
1374 rockchip,pins
1375 <1 RK
1376 };
1377
1378 i2s_8ch_1_m0_sdo1_sdi
1379 rockchip,pins
1380 <1 RK
1381 };
1382
1383 i2s_8ch_1_m0_sdo2_sdi
1384 rockchip,pins
1385 <1 RK
1386 };
1387
1388 i2s_8ch_1_m0_sdo3_sdi
1389 rockchip,pins
1390 <1 RK
1391 };
1392
1393 i2s_8ch_1_m0_sdi0: i2
1394 rockchip,pins
1395 <1 RK
1396 };
1397 };
1398
1399 i2s_8ch_1_m1 {
1400 i2s_8ch_1_m1_mclk: i2
1401 rockchip,pins
1402 <1 RK
1403 };
1404
1405 i2s_8ch_1_m1_sclktx:
1406 rockchip,pins
1407 <1 RK
1408 };
1409
1410 i2s_8ch_1_m1_sclkrx:
1411 rockchip,pins
1412 <1 RK
1413 };
1414
1415 i2s_8ch_1_m1_lrcktx:
1416 rockchip,pins
1417 <1 RK
1418 };
1419
1420 i2s_8ch_1_m1_lrckrx:
1421 rockchip,pins
1422 <1 RK
1423 };
1424
1425 i2s_8ch_1_m1_sdo0: i2
1426 rockchip,pins
1427 <1 RK
1428 };
1429
1430 i2s_8ch_1_m1_sdo1_sdi
1431 rockchip,pins
1432 <1 RK
1433 };
1434
1435 i2s_8ch_1_m1_sdo2_sdi
1436 rockchip,pins
1437 <1 RK
1438 };
1439
1440 i2s_8ch_1_m1_sdo3_sdi
1441 rockchip,pins
1442 <1 RK
1443 };
1444
1445 i2s_8ch_1_m1_sdi0: i2
1446 rockchip,pins
1447 <1 RK
1448 };
1449 };
1450
1451 pdm_m0 {
1452 pdm_m0_clk: pdm-m0-cl
1453 rockchip,pins
1454 <1 RK
1455 };
1456
1457 pdm_m0_sdi0: pdm-m0-s
1458 rockchip,pins
1459 <1 RK
1460 };
1461
1462 pdm_m0_sdi1: pdm-m0-s
1463 rockchip,pins
1464 <1 RK
1465 };
1466
1467 pdm_m0_sdi2: pdm-m0-s
1468 rockchip,pins
1469 <1 RK
1470 };
1471
1472 pdm_m0_sdi3: pdm-m0-s
1473 rockchip,pins
1474 <1 RK
1475 };
1476 };
1477
1478 pdm_m1 {
1479 pdm_m1_clk: pdm-m1-cl
1480 rockchip,pins
1481 <1 RK
1482 };
1483
1484 pdm_m1_sdi0: pdm-m1-s
1485 rockchip,pins
1486 <1 RK
1487 };
1488
1489 pdm_m1_sdi1: pdm-m1-s
1490 rockchip,pins
1491 <1 RK
1492 };
1493
1494 pdm_m1_sdi2: pdm-m1-s
1495 rockchip,pins
1496 <1 RK
1497 };
1498
1499 pdm_m1_sdi3: pdm-m1-s
1500 rockchip,pins
1501 <1 RK
1502 };
1503 };
1504
1505 pdm_m2 {
1506 pdm_m2_clkm: pdm-m2-c
1507 rockchip,pins
1508 <2 RK
1509 };
1510
1511 pdm_m2_clk: pdm-m2-cl
1512 rockchip,pins
1513 <2 RK
1514 };
1515
1516 pdm_m2_sdi0: pdm-m2-s
1517 rockchip,pins
1518 <2 RK
1519 };
1520
1521 pdm_m2_sdi1: pdm-m2-s
1522 rockchip,pins
1523 <2 RK
1524 };
1525
1526 pdm_m2_sdi2: pdm-m2-s
1527 rockchip,pins
1528 <2 RK
1529 };
1530
1531 pdm_m2_sdi3: pdm-m2-s
1532 rockchip,pins
1533 <2 RK
1534 };
1535 };
1536
1537 pwm0 {
1538 pwm0_pin: pwm0-pin {
1539 rockchip,pins
1540 <0 RK
1541 };
1542
1543 pwm0_pin_pull_down: p
1544 rockchip,pins
1545 <0 RK
1546 };
1547 };
1548
1549 pwm1 {
1550 pwm1_pin: pwm1-pin {
1551 rockchip,pins
1552 <0 RK
1553 };
1554
1555 pwm1_pin_pull_down: p
1556 rockchip,pins
1557 <0 RK
1558 };
1559 };
1560
1561 pwm2 {
1562 pwm2_pin: pwm2-pin {
1563 rockchip,pins
1564 <0 RK
1565 };
1566
1567 pwm2_pin_pull_down: p
1568 rockchip,pins
1569 <0 RK
1570 };
1571 };
1572
1573 pwm3 {
1574 pwm3_pin: pwm3-pin {
1575 rockchip,pins
1576 <0 RK
1577 };
1578
1579 pwm3_pin_pull_down: p
1580 rockchip,pins
1581 <0 RK
1582 };
1583 };
1584
1585 pwm4 {
1586 pwm4_pin: pwm4-pin {
1587 rockchip,pins
1588 <0 RK
1589 };
1590
1591 pwm4_pin_pull_down: p
1592 rockchip,pins
1593 <0 RK
1594 };
1595 };
1596
1597 pwm5 {
1598 pwm5_pin: pwm5-pin {
1599 rockchip,pins
1600 <0 RK
1601 };
1602
1603 pwm5_pin_pull_down: p
1604 rockchip,pins
1605 <0 RK
1606 };
1607 };
1608
1609 pwm6 {
1610 pwm6_pin: pwm6-pin {
1611 rockchip,pins
1612 <0 RK
1613 };
1614
1615 pwm6_pin_pull_down: p
1616 rockchip,pins
1617 <0 RK
1618 };
1619 };
1620
1621 pwm7 {
1622 pwm7_pin: pwm7-pin {
1623 rockchip,pins
1624 <2 RK
1625 };
1626
1627 pwm7_pin_pull_down: p
1628 rockchip,pins
1629 <2 RK
1630 };
1631 };
1632
1633 pwm8 {
1634 pwm8_pin: pwm8-pin {
1635 rockchip,pins
1636 <2 RK
1637 };
1638
1639 pwm8_pin_pull_down: p
1640 rockchip,pins
1641 <2 RK
1642 };
1643 };
1644
1645 pwm9 {
1646 pwm9_pin: pwm9-pin {
1647 rockchip,pins
1648 <2 RK
1649 };
1650
1651 pwm9_pin_pull_down: p
1652 rockchip,pins
1653 <2 RK
1654 };
1655 };
1656
1657 pwm10 {
1658 pwm10_pin: pwm10-pin
1659 rockchip,pins
1660 <2 RK
1661 };
1662
1663 pwm10_pin_pull_down:
1664 rockchip,pins
1665 <2 RK
1666 };
1667 };
1668
1669 pwm11 {
1670 pwm11_pin: pwm11-pin
1671 rockchip,pins
1672 <2 RK
1673 };
1674
1675 pwm11_pin_pull_down:
1676 rockchip,pins
1677 <2 RK
1678 };
1679 };
1680
1681 rtc {
1682 rtc_32k: rtc-32k {
1683 rockchip,pins
1684 <0 RK
1685 };
1686 };
1687
1688 sdmmc {
1689 sdmmc_clk: sdmmc-clk
1690 rockchip,pins
1691 <4 RK
1692 };
1693
1694 sdmmc_cmd: sdmmc-cmd
1695 rockchip,pins
1696 <4 RK
1697 };
1698
1699 sdmmc_det: sdmmc-det
1700 rockchip,pins
1701 <0 RK
1702 };
1703
1704 sdmmc_pwren: sdmmc-pw
1705 rockchip,pins
1706 <4 RK
1707 };
1708
1709 sdmmc_bus1: sdmmc-bus
1710 rockchip,pins
1711 <4 RK
1712 };
1713
1714 sdmmc_bus4: sdmmc-bus
1715 rockchip,pins
1716 <4 RK
1717 <4 RK
1718 <4 RK
1719 <4 RK
1720 };
1721 };
1722
1723 sdio {
1724 sdio_clk: sdio-clk {
1725 rockchip,pins
1726 <4 RK
1727 };
1728
1729 sdio_cmd: sdio-cmd {
1730 rockchip,pins
1731 <4 RK
1732 };
1733
1734 sdio_pwren: sdio-pwre
1735 rockchip,pins
1736 <0 RK
1737 };
1738
1739 sdio_wrpt: sdio-wrpt
1740 rockchip,pins
1741 <0 RK
1742 };
1743
1744 sdio_intn: sdio-intn
1745 rockchip,pins
1746 <0 RK
1747 };
1748
1749 sdio_bus1: sdio-bus1
1750 rockchip,pins
1751 <4 RK
1752 };
1753
1754 sdio_bus4: sdio-bus4
1755 rockchip,pins
1756 <4 RK
1757 <4 RK
1758 <4 RK
1759 <4 RK
1760 };
1761 };
1762
1763 spdif_in {
1764 spdif_in: spdif-in {
1765 rockchip,pins
1766 <0 RK
1767 };
1768 };
1769
1770 spdif_out {
1771 spdif_out: spdif-out
1772 rockchip,pins
1773 <0 RK
1774 };
1775 };
1776
1777 spi0 {
1778 spi0_clk: spi0-clk {
1779 rockchip,pins
1780 <2 RK
1781 };
1782
1783 spi0_csn0: spi0-csn0
1784 rockchip,pins
1785 <2 RK
1786 };
1787
1788 spi0_miso: spi0-miso
1789 rockchip,pins
1790 <2 RK
1791 };
1792
1793 spi0_mosi: spi0-mosi
1794 rockchip,pins
1795 <2 RK
1796 };
1797 };
1798
1799 spi1 {
1800 spi1_clk: spi1-clk {
1801 rockchip,pins
1802 <3 RK
1803 };
1804
1805 spi1_csn0: spi1-csn0
1806 rockchip,pins
1807 <3 RK
1808 };
1809
1810 spi1_miso: spi1-miso
1811 rockchip,pins
1812 <3 RK
1813 };
1814
1815 spi1_mosi: spi1-mosi
1816 rockchip,pins
1817 <3 RK
1818 };
1819 };
1820
1821 spi1-m1 {
1822 spi1m1_miso: spi1m1-m
1823 rockchip,pins
1824 <2 RK
1825 };
1826
1827 spi1m1_mosi: spi1m1-m
1828 rockchip,pins
1829 <2 RK
1830 };
1831
1832 spi1m1_clk: spi1m1-cl
1833 rockchip,pins
1834 <2 RK
1835 };
1836
1837 spi1m1_csn0: spi1m1-c
1838 rockchip,pins
1839 <2 RK
1840 };
1841 };
1842
1843 spi2 {
1844 spi2_clk: spi2-clk {
1845 rockchip,pins
1846 <1 RK
1847 };
1848
1849 spi2_csn0: spi2-csn0
1850 rockchip,pins
1851 <1 RK
1852 };
1853
1854 spi2_miso: spi2-miso
1855 rockchip,pins
1856 <1 RK
1857 };
1858
1859 spi2_mosi: spi2-mosi
1860 rockchip,pins
1861 <1 RK
1862 };
1863 };
1864
1865 tsadc {
1866 tsadc_otp_pin: tsadc-
1867 rockchip,pins
1868 <0 RK
1869 };
1870
1871 tsadc_otp_out: tsadc-
1872 rockchip,pins
1873 <0 RK
1874 };
1875 };
1876
1877 uart0 {
1878 uart0_xfer: uart0-xfe
1879 rockchip,pins
1880 <2 RK
1881 <2 RK
1882 };
1883
1884 uart0_cts: uart0-cts
1885 rockchip,pins
1886 <2 RK
1887 };
1888
1889 uart0_rts: uart0-rts
1890 rockchip,pins
1891 <2 RK
1892 };
1893
1894 uart0_rts_pin: uart0-
1895 rockchip,pins
1896 <2 RK
1897 };
1898 };
1899
1900 uart1 {
1901 uart1_xfer: uart1-xfe
1902 rockchip,pins
1903 <1 RK
1904 <1 RK
1905 };
1906
1907 uart1_cts: uart1-cts
1908 rockchip,pins
1909 <1 RK
1910 };
1911
1912 uart1_rts: uart1-rts
1913 rockchip,pins
1914 <1 RK
1915 };
1916 };
1917
1918 uart2-m0 {
1919 uart2m0_xfer: uart2m0
1920 rockchip,pins
1921 <1 RK
1922 <1 RK
1923 };
1924 };
1925
1926 uart2-m1 {
1927 uart2m1_xfer: uart2m1
1928 rockchip,pins
1929 <4 RK
1930 <4 RK
1931 };
1932 };
1933
1934 uart3 {
1935 uart3_xfer: uart3-xfe
1936 rockchip,pins
1937 <3 RK
1938 <3 RK
1939 };
1940 };
1941
1942 uart3-m1 {
1943 uart3m1_xfer: uart3m1
1944 rockchip,pins
1945 <0 RK
1946 <0 RK
1947 };
1948 };
1949
1950 uart4 {
1951 uart4_xfer: uart4-xfe
1952 rockchip,pins
1953 <4 RK
1954 <4 RK
1955 };
1956
1957 uart4_cts: uart4-cts
1958 rockchip,pins
1959 <4 RK
1960 };
1961
1962 uart4_rts: uart4-rts
1963 rockchip,pins
1964 <4 RK
1965 };
1966
1967 uart4_rts_pin: uart4-
1968 rockchip,pins
1969 <4 RK
1970 };
1971 };
1972 };
1973 };
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