1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright (c) 2016 Fuzhou Rockchip Electron
4 */
5
6 #include <dt-bindings/clock/rk3399-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm
9 #include <dt-bindings/interrupt-controller/irq
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3399-power.h>
12 #include <dt-bindings/thermal/thermal.h>
13
14 / {
15 compatible = "rockchip,rk3399";
16
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
20
21 aliases {
22 gpio0 = &gpio0;
23 gpio1 = &gpio1;
24 gpio2 = &gpio2;
25 gpio3 = &gpio3;
26 gpio4 = &gpio4;
27 i2c0 = &i2c0;
28 i2c1 = &i2c1;
29 i2c2 = &i2c2;
30 i2c3 = &i2c3;
31 i2c4 = &i2c4;
32 i2c5 = &i2c5;
33 i2c6 = &i2c6;
34 i2c7 = &i2c7;
35 i2c8 = &i2c8;
36 serial0 = &uart0;
37 serial1 = &uart1;
38 serial2 = &uart2;
39 serial3 = &uart3;
40 serial4 = &uart4;
41 spi0 = &spi0;
42 spi1 = &spi1;
43 spi2 = &spi2;
44 spi3 = &spi3;
45 spi4 = &spi4;
46 spi5 = &spi5;
47 };
48
49 cpus {
50 #address-cells = <2>;
51 #size-cells = <0>;
52
53 cpu-map {
54 cluster0 { /* Cor
55 core0 {
56 cpu =
57 };
58 core1 {
59 cpu =
60 };
61 core2 {
62 cpu =
63 };
64 core3 {
65 cpu =
66 };
67 };
68
69 cluster1 { /* Cor
70 core0 {
71 cpu =
72 };
73 core1 {
74 cpu =
75 };
76 };
77 };
78
79 cpu_l0: cpu@0 {
80 device_type = "cpu";
81 compatible = "arm,cort
82 reg = <0x0 0x0>;
83 enable-method = "psci"
84 capacity-dmips-mhz = <
85 clocks = <&cru ARMCLKL
86 #cooling-cells = <2>;
87 dynamic-power-coeffici
88 cpu-idle-states = <&CP
89 i-cache-size = <0x8000
90 i-cache-line-size = <6
91 i-cache-sets = <256>;
92 d-cache-size = <0x8000
93 d-cache-line-size = <6
94 d-cache-sets = <128>;
95 next-level-cache = <&l
96 };
97
98 cpu_l1: cpu@1 {
99 device_type = "cpu";
100 compatible = "arm,cort
101 reg = <0x0 0x1>;
102 enable-method = "psci"
103 capacity-dmips-mhz = <
104 clocks = <&cru ARMCLKL
105 #cooling-cells = <2>;
106 dynamic-power-coeffici
107 cpu-idle-states = <&CP
108 i-cache-size = <0x8000
109 i-cache-line-size = <6
110 i-cache-sets = <256>;
111 d-cache-size = <0x8000
112 d-cache-line-size = <6
113 d-cache-sets = <128>;
114 next-level-cache = <&l
115 };
116
117 cpu_l2: cpu@2 {
118 device_type = "cpu";
119 compatible = "arm,cort
120 reg = <0x0 0x2>;
121 enable-method = "psci"
122 capacity-dmips-mhz = <
123 clocks = <&cru ARMCLKL
124 #cooling-cells = <2>;
125 dynamic-power-coeffici
126 cpu-idle-states = <&CP
127 i-cache-size = <0x8000
128 i-cache-line-size = <6
129 i-cache-sets = <256>;
130 d-cache-size = <0x8000
131 d-cache-line-size = <6
132 d-cache-sets = <128>;
133 next-level-cache = <&l
134 };
135
136 cpu_l3: cpu@3 {
137 device_type = "cpu";
138 compatible = "arm,cort
139 reg = <0x0 0x3>;
140 enable-method = "psci"
141 capacity-dmips-mhz = <
142 clocks = <&cru ARMCLKL
143 #cooling-cells = <2>;
144 dynamic-power-coeffici
145 cpu-idle-states = <&CP
146 i-cache-size = <0x8000
147 i-cache-line-size = <6
148 i-cache-sets = <256>;
149 d-cache-size = <0x8000
150 d-cache-line-size = <6
151 d-cache-sets = <128>;
152 next-level-cache = <&l
153 };
154
155 cpu_b0: cpu@100 {
156 device_type = "cpu";
157 compatible = "arm,cort
158 reg = <0x0 0x100>;
159 enable-method = "psci"
160 capacity-dmips-mhz = <
161 clocks = <&cru ARMCLKB
162 #cooling-cells = <2>;
163 dynamic-power-coeffici
164 cpu-idle-states = <&CP
165 i-cache-size = <0xC000
166 i-cache-line-size = <6
167 i-cache-sets = <256>;
168 d-cache-size = <0x8000
169 d-cache-line-size = <6
170 d-cache-sets = <256>;
171 next-level-cache = <&l
172
173 thermal-idle {
174 #cooling-cells
175 duration-us =
176 exit-latency-u
177 };
178 };
179
180 cpu_b1: cpu@101 {
181 device_type = "cpu";
182 compatible = "arm,cort
183 reg = <0x0 0x101>;
184 enable-method = "psci"
185 capacity-dmips-mhz = <
186 clocks = <&cru ARMCLKB
187 #cooling-cells = <2>;
188 dynamic-power-coeffici
189 cpu-idle-states = <&CP
190 i-cache-size = <0xC000
191 i-cache-line-size = <6
192 i-cache-sets = <256>;
193 d-cache-size = <0x8000
194 d-cache-line-size = <6
195 d-cache-sets = <256>;
196 next-level-cache = <&l
197
198 thermal-idle {
199 #cooling-cells
200 duration-us =
201 exit-latency-u
202 };
203 };
204
205 l2_cache_l: l2-cache-cluster0
206 compatible = "cache";
207 cache-level = <2>;
208 cache-unified;
209 cache-size = <0x80000>
210 cache-line-size = <64>
211 cache-sets = <512>;
212 };
213
214 l2_cache_b: l2-cache-cluster1
215 compatible = "cache";
216 cache-level = <2>;
217 cache-unified;
218 cache-size = <0x100000
219 cache-line-size = <64>
220 cache-sets = <1024>;
221 };
222
223 idle-states {
224 entry-method = "psci";
225
226 CPU_SLEEP: cpu-sleep {
227 compatible = "
228 local-timer-st
229 arm,psci-suspe
230 entry-latency-
231 exit-latency-u
232 min-residency-
233 };
234
235 CLUSTER_SLEEP: cluster
236 compatible = "
237 local-timer-st
238 arm,psci-suspe
239 entry-latency-
240 exit-latency-u
241 min-residency-
242 };
243 };
244 };
245
246 display-subsystem {
247 compatible = "rockchip,display
248 ports = <&vopl_out>, <&vopb_ou
249 };
250
251 dmc: memory-controller {
252 compatible = "rockchip,rk3399-
253 rockchip,pmu = <&pmugrf>;
254 devfreq-events = <&dfi>;
255 clocks = <&cru SCLK_DDRC>;
256 clock-names = "dmc_clk";
257 status = "disabled";
258 };
259
260 pmu_a53 {
261 compatible = "arm,cortex-a53-p
262 interrupts = <GIC_PPI 7 IRQ_TY
263 };
264
265 pmu_a72 {
266 compatible = "arm,cortex-a72-p
267 interrupts = <GIC_PPI 7 IRQ_TY
268 };
269
270 psci {
271 compatible = "arm,psci-1.0";
272 method = "smc";
273 };
274
275 timer {
276 compatible = "arm,armv8-timer"
277 interrupts = <GIC_PPI 13 IRQ_T
278 <GIC_PPI 14 IRQ_T
279 <GIC_PPI 11 IRQ_T
280 <GIC_PPI 10 IRQ_T
281 arm,no-tick-in-suspend;
282 };
283
284 xin24m: xin24m {
285 compatible = "fixed-clock";
286 clock-frequency = <24000000>;
287 clock-output-names = "xin24m";
288 #clock-cells = <0>;
289 };
290
291 pcie0: pcie@f8000000 {
292 compatible = "rockchip,rk3399-
293 reg = <0x0 0xf8000000 0x0 0x20
294 <0x0 0xfd000000 0x0 0x10
295 reg-names = "axi-base", "apb-b
296 device_type = "pci";
297 #address-cells = <3>;
298 #size-cells = <2>;
299 #interrupt-cells = <1>;
300 aspm-no-l0s;
301 bus-range = <0x0 0x1f>;
302 clocks = <&cru ACLK_PCIE>, <&c
303 <&cru PCLK_PCIE>, <&c
304 clock-names = "aclk", "aclk-pe
305 "hclk", "pm";
306 interrupts = <GIC_SPI 49 IRQ_T
307 <GIC_SPI 50 IRQ_T
308 <GIC_SPI 51 IRQ_T
309 interrupt-names = "sys", "lega
310 interrupt-map-mask = <0 0 0 7>
311 interrupt-map = <0 0 0 1 &pcie
312 <0 0 0 2 &pcie
313 <0 0 0 3 &pcie
314 <0 0 0 4 &pcie
315 max-link-speed = <1>;
316 msi-map = <0x0 &its 0x0 0x1000
317 phys = <&pcie_phy 0>, <&pcie_p
318 <&pcie_phy 2>, <&pcie_p
319 phy-names = "pcie-phy-0", "pci
320 "pcie-phy-2", "pci
321 ranges = <0x82000000 0x0 0xfa0
322 <0x81000000 0x0 0xfbe
323 resets = <&cru SRST_PCIE_CORE>
324 <&cru SRST_PCIE_MGMT_
325 <&cru SRST_PCIE_PM>,
326 <&cru SRST_A_PCIE>;
327 reset-names = "core", "mgmt",
328 "pm", "pclk", "a
329 status = "disabled";
330
331 pcie0_intc: interrupt-controll
332 interrupt-controller;
333 #address-cells = <0>;
334 #interrupt-cells = <1>
335 };
336 };
337
338 pcie0_ep: pcie-ep@f8000000 {
339 compatible = "rockchip,rk3399-
340 reg = <0x0 0xfd000000 0x0 0x10
341 <0x0 0xfa000000 0x0 0x20
342 reg-names = "apb-base", "mem-b
343 clocks = <&cru ACLK_PCIE>, <&c
344 <&cru PCLK_PCIE>, <&c
345 clock-names = "aclk", "aclk-pe
346 "hclk", "pm";
347 max-functions = /bits/ 8 <8>;
348 num-lanes = <4>;
349 resets = <&cru SRST_PCIE_CORE>
350 <&cru SRST_PCIE_MGMT_
351 <&cru SRST_PCIE_PM>,
352 <&cru SRST_A_PCIE>;
353 reset-names = "core", "mgmt",
354 "pm", "pclk", "a
355 phys = <&pcie_phy 0>, <&pcie_p
356 <&pcie_phy 2>, <&pcie_p
357 phy-names = "pcie-phy-0", "pci
358 "pcie-phy-2", "pci
359 rockchip,max-outbound-regions
360 pinctrl-names = "default";
361 pinctrl-0 = <&pcie_clkreqnb_cp
362 status = "disabled";
363 };
364
365 gmac: ethernet@fe300000 {
366 compatible = "rockchip,rk3399-
367 reg = <0x0 0xfe300000 0x0 0x10
368 interrupts = <GIC_SPI 12 IRQ_T
369 interrupt-names = "macirq";
370 clocks = <&cru SCLK_MAC>, <&cr
371 <&cru SCLK_MAC_TX>, <
372 <&cru SCLK_MACREF_OUT
373 <&cru PCLK_GMAC>;
374 clock-names = "stmmaceth", "ma
375 "mac_clk_tx", "c
376 "clk_mac_refout"
377 "pclk_mac";
378 power-domains = <&power RK3399
379 resets = <&cru SRST_A_GMAC>;
380 reset-names = "stmmaceth";
381 rockchip,grf = <&grf>;
382 snps,txpbl = <0x4>;
383 status = "disabled";
384 };
385
386 sdio0: mmc@fe310000 {
387 compatible = "rockchip,rk3399-
388 "rockchip,rk3288-
389 reg = <0x0 0xfe310000 0x0 0x40
390 interrupts = <GIC_SPI 64 IRQ_T
391 max-frequency = <150000000>;
392 clocks = <&cru HCLK_SDIO>, <&c
393 <&cru SCLK_SDIO_DRV>,
394 clock-names = "biu", "ciu", "c
395 fifo-depth = <0x100>;
396 power-domains = <&power RK3399
397 resets = <&cru SRST_SDIO0>;
398 reset-names = "reset";
399 status = "disabled";
400 };
401
402 sdmmc: mmc@fe320000 {
403 compatible = "rockchip,rk3399-
404 "rockchip,rk3288-
405 reg = <0x0 0xfe320000 0x0 0x40
406 interrupts = <GIC_SPI 65 IRQ_T
407 max-frequency = <150000000>;
408 assigned-clocks = <&cru HCLK_S
409 assigned-clock-rates = <200000
410 clocks = <&cru HCLK_SDMMC>, <&
411 <&cru SCLK_SDMMC_DRV>
412 clock-names = "biu", "ciu", "c
413 fifo-depth = <0x100>;
414 power-domains = <&power RK3399
415 resets = <&cru SRST_SDMMC>;
416 reset-names = "reset";
417 status = "disabled";
418 };
419
420 sdhci: mmc@fe330000 {
421 compatible = "rockchip,rk3399-
422 reg = <0x0 0xfe330000 0x0 0x10
423 interrupts = <GIC_SPI 11 IRQ_T
424 arasan,soc-ctl-syscon = <&grf>
425 assigned-clocks = <&cru SCLK_E
426 assigned-clock-rates = <200000
427 clocks = <&cru SCLK_EMMC>, <&c
428 clock-names = "clk_xin", "clk_
429 clock-output-names = "emmc_car
430 #clock-cells = <0>;
431 phys = <&emmc_phy>;
432 phy-names = "phy_arasan";
433 power-domains = <&power RK3399
434 disable-cqe-dcmd;
435 status = "disabled";
436 };
437
438 usb_host0_ehci: usb@fe380000 {
439 compatible = "generic-ehci";
440 reg = <0x0 0xfe380000 0x0 0x20
441 interrupts = <GIC_SPI 26 IRQ_T
442 clocks = <&cru HCLK_HOST0>, <&
443 <&u2phy0>;
444 phys = <&u2phy0_host>;
445 phy-names = "usb";
446 status = "disabled";
447 };
448
449 usb_host0_ohci: usb@fe3a0000 {
450 compatible = "generic-ohci";
451 reg = <0x0 0xfe3a0000 0x0 0x20
452 interrupts = <GIC_SPI 28 IRQ_T
453 clocks = <&cru HCLK_HOST0>, <&
454 <&u2phy0>;
455 phys = <&u2phy0_host>;
456 phy-names = "usb";
457 status = "disabled";
458 };
459
460 usb_host1_ehci: usb@fe3c0000 {
461 compatible = "generic-ehci";
462 reg = <0x0 0xfe3c0000 0x0 0x20
463 interrupts = <GIC_SPI 30 IRQ_T
464 clocks = <&cru HCLK_HOST1>, <&
465 <&u2phy1>;
466 phys = <&u2phy1_host>;
467 phy-names = "usb";
468 status = "disabled";
469 };
470
471 usb_host1_ohci: usb@fe3e0000 {
472 compatible = "generic-ohci";
473 reg = <0x0 0xfe3e0000 0x0 0x20
474 interrupts = <GIC_SPI 32 IRQ_T
475 clocks = <&cru HCLK_HOST1>, <&
476 <&u2phy1>;
477 phys = <&u2phy1_host>;
478 phy-names = "usb";
479 status = "disabled";
480 };
481
482 debug@fe430000 {
483 compatible = "arm,coresight-cp
484 reg = <0 0xfe430000 0 0x1000>;
485 clocks = <&cru PCLK_COREDBG_L>
486 clock-names = "apb_pclk";
487 cpu = <&cpu_l0>;
488 };
489
490 debug@fe432000 {
491 compatible = "arm,coresight-cp
492 reg = <0 0xfe432000 0 0x1000>;
493 clocks = <&cru PCLK_COREDBG_L>
494 clock-names = "apb_pclk";
495 cpu = <&cpu_l1>;
496 };
497
498 debug@fe434000 {
499 compatible = "arm,coresight-cp
500 reg = <0 0xfe434000 0 0x1000>;
501 clocks = <&cru PCLK_COREDBG_L>
502 clock-names = "apb_pclk";
503 cpu = <&cpu_l2>;
504 };
505
506 debug@fe436000 {
507 compatible = "arm,coresight-cp
508 reg = <0 0xfe436000 0 0x1000>;
509 clocks = <&cru PCLK_COREDBG_L>
510 clock-names = "apb_pclk";
511 cpu = <&cpu_l3>;
512 };
513
514 debug@fe610000 {
515 compatible = "arm,coresight-cp
516 reg = <0 0xfe610000 0 0x1000>;
517 clocks = <&cru PCLK_COREDBG_B>
518 clock-names = "apb_pclk";
519 cpu = <&cpu_b0>;
520 };
521
522 debug@fe710000 {
523 compatible = "arm,coresight-cp
524 reg = <0 0xfe710000 0 0x1000>;
525 clocks = <&cru PCLK_COREDBG_B>
526 clock-names = "apb_pclk";
527 cpu = <&cpu_b1>;
528 };
529
530 usbdrd3_0: usb@fe800000 {
531 compatible = "rockchip,rk3399-
532 #address-cells = <2>;
533 #size-cells = <2>;
534 ranges;
535 clocks = <&cru SCLK_USB3OTG0_R
536 <&cru ACLK_USB3OTG0>,
537 <&cru ACLK_USB3>, <&c
538 clock-names = "ref_clk", "susp
539 "bus_clk", "aclk
540 "aclk_usb3", "gr
541 resets = <&cru SRST_A_USB3_OTG
542 reset-names = "usb3-otg";
543 status = "disabled";
544
545 usbdrd_dwc3_0: usb@fe800000 {
546 compatible = "snps,dwc
547 reg = <0x0 0xfe800000
548 interrupts = <GIC_SPI
549 clocks = <&cru SCLK_US
550 <&cru SCLK_US
551 clock-names = "ref", "
552 dr_mode = "otg";
553 phys = <&u2phy0_otg>,
554 phy-names = "usb2-phy"
555 phy_type = "utmi_wide"
556 snps,dis_enblslpm_quir
557 snps,dis-u2-freeclk-ex
558 snps,dis_u2_susphy_qui
559 snps,dis-del-phy-power
560 snps,dis-tx-ipgap-line
561 power-domains = <&powe
562 status = "disabled";
563 };
564 };
565
566 usbdrd3_1: usb@fe900000 {
567 compatible = "rockchip,rk3399-
568 #address-cells = <2>;
569 #size-cells = <2>;
570 ranges;
571 clocks = <&cru SCLK_USB3OTG1_R
572 <&cru ACLK_USB3OTG1>,
573 <&cru ACLK_USB3>, <&c
574 clock-names = "ref_clk", "susp
575 "bus_clk", "aclk
576 "aclk_usb3", "gr
577 resets = <&cru SRST_A_USB3_OTG
578 reset-names = "usb3-otg";
579 status = "disabled";
580
581 usbdrd_dwc3_1: usb@fe900000 {
582 compatible = "snps,dwc
583 reg = <0x0 0xfe900000
584 interrupts = <GIC_SPI
585 clocks = <&cru SCLK_US
586 <&cru SCLK_US
587 clock-names = "ref", "
588 dr_mode = "otg";
589 phys = <&u2phy1_otg>,
590 phy-names = "usb2-phy"
591 phy_type = "utmi_wide"
592 snps,dis_enblslpm_quir
593 snps,dis-u2-freeclk-ex
594 snps,dis_u2_susphy_qui
595 snps,dis-del-phy-power
596 snps,dis-tx-ipgap-line
597 power-domains = <&powe
598 status = "disabled";
599 };
600 };
601
602 cdn_dp: dp@fec00000 {
603 compatible = "rockchip,rk3399-
604 reg = <0x0 0xfec00000 0x0 0x10
605 interrupts = <GIC_SPI 9 IRQ_TY
606 assigned-clocks = <&cru SCLK_D
607 assigned-clock-rates = <100000
608 clocks = <&cru SCLK_DP_CORE>,
609 <&cru SCLK_SPDIF_REC_
610 clock-names = "core-clk", "pcl
611 phys = <&tcphy0_dp>, <&tcphy1_
612 power-domains = <&power RK3399
613 resets = <&cru SRST_DPTX_SPDIF
614 <&cru SRST_P_UPHY0_AP
615 reset-names = "spdif", "dptx",
616 rockchip,grf = <&grf>;
617 #sound-dai-cells = <1>;
618 status = "disabled";
619
620 ports {
621 dp_in: port {
622 #address-cells
623 #size-cells =
624
625 dp_in_vopb: en
626 reg =
627 remote
628 };
629
630 dp_in_vopl: en
631 reg =
632 remote
633 };
634 };
635 };
636 };
637
638 gic: interrupt-controller@fee00000 {
639 compatible = "arm,gic-v3";
640 #interrupt-cells = <4>;
641 #address-cells = <2>;
642 #size-cells = <2>;
643 ranges;
644 interrupt-controller;
645
646 reg = <0x0 0xfee00000 0 0x1000
647 <0x0 0xfef00000 0 0xc000
648 <0x0 0xfff00000 0 0x1000
649 <0x0 0xfff10000 0 0x1000
650 <0x0 0xfff20000 0 0x1000
651 interrupts = <GIC_PPI 9 IRQ_TY
652 its: msi-controller@fee20000 {
653 compatible = "arm,gic-
654 msi-controller;
655 #msi-cells = <1>;
656 reg = <0x0 0xfee20000
657 };
658
659 ppi-partitions {
660 ppi_cluster0: interrup
661 affinity = <&c
662 };
663
664 ppi_cluster1: interrup
665 affinity = <&c
666 };
667 };
668 };
669
670 saradc: saradc@ff100000 {
671 compatible = "rockchip,rk3399-
672 reg = <0x0 0xff100000 0x0 0x10
673 interrupts = <GIC_SPI 62 IRQ_T
674 #io-channel-cells = <1>;
675 clocks = <&cru SCLK_SARADC>, <
676 clock-names = "saradc", "apb_p
677 resets = <&cru SRST_P_SARADC>;
678 reset-names = "saradc-apb";
679 status = "disabled";
680 };
681
682 crypto0: crypto@ff8b0000 {
683 compatible = "rockchip,rk3399-
684 reg = <0x0 0xff8b0000 0x0 0x40
685 interrupts = <GIC_SPI 0 IRQ_TY
686 clocks = <&cru HCLK_M_CRYPTO0>
687 clock-names = "hclk_master", "
688 resets = <&cru SRST_CRYPTO0>,
689 reset-names = "master", "slave
690 };
691
692 crypto1: crypto@ff8b8000 {
693 compatible = "rockchip,rk3399-
694 reg = <0x0 0xff8b8000 0x0 0x40
695 interrupts = <GIC_SPI 135 IRQ_
696 clocks = <&cru HCLK_M_CRYPTO1>
697 clock-names = "hclk_master", "
698 resets = <&cru SRST_CRYPTO1>,
699 reset-names = "master", "slave
700 };
701
702 i2c1: i2c@ff110000 {
703 compatible = "rockchip,rk3399-
704 reg = <0x0 0xff110000 0x0 0x10
705 assigned-clocks = <&cru SCLK_I
706 assigned-clock-rates = <200000
707 clocks = <&cru SCLK_I2C1>, <&c
708 clock-names = "i2c", "pclk";
709 interrupts = <GIC_SPI 59 IRQ_T
710 pinctrl-names = "default";
711 pinctrl-0 = <&i2c1_xfer>;
712 #address-cells = <1>;
713 #size-cells = <0>;
714 status = "disabled";
715 };
716
717 i2c2: i2c@ff120000 {
718 compatible = "rockchip,rk3399-
719 reg = <0x0 0xff120000 0x0 0x10
720 assigned-clocks = <&cru SCLK_I
721 assigned-clock-rates = <200000
722 clocks = <&cru SCLK_I2C2>, <&c
723 clock-names = "i2c", "pclk";
724 interrupts = <GIC_SPI 35 IRQ_T
725 pinctrl-names = "default";
726 pinctrl-0 = <&i2c2_xfer>;
727 #address-cells = <1>;
728 #size-cells = <0>;
729 status = "disabled";
730 };
731
732 i2c3: i2c@ff130000 {
733 compatible = "rockchip,rk3399-
734 reg = <0x0 0xff130000 0x0 0x10
735 assigned-clocks = <&cru SCLK_I
736 assigned-clock-rates = <200000
737 clocks = <&cru SCLK_I2C3>, <&c
738 clock-names = "i2c", "pclk";
739 interrupts = <GIC_SPI 34 IRQ_T
740 pinctrl-names = "default";
741 pinctrl-0 = <&i2c3_xfer>;
742 #address-cells = <1>;
743 #size-cells = <0>;
744 status = "disabled";
745 };
746
747 i2c5: i2c@ff140000 {
748 compatible = "rockchip,rk3399-
749 reg = <0x0 0xff140000 0x0 0x10
750 assigned-clocks = <&cru SCLK_I
751 assigned-clock-rates = <200000
752 clocks = <&cru SCLK_I2C5>, <&c
753 clock-names = "i2c", "pclk";
754 interrupts = <GIC_SPI 38 IRQ_T
755 pinctrl-names = "default";
756 pinctrl-0 = <&i2c5_xfer>;
757 #address-cells = <1>;
758 #size-cells = <0>;
759 status = "disabled";
760 };
761
762 i2c6: i2c@ff150000 {
763 compatible = "rockchip,rk3399-
764 reg = <0x0 0xff150000 0x0 0x10
765 assigned-clocks = <&cru SCLK_I
766 assigned-clock-rates = <200000
767 clocks = <&cru SCLK_I2C6>, <&c
768 clock-names = "i2c", "pclk";
769 interrupts = <GIC_SPI 37 IRQ_T
770 pinctrl-names = "default";
771 pinctrl-0 = <&i2c6_xfer>;
772 #address-cells = <1>;
773 #size-cells = <0>;
774 status = "disabled";
775 };
776
777 i2c7: i2c@ff160000 {
778 compatible = "rockchip,rk3399-
779 reg = <0x0 0xff160000 0x0 0x10
780 assigned-clocks = <&cru SCLK_I
781 assigned-clock-rates = <200000
782 clocks = <&cru SCLK_I2C7>, <&c
783 clock-names = "i2c", "pclk";
784 interrupts = <GIC_SPI 36 IRQ_T
785 pinctrl-names = "default";
786 pinctrl-0 = <&i2c7_xfer>;
787 #address-cells = <1>;
788 #size-cells = <0>;
789 status = "disabled";
790 };
791
792 uart0: serial@ff180000 {
793 compatible = "rockchip,rk3399-
794 reg = <0x0 0xff180000 0x0 0x10
795 clocks = <&cru SCLK_UART0>, <&
796 clock-names = "baudclk", "apb_
797 interrupts = <GIC_SPI 99 IRQ_T
798 reg-shift = <2>;
799 reg-io-width = <4>;
800 pinctrl-names = "default";
801 pinctrl-0 = <&uart0_xfer>;
802 status = "disabled";
803 };
804
805 uart1: serial@ff190000 {
806 compatible = "rockchip,rk3399-
807 reg = <0x0 0xff190000 0x0 0x10
808 clocks = <&cru SCLK_UART1>, <&
809 clock-names = "baudclk", "apb_
810 interrupts = <GIC_SPI 98 IRQ_T
811 reg-shift = <2>;
812 reg-io-width = <4>;
813 pinctrl-names = "default";
814 pinctrl-0 = <&uart1_xfer>;
815 status = "disabled";
816 };
817
818 uart2: serial@ff1a0000 {
819 compatible = "rockchip,rk3399-
820 reg = <0x0 0xff1a0000 0x0 0x10
821 clocks = <&cru SCLK_UART2>, <&
822 clock-names = "baudclk", "apb_
823 interrupts = <GIC_SPI 100 IRQ_
824 reg-shift = <2>;
825 reg-io-width = <4>;
826 pinctrl-names = "default";
827 pinctrl-0 = <&uart2c_xfer>;
828 status = "disabled";
829 };
830
831 uart3: serial@ff1b0000 {
832 compatible = "rockchip,rk3399-
833 reg = <0x0 0xff1b0000 0x0 0x10
834 clocks = <&cru SCLK_UART3>, <&
835 clock-names = "baudclk", "apb_
836 interrupts = <GIC_SPI 101 IRQ_
837 reg-shift = <2>;
838 reg-io-width = <4>;
839 pinctrl-names = "default";
840 pinctrl-0 = <&uart3_xfer>;
841 status = "disabled";
842 };
843
844 spi0: spi@ff1c0000 {
845 compatible = "rockchip,rk3399-
846 reg = <0x0 0xff1c0000 0x0 0x10
847 clocks = <&cru SCLK_SPI0>, <&c
848 clock-names = "spiclk", "apb_p
849 interrupts = <GIC_SPI 68 IRQ_T
850 dmas = <&dmac_peri 10>, <&dmac
851 dma-names = "tx", "rx";
852 pinctrl-names = "default";
853 pinctrl-0 = <&spi0_clk &spi0_t
854 #address-cells = <1>;
855 #size-cells = <0>;
856 status = "disabled";
857 };
858
859 spi1: spi@ff1d0000 {
860 compatible = "rockchip,rk3399-
861 reg = <0x0 0xff1d0000 0x0 0x10
862 clocks = <&cru SCLK_SPI1>, <&c
863 clock-names = "spiclk", "apb_p
864 interrupts = <GIC_SPI 53 IRQ_T
865 dmas = <&dmac_peri 12>, <&dmac
866 dma-names = "tx", "rx";
867 pinctrl-names = "default";
868 pinctrl-0 = <&spi1_clk &spi1_t
869 #address-cells = <1>;
870 #size-cells = <0>;
871 status = "disabled";
872 };
873
874 spi2: spi@ff1e0000 {
875 compatible = "rockchip,rk3399-
876 reg = <0x0 0xff1e0000 0x0 0x10
877 clocks = <&cru SCLK_SPI2>, <&c
878 clock-names = "spiclk", "apb_p
879 interrupts = <GIC_SPI 52 IRQ_T
880 dmas = <&dmac_peri 14>, <&dmac
881 dma-names = "tx", "rx";
882 pinctrl-names = "default";
883 pinctrl-0 = <&spi2_clk &spi2_t
884 #address-cells = <1>;
885 #size-cells = <0>;
886 status = "disabled";
887 };
888
889 spi4: spi@ff1f0000 {
890 compatible = "rockchip,rk3399-
891 reg = <0x0 0xff1f0000 0x0 0x10
892 clocks = <&cru SCLK_SPI4>, <&c
893 clock-names = "spiclk", "apb_p
894 interrupts = <GIC_SPI 67 IRQ_T
895 dmas = <&dmac_peri 18>, <&dmac
896 dma-names = "tx", "rx";
897 pinctrl-names = "default";
898 pinctrl-0 = <&spi4_clk &spi4_t
899 #address-cells = <1>;
900 #size-cells = <0>;
901 status = "disabled";
902 };
903
904 spi5: spi@ff200000 {
905 compatible = "rockchip,rk3399-
906 reg = <0x0 0xff200000 0x0 0x10
907 clocks = <&cru SCLK_SPI5>, <&c
908 clock-names = "spiclk", "apb_p
909 interrupts = <GIC_SPI 132 IRQ_
910 dmas = <&dmac_bus 8>, <&dmac_b
911 dma-names = "tx", "rx";
912 pinctrl-names = "default";
913 pinctrl-0 = <&spi5_clk &spi5_t
914 power-domains = <&power RK3399
915 #address-cells = <1>;
916 #size-cells = <0>;
917 status = "disabled";
918 };
919
920 thermal_zones: thermal-zones {
921 cpu_thermal: cpu-thermal {
922 polling-delay-passive
923 polling-delay = <1000>
924
925 thermal-sensors = <&ts
926
927 trips {
928 cpu_alert0: cp
929 temper
930 hyster
931 type =
932 };
933 cpu_alert1: cp
934 temper
935 hyster
936 type =
937 };
938 cpu_crit: cpu_
939 temper
940 hyster
941 type =
942 };
943 };
944
945 cooling-maps {
946 map0 {
947 trip =
948 coolin
949
950
951 };
952 map1 {
953 trip =
954 coolin
955
956
957
958
959
960
961 };
962 };
963 };
964
965 gpu_thermal: gpu-thermal {
966 polling-delay-passive
967 polling-delay = <1000>
968
969 thermal-sensors = <&ts
970
971 trips {
972 gpu_alert0: gp
973 temper
974 hyster
975 type =
976 };
977 gpu_crit: gpu_
978 temper
979 hyster
980 type =
981 };
982 };
983
984 cooling-maps {
985 map0 {
986 trip =
987 coolin
988
989 };
990 };
991 };
992 };
993
994 tsadc: tsadc@ff260000 {
995 compatible = "rockchip,rk3399-
996 reg = <0x0 0xff260000 0x0 0x10
997 interrupts = <GIC_SPI 97 IRQ_T
998 assigned-clocks = <&cru SCLK_T
999 assigned-clock-rates = <750000
1000 clocks = <&cru SCLK_TSADC>, <
1001 clock-names = "tsadc", "apb_p
1002 resets = <&cru SRST_TSADC>;
1003 reset-names = "tsadc-apb";
1004 rockchip,grf = <&grf>;
1005 rockchip,hw-tshut-temp = <950
1006 pinctrl-names = "init", "defa
1007 pinctrl-0 = <&otp_pin>;
1008 pinctrl-1 = <&otp_out>;
1009 pinctrl-2 = <&otp_pin>;
1010 #thermal-sensor-cells = <1>;
1011 status = "disabled";
1012 };
1013
1014 qos_emmc: qos@ffa58000 {
1015 compatible = "rockchip,rk3399
1016 reg = <0x0 0xffa58000 0x0 0x2
1017 };
1018
1019 qos_gmac: qos@ffa5c000 {
1020 compatible = "rockchip,rk3399
1021 reg = <0x0 0xffa5c000 0x0 0x2
1022 };
1023
1024 qos_pcie: qos@ffa60080 {
1025 compatible = "rockchip,rk3399
1026 reg = <0x0 0xffa60080 0x0 0x2
1027 };
1028
1029 qos_usb_host0: qos@ffa60100 {
1030 compatible = "rockchip,rk3399
1031 reg = <0x0 0xffa60100 0x0 0x2
1032 };
1033
1034 qos_usb_host1: qos@ffa60180 {
1035 compatible = "rockchip,rk3399
1036 reg = <0x0 0xffa60180 0x0 0x2
1037 };
1038
1039 qos_usb_otg0: qos@ffa70000 {
1040 compatible = "rockchip,rk3399
1041 reg = <0x0 0xffa70000 0x0 0x2
1042 };
1043
1044 qos_usb_otg1: qos@ffa70080 {
1045 compatible = "rockchip,rk3399
1046 reg = <0x0 0xffa70080 0x0 0x2
1047 };
1048
1049 qos_sd: qos@ffa74000 {
1050 compatible = "rockchip,rk3399
1051 reg = <0x0 0xffa74000 0x0 0x2
1052 };
1053
1054 qos_sdioaudio: qos@ffa76000 {
1055 compatible = "rockchip,rk3399
1056 reg = <0x0 0xffa76000 0x0 0x2
1057 };
1058
1059 qos_hdcp: qos@ffa90000 {
1060 compatible = "rockchip,rk3399
1061 reg = <0x0 0xffa90000 0x0 0x2
1062 };
1063
1064 qos_iep: qos@ffa98000 {
1065 compatible = "rockchip,rk3399
1066 reg = <0x0 0xffa98000 0x0 0x2
1067 };
1068
1069 qos_isp0_m0: qos@ffaa0000 {
1070 compatible = "rockchip,rk3399
1071 reg = <0x0 0xffaa0000 0x0 0x2
1072 };
1073
1074 qos_isp0_m1: qos@ffaa0080 {
1075 compatible = "rockchip,rk3399
1076 reg = <0x0 0xffaa0080 0x0 0x2
1077 };
1078
1079 qos_isp1_m0: qos@ffaa8000 {
1080 compatible = "rockchip,rk3399
1081 reg = <0x0 0xffaa8000 0x0 0x2
1082 };
1083
1084 qos_isp1_m1: qos@ffaa8080 {
1085 compatible = "rockchip,rk3399
1086 reg = <0x0 0xffaa8080 0x0 0x2
1087 };
1088
1089 qos_rga_r: qos@ffab0000 {
1090 compatible = "rockchip,rk3399
1091 reg = <0x0 0xffab0000 0x0 0x2
1092 };
1093
1094 qos_rga_w: qos@ffab0080 {
1095 compatible = "rockchip,rk3399
1096 reg = <0x0 0xffab0080 0x0 0x2
1097 };
1098
1099 qos_video_m0: qos@ffab8000 {
1100 compatible = "rockchip,rk3399
1101 reg = <0x0 0xffab8000 0x0 0x2
1102 };
1103
1104 qos_video_m1_r: qos@ffac0000 {
1105 compatible = "rockchip,rk3399
1106 reg = <0x0 0xffac0000 0x0 0x2
1107 };
1108
1109 qos_video_m1_w: qos@ffac0080 {
1110 compatible = "rockchip,rk3399
1111 reg = <0x0 0xffac0080 0x0 0x2
1112 };
1113
1114 qos_vop_big_r: qos@ffac8000 {
1115 compatible = "rockchip,rk3399
1116 reg = <0x0 0xffac8000 0x0 0x2
1117 };
1118
1119 qos_vop_big_w: qos@ffac8080 {
1120 compatible = "rockchip,rk3399
1121 reg = <0x0 0xffac8080 0x0 0x2
1122 };
1123
1124 qos_vop_little: qos@ffad0000 {
1125 compatible = "rockchip,rk3399
1126 reg = <0x0 0xffad0000 0x0 0x2
1127 };
1128
1129 qos_perihp: qos@ffad8080 {
1130 compatible = "rockchip,rk3399
1131 reg = <0x0 0xffad8080 0x0 0x2
1132 };
1133
1134 qos_gpu: qos@ffae0000 {
1135 compatible = "rockchip,rk3399
1136 reg = <0x0 0xffae0000 0x0 0x2
1137 };
1138
1139 pmu: power-management@ff310000 {
1140 compatible = "rockchip,rk3399
1141 reg = <0x0 0xff310000 0x0 0x1
1142
1143 /*
1144 * Note: RK3399 supports 6 vo
1145 * VD_CORE_B, VD_CENTER, VD_G
1146 * Some of the power domains
1147 * voltage domain.
1148 * The detail contents as bel
1149 */
1150 power: power-controller {
1151 compatible = "rockchi
1152 #power-domain-cells =
1153 #address-cells = <1>;
1154 #size-cells = <0>;
1155
1156 /* These power domain
1157 power-domain@RK3399_P
1158 reg = <RK3399
1159 clocks = <&cr
1160 <&cr
1161 pm_qos = <&qo
1162 #power-domain
1163 };
1164 power-domain@RK3399_P
1165 reg = <RK3399
1166 clocks = <&cr
1167 <&cr
1168 pm_qos = <&qo
1169 <&qo
1170 #power-domain
1171 };
1172 power-domain@RK3399_P
1173 reg = <RK3399
1174 clocks = <&cr
1175 <&cr
1176 pm_qos = <&qo
1177 #power-domain
1178 };
1179 power-domain@RK3399_P
1180 reg = <RK3399
1181 clocks = <&cr
1182 <&cr
1183 <&cr
1184 <&cr
1185 pm_qos = <&qo
1186 <&qo
1187 #power-domain
1188 };
1189
1190 /* These power domain
1191 power-domain@RK3399_P
1192 reg = <RK3399
1193 clocks = <&cr
1194 pm_qos = <&qo
1195 #power-domain
1196 };
1197
1198 /* These power domain
1199 power-domain@RK3399_P
1200 reg = <RK3399
1201 clocks = <&cr
1202 #power-domain
1203 };
1204 power-domain@RK3399_P
1205 reg = <RK3399
1206 clocks = <&cr
1207 pm_qos = <&qo
1208 #power-domain
1209 };
1210 power-domain@RK3399_P
1211 reg = <RK3399
1212 clocks = <&cr
1213 <&cr
1214 pm_qos = <&qo
1215 #power-domain
1216 };
1217 power-domain@RK3399_P
1218 reg = <RK3399
1219 clocks = <&cr
1220 <&cr
1221 pm_qos = <&qo
1222 #power-domain
1223 };
1224 power-domain@RK3399_P
1225 reg = <RK3399
1226 clocks = <&cr
1227 pm_qos = <&qo
1228 #power-domain
1229 };
1230 power-domain@RK3399_P
1231 reg = <RK3399
1232 clocks = <&cr
1233 <&cr
1234 #power-domain
1235 };
1236 power-domain@RK3399_P
1237 reg = <RK3399
1238 clocks = <&cr
1239 <&cr
1240 #power-domain
1241 };
1242 power-domain@RK3399_P
1243 reg = <RK3399
1244 clocks = <&cr
1245 pm_qos = <&qo
1246 <&qo
1247 #power-domain
1248 };
1249 power-domain@RK3399_P
1250 reg = <RK3399
1251 #power-domain
1252 #address-cell
1253 #size-cells =
1254
1255 power-domain@
1256 reg =
1257 clock
1258
1259
1260 pm_qo
1261 #powe
1262 };
1263 power-domain@
1264 reg =
1265 clock
1266
1267 pm_qo
1268
1269 #powe
1270 };
1271 power-domain@
1272 reg =
1273 clock
1274
1275 pm_qo
1276
1277 #powe
1278 };
1279 power-domain@
1280 reg =
1281 #powe
1282 #addr
1283 #size
1284
1285 power
1286
1287
1288
1289
1290
1291
1292 };
1293 power
1294
1295
1296
1297
1298
1299 };
1300 };
1301 };
1302 };
1303 };
1304
1305 pmugrf: syscon@ff320000 {
1306 compatible = "rockchip,rk3399
1307 reg = <0x0 0xff320000 0x0 0x1
1308
1309 pmu_io_domains: io-domains {
1310 compatible = "rockchi
1311 status = "disabled";
1312 };
1313 };
1314
1315 spi3: spi@ff350000 {
1316 compatible = "rockchip,rk3399
1317 reg = <0x0 0xff350000 0x0 0x1
1318 clocks = <&pmucru SCLK_SPI3_P
1319 clock-names = "spiclk", "apb_
1320 interrupts = <GIC_SPI 60 IRQ_
1321 pinctrl-names = "default";
1322 pinctrl-0 = <&spi3_clk &spi3_
1323 #address-cells = <1>;
1324 #size-cells = <0>;
1325 status = "disabled";
1326 };
1327
1328 uart4: serial@ff370000 {
1329 compatible = "rockchip,rk3399
1330 reg = <0x0 0xff370000 0x0 0x1
1331 clocks = <&pmucru SCLK_UART4_
1332 clock-names = "baudclk", "apb
1333 interrupts = <GIC_SPI 102 IRQ
1334 reg-shift = <2>;
1335 reg-io-width = <4>;
1336 pinctrl-names = "default";
1337 pinctrl-0 = <&uart4_xfer>;
1338 status = "disabled";
1339 };
1340
1341 i2c0: i2c@ff3c0000 {
1342 compatible = "rockchip,rk3399
1343 reg = <0x0 0xff3c0000 0x0 0x1
1344 assigned-clocks = <&pmucru SC
1345 assigned-clock-rates = <20000
1346 clocks = <&pmucru SCLK_I2C0_P
1347 clock-names = "i2c", "pclk";
1348 interrupts = <GIC_SPI 57 IRQ_
1349 pinctrl-names = "default";
1350 pinctrl-0 = <&i2c0_xfer>;
1351 #address-cells = <1>;
1352 #size-cells = <0>;
1353 status = "disabled";
1354 };
1355
1356 i2c4: i2c@ff3d0000 {
1357 compatible = "rockchip,rk3399
1358 reg = <0x0 0xff3d0000 0x0 0x1
1359 assigned-clocks = <&pmucru SC
1360 assigned-clock-rates = <20000
1361 clocks = <&pmucru SCLK_I2C4_P
1362 clock-names = "i2c", "pclk";
1363 interrupts = <GIC_SPI 56 IRQ_
1364 pinctrl-names = "default";
1365 pinctrl-0 = <&i2c4_xfer>;
1366 #address-cells = <1>;
1367 #size-cells = <0>;
1368 status = "disabled";
1369 };
1370
1371 i2c8: i2c@ff3e0000 {
1372 compatible = "rockchip,rk3399
1373 reg = <0x0 0xff3e0000 0x0 0x1
1374 assigned-clocks = <&pmucru SC
1375 assigned-clock-rates = <20000
1376 clocks = <&pmucru SCLK_I2C8_P
1377 clock-names = "i2c", "pclk";
1378 interrupts = <GIC_SPI 58 IRQ_
1379 pinctrl-names = "default";
1380 pinctrl-0 = <&i2c8_xfer>;
1381 #address-cells = <1>;
1382 #size-cells = <0>;
1383 status = "disabled";
1384 };
1385
1386 pwm0: pwm@ff420000 {
1387 compatible = "rockchip,rk3399
1388 reg = <0x0 0xff420000 0x0 0x1
1389 #pwm-cells = <3>;
1390 pinctrl-names = "default";
1391 pinctrl-0 = <&pwm0_pin>;
1392 clocks = <&pmucru PCLK_RKPWM_
1393 status = "disabled";
1394 };
1395
1396 pwm1: pwm@ff420010 {
1397 compatible = "rockchip,rk3399
1398 reg = <0x0 0xff420010 0x0 0x1
1399 #pwm-cells = <3>;
1400 pinctrl-names = "default";
1401 pinctrl-0 = <&pwm1_pin>;
1402 clocks = <&pmucru PCLK_RKPWM_
1403 status = "disabled";
1404 };
1405
1406 pwm2: pwm@ff420020 {
1407 compatible = "rockchip,rk3399
1408 reg = <0x0 0xff420020 0x0 0x1
1409 #pwm-cells = <3>;
1410 pinctrl-names = "default";
1411 pinctrl-0 = <&pwm2_pin>;
1412 clocks = <&pmucru PCLK_RKPWM_
1413 status = "disabled";
1414 };
1415
1416 pwm3: pwm@ff420030 {
1417 compatible = "rockchip,rk3399
1418 reg = <0x0 0xff420030 0x0 0x1
1419 #pwm-cells = <3>;
1420 pinctrl-names = "default";
1421 pinctrl-0 = <&pwm3a_pin>;
1422 clocks = <&pmucru PCLK_RKPWM_
1423 status = "disabled";
1424 };
1425
1426 dfi: dfi@ff630000 {
1427 reg = <0x00 0xff630000 0x00 0
1428 compatible = "rockchip,rk3399
1429 rockchip,pmu = <&pmugrf>;
1430 interrupts = <GIC_SPI 131 IRQ
1431 clocks = <&cru PCLK_DDR_MON>;
1432 clock-names = "pclk_ddr_mon";
1433 };
1434
1435 vpu: video-codec@ff650000 {
1436 compatible = "rockchip,rk3399
1437 reg = <0x0 0xff650000 0x0 0x8
1438 interrupts = <GIC_SPI 114 IRQ
1439 <GIC_SPI 113 IRQ
1440 interrupt-names = "vepu", "vd
1441 clocks = <&cru ACLK_VCODEC>,
1442 clock-names = "aclk", "hclk";
1443 iommus = <&vpu_mmu>;
1444 power-domains = <&power RK339
1445 };
1446
1447 vpu_mmu: iommu@ff650800 {
1448 compatible = "rockchip,iommu"
1449 reg = <0x0 0xff650800 0x0 0x4
1450 interrupts = <GIC_SPI 115 IRQ
1451 clocks = <&cru ACLK_VCODEC>,
1452 clock-names = "aclk", "iface"
1453 #iommu-cells = <0>;
1454 power-domains = <&power RK339
1455 };
1456
1457 vdec: video-codec@ff660000 {
1458 compatible = "rockchip,rk3399
1459 reg = <0x0 0xff660000 0x0 0x4
1460 interrupts = <GIC_SPI 116 IRQ
1461 clocks = <&cru ACLK_VDU>, <&c
1462 <&cru SCLK_VDU_CA>,
1463 clock-names = "axi", "ahb", "
1464 iommus = <&vdec_mmu>;
1465 power-domains = <&power RK339
1466 };
1467
1468 vdec_mmu: iommu@ff660480 {
1469 compatible = "rockchip,iommu"
1470 reg = <0x0 0xff660480 0x0 0x4
1471 interrupts = <GIC_SPI 117 IRQ
1472 clocks = <&cru ACLK_VDU>, <&c
1473 clock-names = "aclk", "iface"
1474 power-domains = <&power RK339
1475 #iommu-cells = <0>;
1476 };
1477
1478 iep_mmu: iommu@ff670800 {
1479 compatible = "rockchip,iommu"
1480 reg = <0x0 0xff670800 0x0 0x4
1481 interrupts = <GIC_SPI 42 IRQ_
1482 clocks = <&cru ACLK_IEP>, <&c
1483 clock-names = "aclk", "iface"
1484 #iommu-cells = <0>;
1485 status = "disabled";
1486 };
1487
1488 rga: rga@ff680000 {
1489 compatible = "rockchip,rk3399
1490 reg = <0x0 0xff680000 0x0 0x1
1491 interrupts = <GIC_SPI 55 IRQ_
1492 clocks = <&cru ACLK_RGA>, <&c
1493 clock-names = "aclk", "hclk",
1494 resets = <&cru SRST_RGA_CORE>
1495 reset-names = "core", "axi",
1496 power-domains = <&power RK339
1497 };
1498
1499 efuse0: efuse@ff690000 {
1500 compatible = "rockchip,rk3399
1501 reg = <0x0 0xff690000 0x0 0x8
1502 #address-cells = <1>;
1503 #size-cells = <1>;
1504 clocks = <&cru PCLK_EFUSE1024
1505 clock-names = "pclk_efuse";
1506
1507 /* Data cells */
1508 cpu_id: cpu-id@7 {
1509 reg = <0x07 0x10>;
1510 };
1511 cpub_leakage: cpu-leakage@17
1512 reg = <0x17 0x1>;
1513 };
1514 gpu_leakage: gpu-leakage@18 {
1515 reg = <0x18 0x1>;
1516 };
1517 center_leakage: center-leakag
1518 reg = <0x19 0x1>;
1519 };
1520 cpul_leakage: cpu-leakage@1a
1521 reg = <0x1a 0x1>;
1522 };
1523 logic_leakage: logic-leakage@
1524 reg = <0x1b 0x1>;
1525 };
1526 wafer_info: wafer-info@1c {
1527 reg = <0x1c 0x1>;
1528 };
1529 };
1530
1531 dmac_bus: dma-controller@ff6d0000 {
1532 compatible = "arm,pl330", "ar
1533 reg = <0x0 0xff6d0000 0x0 0x4
1534 interrupts = <GIC_SPI 5 IRQ_T
1535 <GIC_SPI 6 IRQ_T
1536 #dma-cells = <1>;
1537 arm,pl330-periph-burst;
1538 clocks = <&cru ACLK_DMAC0_PER
1539 clock-names = "apb_pclk";
1540 };
1541
1542 dmac_peri: dma-controller@ff6e0000 {
1543 compatible = "arm,pl330", "ar
1544 reg = <0x0 0xff6e0000 0x0 0x4
1545 interrupts = <GIC_SPI 7 IRQ_T
1546 <GIC_SPI 8 IRQ_T
1547 #dma-cells = <1>;
1548 arm,pl330-periph-burst;
1549 clocks = <&cru ACLK_DMAC1_PER
1550 clock-names = "apb_pclk";
1551 };
1552
1553 pmucru: clock-controller@ff750000 {
1554 compatible = "rockchip,rk3399
1555 reg = <0x0 0xff750000 0x0 0x1
1556 clocks = <&xin24m>;
1557 clock-names = "xin24m";
1558 rockchip,grf = <&pmugrf>;
1559 #clock-cells = <1>;
1560 #reset-cells = <1>;
1561 assigned-clocks = <&pmucru PL
1562 assigned-clock-rates = <67600
1563 };
1564
1565 cru: clock-controller@ff760000 {
1566 compatible = "rockchip,rk3399
1567 reg = <0x0 0xff760000 0x0 0x1
1568 clocks = <&xin24m>;
1569 clock-names = "xin24m";
1570 rockchip,grf = <&grf>;
1571 #clock-cells = <1>;
1572 #reset-cells = <1>;
1573 assigned-clocks =
1574 <&cru PLL_GPLL>, <&cr
1575 <&cru PLL_NPLL>,
1576 <&cru ACLK_PERIHP>, <
1577 <&cru PCLK_PERIHP>,
1578 <&cru ACLK_PERILP0>,
1579 <&cru PCLK_PERILP0>,
1580 <&cru HCLK_PERILP1>,
1581 <&cru ACLK_VIO>, <&cr
1582 <&cru ACLK_GIC_PRE>,
1583 <&cru PCLK_DDR>,
1584 <&cru ACLK_VDU>;
1585 assigned-clock-rates =
1586 <594000000>, <80000
1587 <1000000000>,
1588 <150000000>, <7500
1589 <37500000>,
1590 <100000000>, <10000
1591 <50000000>, <600000
1592 <100000000>, <5000
1593 <400000000>, <400000
1594 <200000000>,
1595 <200000000>,
1596 <400000000>;
1597 };
1598
1599 grf: syscon@ff770000 {
1600 compatible = "rockchip,rk3399
1601 reg = <0x0 0xff770000 0x0 0x1
1602 #address-cells = <1>;
1603 #size-cells = <1>;
1604
1605 io_domains: io-domains {
1606 compatible = "rockchi
1607 status = "disabled";
1608 };
1609
1610 mipi_dphy_rx0: mipi-dphy-rx0
1611 compatible = "rockchi
1612 clocks = <&cru SCLK_M
1613 <&cru SCLK_D
1614 <&cru PCLK_V
1615 clock-names = "dphy-r
1616 power-domains = <&pow
1617 #phy-cells = <0>;
1618 status = "disabled";
1619 };
1620
1621 u2phy0: usb2phy@e450 {
1622 compatible = "rockchi
1623 reg = <0xe450 0x10>;
1624 clocks = <&cru SCLK_U
1625 clock-names = "phyclk
1626 #clock-cells = <0>;
1627 clock-output-names =
1628 status = "disabled";
1629
1630 u2phy0_host: host-por
1631 #phy-cells =
1632 interrupts =
1633 interrupt-nam
1634 status = "dis
1635 };
1636
1637 u2phy0_otg: otg-port
1638 #phy-cells =
1639 interrupts =
1640
1641
1642 interrupt-nam
1643
1644 status = "dis
1645 };
1646 };
1647
1648 u2phy1: usb2phy@e460 {
1649 compatible = "rockchi
1650 reg = <0xe460 0x10>;
1651 clocks = <&cru SCLK_U
1652 clock-names = "phyclk
1653 #clock-cells = <0>;
1654 clock-output-names =
1655 status = "disabled";
1656
1657 u2phy1_host: host-por
1658 #phy-cells =
1659 interrupts =
1660 interrupt-nam
1661 status = "dis
1662 };
1663
1664 u2phy1_otg: otg-port
1665 #phy-cells =
1666 interrupts =
1667
1668
1669 interrupt-nam
1670
1671 status = "dis
1672 };
1673 };
1674
1675 emmc_phy: phy@f780 {
1676 compatible = "rockchi
1677 reg = <0xf780 0x24>;
1678 clocks = <&sdhci>;
1679 clock-names = "emmccl
1680 drive-impedance-ohm =
1681 #phy-cells = <0>;
1682 status = "disabled";
1683 };
1684
1685 pcie_phy: pcie-phy {
1686 compatible = "rockchi
1687 clocks = <&cru SCLK_P
1688 clock-names = "refclk
1689 #phy-cells = <1>;
1690 resets = <&cru SRST_P
1691 reset-names = "phy";
1692 status = "disabled";
1693 };
1694 };
1695
1696 tcphy0: phy@ff7c0000 {
1697 compatible = "rockchip,rk3399
1698 reg = <0x0 0xff7c0000 0x0 0x4
1699 clocks = <&cru SCLK_UPHY0_TCP
1700 <&cru SCLK_UPHY0_TCP
1701 clock-names = "tcpdcore", "tc
1702 assigned-clocks = <&cru SCLK_
1703 assigned-clock-rates = <50000
1704 power-domains = <&power RK339
1705 resets = <&cru SRST_UPHY0>,
1706 <&cru SRST_UPHY0_PIP
1707 <&cru SRST_P_UPHY0_T
1708 reset-names = "uphy", "uphy-p
1709 rockchip,grf = <&grf>;
1710 status = "disabled";
1711
1712 tcphy0_dp: dp-port {
1713 #phy-cells = <0>;
1714 };
1715
1716 tcphy0_usb3: usb3-port {
1717 #phy-cells = <0>;
1718 };
1719 };
1720
1721 tcphy1: phy@ff800000 {
1722 compatible = "rockchip,rk3399
1723 reg = <0x0 0xff800000 0x0 0x4
1724 clocks = <&cru SCLK_UPHY1_TCP
1725 <&cru SCLK_UPHY1_TCP
1726 clock-names = "tcpdcore", "tc
1727 assigned-clocks = <&cru SCLK_
1728 assigned-clock-rates = <50000
1729 power-domains = <&power RK339
1730 resets = <&cru SRST_UPHY1>,
1731 <&cru SRST_UPHY1_PIP
1732 <&cru SRST_P_UPHY1_T
1733 reset-names = "uphy", "uphy-p
1734 rockchip,grf = <&grf>;
1735 status = "disabled";
1736
1737 tcphy1_dp: dp-port {
1738 #phy-cells = <0>;
1739 };
1740
1741 tcphy1_usb3: usb3-port {
1742 #phy-cells = <0>;
1743 };
1744 };
1745
1746 watchdog@ff848000 {
1747 compatible = "rockchip,rk3399
1748 reg = <0x0 0xff848000 0x0 0x1
1749 clocks = <&cru PCLK_WDT>;
1750 interrupts = <GIC_SPI 120 IRQ
1751 };
1752
1753 rktimer: rktimer@ff850000 {
1754 compatible = "rockchip,rk3399
1755 reg = <0x0 0xff850000 0x0 0x1
1756 interrupts = <GIC_SPI 81 IRQ_
1757 clocks = <&cru PCLK_TIMER0>,
1758 clock-names = "pclk", "timer"
1759 };
1760
1761 spdif: spdif@ff870000 {
1762 compatible = "rockchip,rk3399
1763 reg = <0x0 0xff870000 0x0 0x1
1764 interrupts = <GIC_SPI 66 IRQ_
1765 dmas = <&dmac_bus 7>;
1766 dma-names = "tx";
1767 clock-names = "mclk", "hclk";
1768 clocks = <&cru SCLK_SPDIF_8CH
1769 pinctrl-names = "default";
1770 pinctrl-0 = <&spdif_bus>;
1771 power-domains = <&power RK339
1772 #sound-dai-cells = <0>;
1773 status = "disabled";
1774 };
1775
1776 i2s0: i2s@ff880000 {
1777 compatible = "rockchip,rk3399
1778 reg = <0x0 0xff880000 0x0 0x1
1779 rockchip,grf = <&grf>;
1780 interrupts = <GIC_SPI 39 IRQ_
1781 dmas = <&dmac_bus 0>, <&dmac_
1782 dma-names = "tx", "rx";
1783 clock-names = "i2s_clk", "i2s
1784 clocks = <&cru SCLK_I2S0_8CH>
1785 pinctrl-names = "bclk_on", "b
1786 pinctrl-0 = <&i2s0_8ch_bus>;
1787 pinctrl-1 = <&i2s0_8ch_bus_bc
1788 power-domains = <&power RK339
1789 #sound-dai-cells = <0>;
1790 status = "disabled";
1791 };
1792
1793 i2s1: i2s@ff890000 {
1794 compatible = "rockchip,rk3399
1795 reg = <0x0 0xff890000 0x0 0x1
1796 interrupts = <GIC_SPI 40 IRQ_
1797 dmas = <&dmac_bus 2>, <&dmac_
1798 dma-names = "tx", "rx";
1799 clock-names = "i2s_clk", "i2s
1800 clocks = <&cru SCLK_I2S1_8CH>
1801 pinctrl-names = "default";
1802 pinctrl-0 = <&i2s1_2ch_bus>;
1803 power-domains = <&power RK339
1804 #sound-dai-cells = <0>;
1805 status = "disabled";
1806 };
1807
1808 i2s2: i2s@ff8a0000 {
1809 compatible = "rockchip,rk3399
1810 reg = <0x0 0xff8a0000 0x0 0x1
1811 interrupts = <GIC_SPI 41 IRQ_
1812 dmas = <&dmac_bus 4>, <&dmac_
1813 dma-names = "tx", "rx";
1814 clock-names = "i2s_clk", "i2s
1815 clocks = <&cru SCLK_I2S2_8CH>
1816 power-domains = <&power RK339
1817 #sound-dai-cells = <0>;
1818 status = "disabled";
1819 };
1820
1821 vopl: vop@ff8f0000 {
1822 compatible = "rockchip,rk3399
1823 reg = <0x0 0xff8f0000 0x0 0x2
1824 interrupts = <GIC_SPI 119 IRQ
1825 assigned-clocks = <&cru ACLK_
1826 assigned-clock-rates = <40000
1827 clocks = <&cru ACLK_VOP1>, <&
1828 clock-names = "aclk_vop", "dc
1829 iommus = <&vopl_mmu>;
1830 power-domains = <&power RK339
1831 resets = <&cru SRST_A_VOP1>,
1832 reset-names = "axi", "ahb", "
1833 status = "disabled";
1834
1835 vopl_out: port {
1836 #address-cells = <1>;
1837 #size-cells = <0>;
1838
1839 vopl_out_mipi: endpoi
1840 reg = <0>;
1841 remote-endpoi
1842 };
1843
1844 vopl_out_edp: endpoin
1845 reg = <1>;
1846 remote-endpoi
1847 };
1848
1849 vopl_out_hdmi: endpoi
1850 reg = <2>;
1851 remote-endpoi
1852 };
1853
1854 vopl_out_mipi1: endpo
1855 reg = <3>;
1856 remote-endpoi
1857 };
1858
1859 vopl_out_dp: endpoint
1860 reg = <4>;
1861 remote-endpoi
1862 };
1863 };
1864 };
1865
1866 vopl_mmu: iommu@ff8f3f00 {
1867 compatible = "rockchip,iommu"
1868 reg = <0x0 0xff8f3f00 0x0 0x1
1869 interrupts = <GIC_SPI 119 IRQ
1870 clocks = <&cru ACLK_VOP1>, <&
1871 clock-names = "aclk", "iface"
1872 power-domains = <&power RK339
1873 #iommu-cells = <0>;
1874 status = "disabled";
1875 };
1876
1877 vopb: vop@ff900000 {
1878 compatible = "rockchip,rk3399
1879 reg = <0x0 0xff900000 0x0 0x2
1880 interrupts = <GIC_SPI 118 IRQ
1881 assigned-clocks = <&cru ACLK_
1882 assigned-clock-rates = <40000
1883 clocks = <&cru ACLK_VOP0>, <&
1884 clock-names = "aclk_vop", "dc
1885 iommus = <&vopb_mmu>;
1886 power-domains = <&power RK339
1887 resets = <&cru SRST_A_VOP0>,
1888 reset-names = "axi", "ahb", "
1889 status = "disabled";
1890
1891 vopb_out: port {
1892 #address-cells = <1>;
1893 #size-cells = <0>;
1894
1895 vopb_out_edp: endpoin
1896 reg = <0>;
1897 remote-endpoi
1898 };
1899
1900 vopb_out_mipi: endpoi
1901 reg = <1>;
1902 remote-endpoi
1903 };
1904
1905 vopb_out_hdmi: endpoi
1906 reg = <2>;
1907 remote-endpoi
1908 };
1909
1910 vopb_out_mipi1: endpo
1911 reg = <3>;
1912 remote-endpoi
1913 };
1914
1915 vopb_out_dp: endpoint
1916 reg = <4>;
1917 remote-endpoi
1918 };
1919 };
1920 };
1921
1922 vopb_mmu: iommu@ff903f00 {
1923 compatible = "rockchip,iommu"
1924 reg = <0x0 0xff903f00 0x0 0x1
1925 interrupts = <GIC_SPI 118 IRQ
1926 clocks = <&cru ACLK_VOP0>, <&
1927 clock-names = "aclk", "iface"
1928 power-domains = <&power RK339
1929 #iommu-cells = <0>;
1930 status = "disabled";
1931 };
1932
1933 isp0: isp0@ff910000 {
1934 compatible = "rockchip,rk3399
1935 reg = <0x0 0xff910000 0x0 0x4
1936 interrupts = <GIC_SPI 43 IRQ_
1937 clocks = <&cru SCLK_ISP0>,
1938 <&cru ACLK_ISP0_WRAP
1939 <&cru HCLK_ISP0_WRAP
1940 clock-names = "isp", "aclk",
1941 iommus = <&isp0_mmu>;
1942 phys = <&mipi_dphy_rx0>;
1943 phy-names = "dphy";
1944 power-domains = <&power RK339
1945 status = "disabled";
1946
1947 ports {
1948 #address-cells = <1>;
1949 #size-cells = <0>;
1950
1951 port@0 {
1952 reg = <0>;
1953 #address-cell
1954 #size-cells =
1955 };
1956 };
1957 };
1958
1959 isp0_mmu: iommu@ff914000 {
1960 compatible = "rockchip,iommu"
1961 reg = <0x0 0xff914000 0x0 0x1
1962 interrupts = <GIC_SPI 43 IRQ_
1963 clocks = <&cru ACLK_ISP0_WRAP
1964 clock-names = "aclk", "iface"
1965 #iommu-cells = <0>;
1966 power-domains = <&power RK339
1967 rockchip,disable-mmu-reset;
1968 };
1969
1970 isp1: isp1@ff920000 {
1971 compatible = "rockchip,rk3399
1972 reg = <0x0 0xff920000 0x0 0x4
1973 interrupts = <GIC_SPI 44 IRQ_
1974 clocks = <&cru SCLK_ISP1>,
1975 <&cru ACLK_ISP1_WRAP
1976 <&cru HCLK_ISP1_WRAP
1977 clock-names = "isp", "aclk",
1978 iommus = <&isp1_mmu>;
1979 phys = <&mipi_dsi1>;
1980 phy-names = "dphy";
1981 power-domains = <&power RK339
1982 status = "disabled";
1983
1984 ports {
1985 #address-cells = <1>;
1986 #size-cells = <0>;
1987
1988 port@0 {
1989 reg = <0>;
1990 #address-cell
1991 #size-cells =
1992 };
1993 };
1994 };
1995
1996 isp1_mmu: iommu@ff924000 {
1997 compatible = "rockchip,iommu"
1998 reg = <0x0 0xff924000 0x0 0x1
1999 interrupts = <GIC_SPI 44 IRQ_
2000 clocks = <&cru ACLK_ISP1_WRAP
2001 clock-names = "aclk", "iface"
2002 #iommu-cells = <0>;
2003 power-domains = <&power RK339
2004 rockchip,disable-mmu-reset;
2005 };
2006
2007 hdmi_sound: hdmi-sound {
2008 compatible = "simple-audio-ca
2009 simple-audio-card,format = "i
2010 simple-audio-card,mclk-fs = <
2011 simple-audio-card,name = "hdm
2012 status = "disabled";
2013
2014 simple-audio-card,cpu {
2015 sound-dai = <&i2s2>;
2016 };
2017 simple-audio-card,codec {
2018 sound-dai = <&hdmi>;
2019 };
2020 };
2021
2022 hdmi: hdmi@ff940000 {
2023 compatible = "rockchip,rk3399
2024 reg = <0x0 0xff940000 0x0 0x2
2025 reg-io-width = <4>;
2026 interrupts = <GIC_SPI 23 IRQ_
2027 clocks = <&cru PCLK_HDMI_CTRL
2028 <&cru SCLK_HDMI_SFR>
2029 <&cru SCLK_HDMI_CEC>
2030 <&cru PCLK_VIO_GRF>,
2031 <&cru PLL_VPLL>;
2032 clock-names = "iahb", "isfr",
2033 power-domains = <&power RK339
2034 rockchip,grf = <&grf>;
2035 #sound-dai-cells = <0>;
2036 status = "disabled";
2037
2038 ports {
2039 #address-cells = <1>;
2040 #size-cells = <0>;
2041
2042 hdmi_in: port@0 {
2043 reg = <0>;
2044 #address-cell
2045 #size-cells =
2046
2047 hdmi_in_vopb:
2048 reg =
2049 remot
2050 };
2051 hdmi_in_vopl:
2052 reg =
2053 remot
2054 };
2055 };
2056
2057 hdmi_out: port@1 {
2058 reg = <1>;
2059 };
2060 };
2061 };
2062
2063 mipi_dsi: dsi@ff960000 {
2064 compatible = "rockchip,rk3399
2065 reg = <0x0 0xff960000 0x0 0x8
2066 interrupts = <GIC_SPI 45 IRQ_
2067 clocks = <&cru SCLK_DPHY_PLL>
2068 <&cru SCLK_DPHY_TX0_
2069 clock-names = "ref", "pclk",
2070 power-domains = <&power RK339
2071 resets = <&cru SRST_P_MIPI_DS
2072 reset-names = "apb";
2073 rockchip,grf = <&grf>;
2074 #address-cells = <1>;
2075 #size-cells = <0>;
2076 status = "disabled";
2077
2078 ports {
2079 #address-cells = <1>;
2080 #size-cells = <0>;
2081
2082 mipi_in: port@0 {
2083 reg = <0>;
2084 #address-cell
2085 #size-cells =
2086
2087 mipi_in_vopb:
2088 reg =
2089 remot
2090 };
2091
2092 mipi_in_vopl:
2093 reg =
2094 remot
2095 };
2096 };
2097
2098 mipi_out: port@1 {
2099 reg = <1>;
2100 };
2101 };
2102 };
2103
2104 mipi_dsi1: dsi@ff968000 {
2105 compatible = "rockchip,rk3399
2106 reg = <0x0 0xff968000 0x0 0x8
2107 interrupts = <GIC_SPI 46 IRQ_
2108 clocks = <&cru SCLK_DPHY_PLL>
2109 <&cru SCLK_DPHY_TX1R
2110 clock-names = "ref", "pclk",
2111 power-domains = <&power RK339
2112 resets = <&cru SRST_P_MIPI_DS
2113 reset-names = "apb";
2114 rockchip,grf = <&grf>;
2115 #address-cells = <1>;
2116 #size-cells = <0>;
2117 #phy-cells = <0>;
2118 status = "disabled";
2119
2120 ports {
2121 #address-cells = <1>;
2122 #size-cells = <0>;
2123
2124 mipi1_in: port@0 {
2125 reg = <0>;
2126 #address-cell
2127 #size-cells =
2128
2129 mipi1_in_vopb
2130 reg =
2131 remot
2132 };
2133
2134 mipi1_in_vopl
2135 reg =
2136 remot
2137 };
2138 };
2139
2140 mipi1_out: port@1 {
2141 reg = <1>;
2142 };
2143 };
2144 };
2145
2146 edp: dp@ff970000 {
2147 compatible = "rockchip,rk3399
2148 reg = <0x0 0xff970000 0x0 0x8
2149 interrupts = <GIC_SPI 10 IRQ_
2150 clocks = <&cru PCLK_EDP>, <&c
2151 clock-names = "dp", "pclk", "
2152 pinctrl-names = "default";
2153 pinctrl-0 = <&edp_hpd>;
2154 power-domains = <&power RK339
2155 resets = <&cru SRST_P_EDP_CTR
2156 reset-names = "dp";
2157 rockchip,grf = <&grf>;
2158 status = "disabled";
2159
2160 ports {
2161 #address-cells = <1>;
2162 #size-cells = <0>;
2163
2164 edp_in: port@0 {
2165 reg = <0>;
2166 #address-cell
2167 #size-cells =
2168
2169 edp_in_vopb:
2170 reg =
2171 remot
2172 };
2173
2174 edp_in_vopl:
2175 reg =
2176 remot
2177 };
2178 };
2179
2180 edp_out: port@1 {
2181 reg = <1>;
2182 };
2183 };
2184 };
2185
2186 gpu: gpu@ff9a0000 {
2187 compatible = "rockchip,rk3399
2188 reg = <0x0 0xff9a0000 0x0 0x1
2189 interrupts = <GIC_SPI 20 IRQ_
2190 <GIC_SPI 21 IRQ_
2191 <GIC_SPI 19 IRQ_
2192 interrupt-names = "job", "mmu
2193 clocks = <&cru ACLK_GPU>;
2194 #cooling-cells = <2>;
2195 dynamic-power-coefficient = <
2196 power-domains = <&power RK339
2197 status = "disabled";
2198 };
2199
2200 pinctrl: pinctrl {
2201 compatible = "rockchip,rk3399
2202 rockchip,grf = <&grf>;
2203 rockchip,pmu = <&pmugrf>;
2204 #address-cells = <2>;
2205 #size-cells = <2>;
2206 ranges;
2207
2208 gpio0: gpio@ff720000 {
2209 compatible = "rockchi
2210 reg = <0x0 0xff720000
2211 clocks = <&pmucru PCL
2212 interrupts = <GIC_SPI
2213
2214 gpio-controller;
2215 #gpio-cells = <0x2>;
2216
2217 interrupt-controller;
2218 #interrupt-cells = <0
2219 };
2220
2221 gpio1: gpio@ff730000 {
2222 compatible = "rockchi
2223 reg = <0x0 0xff730000
2224 clocks = <&pmucru PCL
2225 interrupts = <GIC_SPI
2226
2227 gpio-controller;
2228 #gpio-cells = <0x2>;
2229
2230 interrupt-controller;
2231 #interrupt-cells = <0
2232 };
2233
2234 gpio2: gpio@ff780000 {
2235 compatible = "rockchi
2236 reg = <0x0 0xff780000
2237 clocks = <&cru PCLK_G
2238 interrupts = <GIC_SPI
2239
2240 gpio-controller;
2241 #gpio-cells = <0x2>;
2242
2243 interrupt-controller;
2244 #interrupt-cells = <0
2245 };
2246
2247 gpio3: gpio@ff788000 {
2248 compatible = "rockchi
2249 reg = <0x0 0xff788000
2250 clocks = <&cru PCLK_G
2251 interrupts = <GIC_SPI
2252
2253 gpio-controller;
2254 #gpio-cells = <0x2>;
2255
2256 interrupt-controller;
2257 #interrupt-cells = <0
2258 };
2259
2260 gpio4: gpio@ff790000 {
2261 compatible = "rockchi
2262 reg = <0x0 0xff790000
2263 clocks = <&cru PCLK_G
2264 interrupts = <GIC_SPI
2265
2266 gpio-controller;
2267 #gpio-cells = <0x2>;
2268
2269 interrupt-controller;
2270 #interrupt-cells = <0
2271 };
2272
2273 pcfg_pull_up: pcfg-pull-up {
2274 bias-pull-up;
2275 };
2276
2277 pcfg_pull_down: pcfg-pull-dow
2278 bias-pull-down;
2279 };
2280
2281 pcfg_pull_none: pcfg-pull-non
2282 bias-disable;
2283 };
2284
2285 pcfg_pull_none_12ma: pcfg-pul
2286 bias-disable;
2287 drive-strength = <12>
2288 };
2289
2290 pcfg_pull_none_13ma: pcfg-pul
2291 bias-disable;
2292 drive-strength = <13>
2293 };
2294
2295 pcfg_pull_none_18ma: pcfg-pul
2296 bias-disable;
2297 drive-strength = <18>
2298 };
2299
2300 pcfg_pull_none_20ma: pcfg-pul
2301 bias-disable;
2302 drive-strength = <20>
2303 };
2304
2305 pcfg_pull_up_2ma: pcfg-pull-u
2306 bias-pull-up;
2307 drive-strength = <2>;
2308 };
2309
2310 pcfg_pull_up_8ma: pcfg-pull-u
2311 bias-pull-up;
2312 drive-strength = <8>;
2313 };
2314
2315 pcfg_pull_up_18ma: pcfg-pull-
2316 bias-pull-up;
2317 drive-strength = <18>
2318 };
2319
2320 pcfg_pull_up_20ma: pcfg-pull-
2321 bias-pull-up;
2322 drive-strength = <20>
2323 };
2324
2325 pcfg_pull_down_4ma: pcfg-pull
2326 bias-pull-down;
2327 drive-strength = <4>;
2328 };
2329
2330 pcfg_pull_down_8ma: pcfg-pull
2331 bias-pull-down;
2332 drive-strength = <8>;
2333 };
2334
2335 pcfg_pull_down_12ma: pcfg-pul
2336 bias-pull-down;
2337 drive-strength = <12>
2338 };
2339
2340 pcfg_pull_down_18ma: pcfg-pul
2341 bias-pull-down;
2342 drive-strength = <18>
2343 };
2344
2345 pcfg_pull_down_20ma: pcfg-pul
2346 bias-pull-down;
2347 drive-strength = <20>
2348 };
2349
2350 pcfg_output_high: pcfg-output
2351 output-high;
2352 };
2353
2354 pcfg_output_low: pcfg-output-
2355 output-low;
2356 };
2357
2358 pcfg_input_enable: pcfg-input
2359 input-enable;
2360 };
2361
2362 pcfg_input_pull_up: pcfg-inpu
2363 input-enable;
2364 bias-pull-up;
2365 };
2366
2367 pcfg_input_pull_down: pcfg-in
2368 input-enable;
2369 bias-pull-down;
2370 };
2371
2372 clock {
2373 clk_32k: clk-32k {
2374 rockchip,pins
2375 };
2376 };
2377
2378 cif {
2379 cif_clkin: cif-clkin
2380 rockchip,pins
2381 <2 RK
2382 };
2383
2384 cif_clkouta: cif-clko
2385 rockchip,pins
2386 <2 RK
2387 };
2388 };
2389
2390 edp {
2391 edp_hpd: edp-hpd {
2392 rockchip,pins
2393 <4 RK
2394 };
2395 };
2396
2397 gmac {
2398 rgmii_pins: rgmii-pin
2399 rockchip,pins
2400 /* ma
2401 <3 RK
2402 /* ma
2403 <3 RK
2404 /* ma
2405 <3 RK
2406 /* ma
2407 <3 RK
2408 /* ma
2409 <3 RK
2410 /* ma
2411 <3 RK
2412 /* ma
2413 <3 RK
2414 /* ma
2415 <3 RK
2416 /* ma
2417 <3 RK
2418 /* ma
2419 <3 RK
2420 /* ma
2421 <3 RK
2422 /* ma
2423 <3 RK
2424 /* ma
2425 <3 RK
2426 /* ma
2427 <3 RK
2428 /* ma
2429 <3 RK
2430 };
2431
2432 rmii_pins: rmii-pins
2433 rockchip,pins
2434 /* ma
2435 <3 RK
2436 /* ma
2437 <3 RK
2438 /* ma
2439 <3 RK
2440 /* ma
2441 <3 RK
2442 /* ma
2443 <3 RK
2444 /* ma
2445 <3 RK
2446 /* ma
2447 <3 RK
2448 /* ma
2449 <3 RK
2450 /* ma
2451 <3 RK
2452 /* ma
2453 <3 RK
2454 };
2455 };
2456
2457 i2c0 {
2458 i2c0_xfer: i2c0-xfer
2459 rockchip,pins
2460 <1 RK
2461 <1 RK
2462 };
2463 };
2464
2465 i2c1 {
2466 i2c1_xfer: i2c1-xfer
2467 rockchip,pins
2468 <4 RK
2469 <4 RK
2470 };
2471 };
2472
2473 i2c2 {
2474 i2c2_xfer: i2c2-xfer
2475 rockchip,pins
2476 <2 RK
2477 <2 RK
2478 };
2479 };
2480
2481 i2c3 {
2482 i2c3_xfer: i2c3-xfer
2483 rockchip,pins
2484 <4 RK
2485 <4 RK
2486 };
2487 };
2488
2489 i2c4 {
2490 i2c4_xfer: i2c4-xfer
2491 rockchip,pins
2492 <1 RK
2493 <1 RK
2494 };
2495 };
2496
2497 i2c5 {
2498 i2c5_xfer: i2c5-xfer
2499 rockchip,pins
2500 <3 RK
2501 <3 RK
2502 };
2503 };
2504
2505 i2c6 {
2506 i2c6_xfer: i2c6-xfer
2507 rockchip,pins
2508 <2 RK
2509 <2 RK
2510 };
2511 };
2512
2513 i2c7 {
2514 i2c7_xfer: i2c7-xfer
2515 rockchip,pins
2516 <2 RK
2517 <2 RK
2518 };
2519 };
2520
2521 i2c8 {
2522 i2c8_xfer: i2c8-xfer
2523 rockchip,pins
2524 <1 RK
2525 <1 RK
2526 };
2527 };
2528
2529 i2s0 {
2530 i2s0_2ch_bus: i2s0-2c
2531 rockchip,pins
2532 <3 RK
2533 <3 RK
2534 <3 RK
2535 <3 RK
2536 <3 RK
2537 <4 RK
2538 };
2539
2540 i2s0_2ch_bus_bclk_off
2541 rockchip,pins
2542 <3 RK
2543 <3 RK
2544 <3 RK
2545 <3 RK
2546 <3 RK
2547 <4 RK
2548 };
2549
2550 i2s0_8ch_bus: i2s0-8c
2551 rockchip,pins
2552 <3 RK
2553 <3 RK
2554 <3 RK
2555 <3 RK
2556 <3 RK
2557 <3 RK
2558 <3 RK
2559 <3 RK
2560 <4 RK
2561 };
2562
2563 i2s0_8ch_bus_bclk_off
2564 rockchip,pins
2565 <3 RK
2566 <3 RK
2567 <3 RK
2568 <3 RK
2569 <3 RK
2570 <3 RK
2571 <3 RK
2572 <3 RK
2573 <4 RK
2574 };
2575 };
2576
2577 i2s1 {
2578 i2s1_2ch_bus: i2s1-2c
2579 rockchip,pins
2580 <4 RK
2581 <4 RK
2582 <4 RK
2583 <4 RK
2584 <4 RK
2585 };
2586
2587 i2s1_2ch_bus_bclk_off
2588 rockchip,pins
2589 <4 RK
2590 <4 RK
2591 <4 RK
2592 <4 RK
2593 <4 RK
2594 };
2595 };
2596
2597 sdio0 {
2598 sdio0_bus1: sdio0-bus
2599 rockchip,pins
2600 <2 RK
2601 };
2602
2603 sdio0_bus4: sdio0-bus
2604 rockchip,pins
2605 <2 RK
2606 <2 RK
2607 <2 RK
2608 <2 RK
2609 };
2610
2611 sdio0_cmd: sdio0-cmd
2612 rockchip,pins
2613 <2 RK
2614 };
2615
2616 sdio0_clk: sdio0-clk
2617 rockchip,pins
2618 <2 RK
2619 };
2620
2621 sdio0_cd: sdio0-cd {
2622 rockchip,pins
2623 <2 RK
2624 };
2625
2626 sdio0_pwr: sdio0-pwr
2627 rockchip,pins
2628 <2 RK
2629 };
2630
2631 sdio0_bkpwr: sdio0-bk
2632 rockchip,pins
2633 <2 RK
2634 };
2635
2636 sdio0_wp: sdio0-wp {
2637 rockchip,pins
2638 <0 RK
2639 };
2640
2641 sdio0_int: sdio0-int
2642 rockchip,pins
2643 <0 RK
2644 };
2645 };
2646
2647 sdmmc {
2648 sdmmc_bus1: sdmmc-bus
2649 rockchip,pins
2650 <4 RK
2651 };
2652
2653 sdmmc_bus4: sdmmc-bus
2654 rockchip,pins
2655 <4 RK
2656 <4 RK
2657 <4 RK
2658 <4 RK
2659 };
2660
2661 sdmmc_clk: sdmmc-clk
2662 rockchip,pins
2663 <4 RK
2664 };
2665
2666 sdmmc_cmd: sdmmc-cmd
2667 rockchip,pins
2668 <4 RK
2669 };
2670
2671 sdmmc_cd: sdmmc-cd {
2672 rockchip,pins
2673 <0 RK
2674 };
2675
2676 sdmmc_wp: sdmmc-wp {
2677 rockchip,pins
2678 <0 RK
2679 };
2680 };
2681
2682 suspend {
2683 ap_pwroff: ap-pwroff
2684 rockchip,pins
2685 };
2686
2687 ddrio_pwroff: ddrio-p
2688 rockchip,pins
2689 };
2690 };
2691
2692 spdif {
2693 spdif_bus: spdif-bus
2694 rockchip,pins
2695 <4 RK
2696 };
2697
2698 spdif_bus_1: spdif-bu
2699 rockchip,pins
2700 <3 RK
2701 };
2702 };
2703
2704 spi0 {
2705 spi0_clk: spi0-clk {
2706 rockchip,pins
2707 <3 RK
2708 };
2709 spi0_cs0: spi0-cs0 {
2710 rockchip,pins
2711 <3 RK
2712 };
2713 spi0_cs1: spi0-cs1 {
2714 rockchip,pins
2715 <3 RK
2716 };
2717 spi0_tx: spi0-tx {
2718 rockchip,pins
2719 <3 RK
2720 };
2721 spi0_rx: spi0-rx {
2722 rockchip,pins
2723 <3 RK
2724 };
2725 };
2726
2727 spi1 {
2728 spi1_clk: spi1-clk {
2729 rockchip,pins
2730 <1 RK
2731 };
2732 spi1_cs0: spi1-cs0 {
2733 rockchip,pins
2734 <1 RK
2735 };
2736 spi1_rx: spi1-rx {
2737 rockchip,pins
2738 <1 RK
2739 };
2740 spi1_tx: spi1-tx {
2741 rockchip,pins
2742 <1 RK
2743 };
2744 };
2745
2746 spi2 {
2747 spi2_clk: spi2-clk {
2748 rockchip,pins
2749 <2 RK
2750 };
2751 spi2_cs0: spi2-cs0 {
2752 rockchip,pins
2753 <2 RK
2754 };
2755 spi2_rx: spi2-rx {
2756 rockchip,pins
2757 <2 RK
2758 };
2759 spi2_tx: spi2-tx {
2760 rockchip,pins
2761 <2 RK
2762 };
2763 };
2764
2765 spi3 {
2766 spi3_clk: spi3-clk {
2767 rockchip,pins
2768 <1 RK
2769 };
2770 spi3_cs0: spi3-cs0 {
2771 rockchip,pins
2772 <1 RK
2773 };
2774 spi3_rx: spi3-rx {
2775 rockchip,pins
2776 <1 RK
2777 };
2778 spi3_tx: spi3-tx {
2779 rockchip,pins
2780 <1 RK
2781 };
2782 };
2783
2784 spi4 {
2785 spi4_clk: spi4-clk {
2786 rockchip,pins
2787 <3 RK
2788 };
2789 spi4_cs0: spi4-cs0 {
2790 rockchip,pins
2791 <3 RK
2792 };
2793 spi4_rx: spi4-rx {
2794 rockchip,pins
2795 <3 RK
2796 };
2797 spi4_tx: spi4-tx {
2798 rockchip,pins
2799 <3 RK
2800 };
2801 };
2802
2803 spi5 {
2804 spi5_clk: spi5-clk {
2805 rockchip,pins
2806 <2 RK
2807 };
2808 spi5_cs0: spi5-cs0 {
2809 rockchip,pins
2810 <2 RK
2811 };
2812 spi5_rx: spi5-rx {
2813 rockchip,pins
2814 <2 RK
2815 };
2816 spi5_tx: spi5-tx {
2817 rockchip,pins
2818 <2 RK
2819 };
2820 };
2821
2822 testclk {
2823 test_clkout0: test-cl
2824 rockchip,pins
2825 <0 RK
2826 };
2827
2828 test_clkout1: test-cl
2829 rockchip,pins
2830 <2 RK
2831 };
2832
2833 test_clkout2: test-cl
2834 rockchip,pins
2835 <0 RK
2836 };
2837 };
2838
2839 tsadc {
2840 otp_pin: otp-pin {
2841 rockchip,pins
2842 };
2843
2844 otp_out: otp-out {
2845 rockchip,pins
2846 };
2847 };
2848
2849 uart0 {
2850 uart0_xfer: uart0-xfe
2851 rockchip,pins
2852 <2 RK
2853 <2 RK
2854 };
2855
2856 uart0_cts: uart0-cts
2857 rockchip,pins
2858 <2 RK
2859 };
2860
2861 uart0_rts: uart0-rts
2862 rockchip,pins
2863 <2 RK
2864 };
2865 };
2866
2867 uart1 {
2868 uart1_xfer: uart1-xfe
2869 rockchip,pins
2870 <3 RK
2871 <3 RK
2872 };
2873 };
2874
2875 uart2a {
2876 uart2a_xfer: uart2a-x
2877 rockchip,pins
2878 <4 RK
2879 <4 RK
2880 };
2881 };
2882
2883 uart2b {
2884 uart2b_xfer: uart2b-x
2885 rockchip,pins
2886 <4 RK
2887 <4 RK
2888 };
2889 };
2890
2891 uart2c {
2892 uart2c_xfer: uart2c-x
2893 rockchip,pins
2894 <4 RK
2895 <4 RK
2896 };
2897 };
2898
2899 uart3 {
2900 uart3_xfer: uart3-xfe
2901 rockchip,pins
2902 <3 RK
2903 <3 RK
2904 };
2905
2906 uart3_cts: uart3-cts
2907 rockchip,pins
2908 <3 RK
2909 };
2910
2911 uart3_rts: uart3-rts
2912 rockchip,pins
2913 <3 RK
2914 };
2915 };
2916
2917 uart4 {
2918 uart4_xfer: uart4-xfe
2919 rockchip,pins
2920 <1 RK
2921 <1 RK
2922 };
2923 };
2924
2925 uarthdcp {
2926 uarthdcp_xfer: uarthd
2927 rockchip,pins
2928 <4 RK
2929 <4 RK
2930 };
2931 };
2932
2933 pwm0 {
2934 pwm0_pin: pwm0-pin {
2935 rockchip,pins
2936 <4 RK
2937 };
2938
2939 pwm0_pin_pull_down: p
2940 rockchip,pins
2941 <4 RK
2942 };
2943
2944 vop0_pwm_pin: vop0-pw
2945 rockchip,pins
2946 <4 RK
2947 };
2948
2949 vop1_pwm_pin: vop1-pw
2950 rockchip,pins
2951 <4 RK
2952 };
2953 };
2954
2955 pwm1 {
2956 pwm1_pin: pwm1-pin {
2957 rockchip,pins
2958 <4 RK
2959 };
2960
2961 pwm1_pin_pull_down: p
2962 rockchip,pins
2963 <4 RK
2964 };
2965 };
2966
2967 pwm2 {
2968 pwm2_pin: pwm2-pin {
2969 rockchip,pins
2970 <1 RK
2971 };
2972
2973 pwm2_pin_pull_down: p
2974 rockchip,pins
2975 <1 RK
2976 };
2977 };
2978
2979 pwm3a {
2980 pwm3a_pin: pwm3a-pin
2981 rockchip,pins
2982 <0 RK
2983 };
2984 };
2985
2986 pwm3b {
2987 pwm3b_pin: pwm3b-pin
2988 rockchip,pins
2989 <1 RK
2990 };
2991 };
2992
2993 hdmi {
2994 hdmi_i2c_xfer: hdmi-i
2995 rockchip,pins
2996 <4 RK
2997 <4 RK
2998 };
2999
3000 hdmi_cec: hdmi-cec {
3001 rockchip,pins
3002 <4 RK
3003 };
3004 };
3005
3006 pcie {
3007 pcie_clkreqn_cpm: pci
3008 rockchip,pins
3009 <2 RK
3010 };
3011
3012 pcie_clkreqnb_cpm: pc
3013 rockchip,pins
3014 <4 RK
3015 };
3016 };
3017
3018 };
3019 };
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