1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
3 /dts-v1/;
4
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/soc/rockchip,vop2.h>
8 #include "rk3566.dtsi"
9
10 / {
11 model = "Pine64 SOQuartz system on mod
12 compatible = "pine64,soquartz", "rockc
13
14 aliases {
15 mmc0 = &sdmmc0;
16 mmc1 = &sdhci;
17 mmc2 = &sdmmc1;
18 };
19
20 chosen: chosen {
21 stdout-path = "serial2:1500000
22 };
23
24 gmac1_clkin: external-gmac1-clock {
25 compatible = "fixed-clock";
26 clock-frequency = <125000000>;
27 clock-output-names = "gmac1_cl
28 #clock-cells = <0>;
29 };
30
31 hdmi-con {
32 compatible = "hdmi-connector";
33 type = "a";
34
35 port {
36 hdmi_con_in: endpoint
37 remote-endpoin
38 };
39 };
40 };
41
42 leds {
43 compatible = "gpio-leds";
44
45 led_diy: led-diy {
46 label = "diy-led";
47 default-state = "on";
48 gpios = <&gpio0 RK_PC1
49 linux,default-trigger
50 pinctrl-names = "defau
51 pinctrl-0 = <&diy_led_
52 retain-state-suspended
53 status = "disabled";
54 };
55
56 led_work: led-work {
57 label = "work-led";
58 default-state = "off";
59 gpios = <&gpio0 RK_PC0
60 pinctrl-names = "defau
61 pinctrl-0 = <&work_led
62 retain-state-suspended
63 status = "disabled";
64 };
65 };
66
67 sdio_pwrseq: sdio-pwrseq {
68 status = "okay";
69 compatible = "mmc-pwrseq-simpl
70 clocks = <&rk809 1>;
71 clock-names = "ext_clock";
72 pinctrl-names = "default";
73 pinctrl-0 = <&wifi_enable_h>;
74 reset-gpios = <&gpio2 RK_PC2 G
75 };
76
77 vbus: vbus-regulator {
78 compatible = "regulator-fixed"
79 regulator-name = "vbus";
80 regulator-always-on;
81 regulator-boot-on;
82 regulator-min-microvolt = <500
83 regulator-max-microvolt = <500
84 };
85
86 /* sourced from vbus, vbus is provided
87 vcc5v0_sys: vcc5v0-sys-regulator {
88 compatible = "regulator-fixed"
89 regulator-name = "vcc5v0_sys";
90 regulator-always-on;
91 regulator-boot-on;
92 regulator-min-microvolt = <500
93 regulator-max-microvolt = <500
94 vin-supply = <&vbus>;
95 };
96
97 vcc3v3_sys: vcc3v3-sys-regulator {
98 compatible = "regulator-fixed"
99 regulator-name = "vcc3v3_sys";
100 regulator-always-on;
101 regulator-boot-on;
102 regulator-min-microvolt = <330
103 regulator-max-microvolt = <330
104 vin-supply = <&vcc5v0_sys>;
105 };
106 };
107
108 &cpu0 {
109 cpu-supply = <&vdd_cpu>;
110 };
111
112 &cpu1 {
113 cpu-supply = <&vdd_cpu>;
114 };
115
116 &cpu2 {
117 cpu-supply = <&vdd_cpu>;
118 };
119
120 &cpu3 {
121 cpu-supply = <&vdd_cpu>;
122 };
123
124 &gmac1 {
125 assigned-clocks = <&cru SCLK_GMAC1_RX_
126 assigned-clock-parents = <&cru SCLK_GM
127 clock_in_out = "input";
128 phy-supply = <&vcc_3v3>;
129 phy-mode = "rgmii";
130 pinctrl-names = "default";
131 pinctrl-0 = <&gmac1m0_miim
132 &gmac1m0_tx_bus2
133 &gmac1m0_rx_bus2
134 &gmac1m0_rgmii_clk
135 &gmac1m0_clkinout
136 &gmac1m0_rgmii_bus>;
137 snps,reset-gpio = <&gpio0 RK_PC3 GPIO_
138 snps,reset-active-low;
139 /* Reset time is 20ms, 100ms for rtl82
140 snps,reset-delays-us = <0 20000 100000
141 tx_delay = <0x30>;
142 rx_delay = <0x10>;
143 phy-handle = <&rgmii_phy1>;
144 status = "disabled";
145 };
146
147 &gpio0 {
148 nextrst-hog {
149 gpio-hog;
150 /*
151 * GPIO_ACTIVE_LOW + output-lo
152 * to high, because output-low
153 */
154 gpios = <RK_PA5 GPIO_ACTIVE_LO
155 line-name = "nEXTRST";
156 output-low;
157 };
158 };
159
160 &gpu {
161 mali-supply = <&vdd_gpu>;
162 status = "okay";
163 };
164
165 &hdmi {
166 avdd-0v9-supply = <&vdda0v9_image>;
167 avdd-1v8-supply = <&vcca1v8_image>;
168 status = "okay";
169 };
170
171 &hdmi_in {
172 hdmi_in_vp0: endpoint {
173 remote-endpoint = <&vp0_out_hd
174 };
175 };
176
177 &hdmi_out {
178 hdmi_out_con: endpoint {
179 remote-endpoint = <&hdmi_con_i
180 };
181 };
182
183 &hdmi_sound {
184 status = "okay";
185 };
186
187 &i2c0 {
188 status = "okay";
189
190 vdd_cpu: regulator@1c {
191 compatible = "tcs,tcs4525";
192 reg = <0x1c>;
193 fcs,suspend-voltage-selector =
194 regulator-name = "vdd_cpu";
195 regulator-min-microvolt = <800
196 regulator-max-microvolt = <115
197 regulator-ramp-delay = <2300>;
198 regulator-always-on;
199 regulator-boot-on;
200 vin-supply = <&vcc5v0_sys>;
201
202 regulator-state-mem {
203 regulator-off-in-suspe
204 };
205 };
206
207 rk809: pmic@20 {
208 compatible = "rockchip,rk809";
209 reg = <0x20>;
210 interrupt-parent = <&gpio0>;
211 interrupts = <RK_PA3 IRQ_TYPE_
212 #clock-cells = <1>;
213 clock-output-names = "rk808-cl
214 pinctrl-names = "default";
215 pinctrl-0 = <&pmic_int_l>;
216 rockchip,system-power-controll
217 wakeup-source;
218
219 vcc1-supply = <&vcc3v3_sys>;
220 vcc2-supply = <&vcc3v3_sys>;
221 vcc3-supply = <&vcc3v3_sys>;
222 vcc4-supply = <&vcc3v3_sys>;
223 vcc5-supply = <&vcc3v3_sys>;
224 vcc6-supply = <&vcc3v3_sys>;
225 vcc7-supply = <&vcc3v3_sys>;
226 vcc8-supply = <&vcc3v3_sys>;
227 vcc9-supply = <&vcc3v3_sys>;
228
229 regulators {
230 vdd_logic: DCDC_REG1 {
231 regulator-name
232 regulator-alwa
233 regulator-boot
234 regulator-min-
235 regulator-max-
236 regulator-ramp
237 regulator-init
238 regulator-stat
239 regula
240 regula
241 };
242 };
243
244 vdd_gpu: DCDC_REG2 {
245 regulator-name
246 regulator-alwa
247 regulator-boot
248 regulator-min-
249 regulator-max-
250 regulator-ramp
251 regulator-init
252 regula
253 regula
254 };
255 };
256
257 vcc_ddr: DCDC_REG3 {
258 regulator-alwa
259 regulator-boot
260 regulator-init
261 regulator-name
262 regulator-stat
263 regula
264 };
265 };
266
267 vdd_npu: DCDC_REG4 {
268 regulator-alwa
269 regulator-boot
270 regulator-min-
271 regulator-max-
272 regulator-init
273 regulator-name
274 regulator-stat
275 regula
276 };
277 };
278
279 vcc_1v8: DCDC_REG5 {
280 regulator-name
281 regulator-alwa
282 regulator-boot
283 regulator-min-
284 regulator-max-
285 regulator-stat
286 regula
287 regula
288 };
289 };
290
291 vdda0v9_image: LDO_REG
292 regulator-alwa
293 regulator-boot
294 regulator-min-
295 regulator-max-
296 regulator-name
297 regulator-stat
298 regula
299 regula
300 };
301 };
302
303 vdda_0v9: LDO_REG2 {
304 regulator-alwa
305 regulator-boot
306 regulator-min-
307 regulator-max-
308 regulator-name
309 regulator-stat
310 regula
311 };
312 };
313
314 vdda0v9_pmu: LDO_REG3
315 regulator-alwa
316 regulator-boot
317 regulator-min-
318 regulator-max-
319 regulator-name
320 regulator-stat
321 regula
322 regula
323 };
324 };
325
326 vccio_acodec: LDO_REG4
327 regulator-alwa
328 regulator-boot
329 regulator-min-
330 regulator-max-
331 regulator-name
332 regulator-stat
333 regula
334 };
335 };
336
337 vccio_sd: LDO_REG5 {
338 regulator-alwa
339 regulator-boot
340 regulator-min-
341 regulator-max-
342 regulator-name
343 regulator-stat
344 regula
345 };
346 };
347
348 vcc3v3_pmu: LDO_REG6 {
349 regulator-alwa
350 regulator-boot
351 regulator-min-
352 regulator-max-
353 regulator-name
354 regulator-stat
355 regula
356 regula
357 };
358 };
359
360 vcca_1v8: LDO_REG7 {
361 regulator-alwa
362 regulator-boot
363 regulator-min-
364 regulator-max-
365 regulator-name
366 regulator-stat
367 regula
368 };
369 };
370
371 vcca1v8_pmu: LDO_REG8
372 regulator-alwa
373 regulator-boot
374 regulator-min-
375 regulator-max-
376 regulator-name
377 regulator-stat
378 regula
379 };
380 };
381
382 vcca1v8_image: LDO_REG
383 regulator-alwa
384 regulator-boot
385 regulator-min-
386 regulator-max-
387 regulator-name
388 regulator-stat
389 regula
390 };
391 };
392
393 vcc_3v3: SWITCH_REG1 {
394 regulator-name
395 regulator-stat
396 regula
397 };
398 };
399
400 vcc3v3_sd: SWITCH_REG2
401 regulator-name
402 status = "disa
403 regulator-stat
404 regula
405 };
406 };
407
408 };
409 };
410 };
411
412 /*
413 * i2c1 is exposed on CM1 / Module1A
414 * pin 80 - i2c1_scl_m0, pullup to vcc3v3_pmu
415 * pin 82 - i2c1_sda_m0, pullup to vcc3v3_pmu
416 */
417 &i2c1 {
418 status = "disabled";
419 };
420
421 /*
422 * i2c2 is exposed on CM1 / Module1A
423 * pin 56 - i2c2_scl_m1, pullup to vcc_3v3, sh
424 * pin 58 - i2c2_sda_m1, pullup to vcc_3v3
425 */
426 &i2c2 {
427 pinctrl-names = "default";
428 pinctrl-0 = <&i2c2m1_xfer>;
429 status = "disabled";
430 };
431
432 /*
433 * i2c3 is exposed on CM1 / Module1A
434 * pin 35 - i2c3_scl_m0, pullup to vcc_3v3
435 * pin 36 - i2c3_sda_m0, pullup to vcc_3v3
436 */
437 &i2c3 {
438 status = "disabled";
439 };
440
441 /*
442 * i2c4 is exposed on CM2 / Module1B
443 * pin 45 - i2c4_scl_m1
444 * pin 47 - i2c4_sda_m1
445 */
446 &i2c4 {
447 pinctrl-names = "default";
448 pinctrl-0 = <&i2c4m1_xfer>;
449 status = "disabled";
450 };
451
452 &i2s0_8ch {
453 status = "okay";
454 };
455
456 /*
457 * i2s1_8ch is exposed on CM1 / Module1A
458 * pin 24 - i2s1_sdi1_m1
459 * pin 25 - i2s1_sdo0_m1
460 * pin 26 - i2s1_lrck_tx_m1
461 * pin 27 - i2s1_sdi0_m1
462 * pin 29 - i2s1_sdi3_m1
463 * pin 30 - i2s1_sdi2_m1
464 * pin 40 - i2s1_sdo1_m1, shared with spi3
465 * pin 41 - i2s1_sdo2_m1
466 * pin 49 - i2s1_sclk_tx_m1
467 * pin 50 - i2s1_mclk_m1
468 * pin 56 - i2s1_sdo3_m1, shared with i2c2
469 */
470 &i2s1_8ch {
471 pinctrl-names = "default";
472 pinctrl-0 = <&i2s1m1_sclktx &i2s1m1_sc
473 &i2s1m1_lrcktx &i2s1m1_lr
474 &i2s1m1_sdi0 &i2s1m1_sd
475 &i2s1m1_sdi2 &i2s1m1_sd
476 &i2s1m1_sdo0 &i2s1m1_sd
477 &i2s1m1_sdo2 &i2s1m1_sd
478 status = "disabled";
479 };
480
481 &mdio1 {
482 rgmii_phy1: ethernet-phy@0 {
483 compatible = "ethernet-phy-iee
484 reg = <0>;
485 status = "disabled";
486 };
487 };
488
489 &pcie2x1 {
490 pinctrl-names = "default";
491 pinctrl-0 = <&pcie_reset_h>;
492 reset-gpios = <&gpio1 RK_PB2 GPIO_ACTI
493 };
494
495 &pinctrl {
496 bt {
497 bt_enable_h: bt-enable-h {
498 rockchip,pins = <2 RK_
499 };
500
501 bt_host_wake_l: bt-host-wake-l
502 rockchip,pins = <2 RK_
503 };
504
505 bt_wake_l: bt-wake-l {
506 rockchip,pins = <2 RK_
507 };
508 };
509
510 leds {
511 work_led_enable_h: work-led-en
512 rockchip,pins = <0 RK_
513 };
514
515 diy_led_enable_h: diy-led-enab
516 rockchip,pins = <0 RK_
517 };
518 };
519
520 pcie {
521 pcie_clkreq_h: pcie-clkreq-h {
522 rockchip,pins = <1 RK_
523 };
524 pcie_reset_h: pcie-reset-h {
525 rockchip,pins = <1 RK_
526 };
527 };
528
529 pmic {
530 pmic_int_l: pmic-int-l {
531 rockchip,pins = <0 RK_
532 };
533 };
534
535 sdio-pwrseq {
536 wifi_enable_h: wifi-enable-h {
537 rockchip,pins = <2 RK_
538 };
539 };
540 };
541
542 &pmu_io_domains {
543 pmuio1-supply = <&vcc3v3_pmu>;
544 pmuio2-supply = <&vcc3v3_pmu>;
545 vccio1-supply = <&vcc_3v3>;
546 vccio2-supply = <&vcc_1v8>;
547 vccio3-supply = <&vccio_sd>;
548 vccio4-supply = <&vcc_1v8>;
549 vccio5-supply = <&vcc_3v3>;
550 vccio6-supply = <&vcc_3v3>;
551 vccio7-supply = <&vcc_3v3>;
552 status = "okay";
553 };
554
555 /*
556 * saradc is exposed on CM1 / Module1A
557 * pin 94 - saradc_vin3
558 * pin 96 - saradc_vin2
559 */
560 &saradc {
561 vref-supply = <&vcca_1v8>;
562 status = "disabled";
563 };
564
565 &sdhci {
566 bus-width = <8>;
567 mmc-hs200-1_8v;
568 non-removable;
569 vmmc-supply = <&vcc_3v3>;
570 vqmmc-supply = <&vcc_1v8>;
571 status = "okay";
572 };
573
574 &sdmmc0 {
575 broken-cd;
576 bus-width = <4>;
577 cap-sd-highspeed;
578 disable-wp;
579 pinctrl-names = "default";
580 pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk
581 vqmmc-supply = <&vccio_sd>;
582 status = "disabled";
583 };
584
585 &sdmmc1 {
586 bus-width = <4>;
587 cap-sd-highspeed;
588 cap-sdio-irq;
589 keep-power-in-suspend;
590 mmc-pwrseq = <&sdio_pwrseq>;
591 non-removable;
592 pinctrl-names = "default";
593 pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd
594 sd-uhs-sdr50;
595 vmmc-supply = <&vcc3v3_sys>;
596 vqmmc-supply = <&vcc_1v8>;
597 status = "okay";
598 };
599
600 /*
601 * spi3 is exposed on CM1 / Module1A
602 * pin 37 - spi3_cs1_m0
603 * pin 38 - spi3_clk_m0
604 * pin 39 - spi3_cs0_m0
605 * pin 40 - spi3_miso_m0, shared with i2s1_8ch
606 * pin 44 - spi3_mosi_m0
607 */
608 &spi3 {
609 status = "disabled";
610 };
611
612 &tsadc {
613 status = "okay";
614 };
615
616 &uart1 {
617 dma-names = "tx", "rx";
618 pinctrl-names = "default";
619 pinctrl-0 = <&uart1m0_xfer &uart1m0_ct
620 uart-has-rtscts;
621 status = "okay";
622
623 bluetooth {
624 compatible = "brcm,bcm43438-bt
625 clocks = <&rk809 1>;
626 clock-names = "lpo";
627 device-wakeup-gpios = <&gpio2
628 host-wakeup-gpios = <&gpio2 RK
629 shutdown-gpios = <&gpio2 RK_PB
630 pinctrl-names = "default";
631 pinctrl-0 = <&bt_host_wake_l &
632 vbat-supply = <&vcc3v3_sys>;
633 vddio-supply = <&vcca1v8_pmu>;
634 };
635 };
636
637 /*
638 * uart2 is exposed on CM1 / Module1A
639 * pin 51 - uart2_rx_m0
640 * pin 55 - uart2_tx_m0
641 */
642 &uart2 {
643 status = "disabled";
644 };
645
646 /*
647 * uart7 is exposed on CM1 / Module1A
648 * pin 46 - uart7_tx_m2
649 * pin 47 - uart7_rx_m2
650 */
651 &uart7 {
652 pinctrl-names = "default";
653 pinctrl-0 = <&uart7m2_xfer>;
654 status = "disabled";
655 };
656
657 /* dwc3_otg is the only usb port available */
658 &usb2phy0 {
659 status = "disabled";
660 };
661
662 &usb2phy0_otg {
663 status = "disabled";
664 };
665
666 &usb_host0_xhci {
667 status = "disabled";
668 };
669
670 &vop {
671 assigned-clocks = <&cru DCLK_VOP0>, <&
672 assigned-clock-parents = <&pmucru PLL_
673 status = "okay";
674 };
675
676 &vop_mmu {
677 status = "okay";
678 };
679
680 &vp0 {
681 vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_E
682 reg = <ROCKCHIP_VOP2_EP_HDMI0>
683 remote-endpoint = <&hdmi_in_vp
684 };
685 };
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