1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright (c) 2021 Rockchip Electronics Co.
4 *
5 */
6
7 /dts-v1/;
8
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/pinctrl/rockchip.h>
12 #include <dt-bindings/usb/pd.h>
13 #include "rk3588.dtsi"
14
15 / {
16 model = "Rockchip RK3588 EVB1 V10 Boar
17 compatible = "rockchip,rk3588-evb1-v10
18
19 aliases {
20 ethernet0 = &gmac0;
21 mmc0 = &sdhci;
22 };
23
24 chosen {
25 stdout-path = "serial2:1500000
26 };
27
28 adc-keys {
29 compatible = "adc-keys";
30 io-channels = <&saradc 1>;
31 io-channel-names = "buttons";
32 keyup-threshold-microvolt = <1
33 poll-interval = <100>;
34
35 button-vol-up {
36 label = "Volume Up";
37 linux,code = <KEY_VOLU
38 press-threshold-microv
39 };
40
41 button-vol-down {
42 label = "Volume Down";
43 linux,code = <KEY_VOLU
44 press-threshold-microv
45 };
46
47 button-menu {
48 label = "Menu";
49 linux,code = <KEY_MENU
50 press-threshold-microv
51 };
52
53 button-escape {
54 label = "Escape";
55 linux,code = <KEY_ESC>
56 press-threshold-microv
57 };
58 };
59
60 analog-sound {
61 compatible = "simple-audio-car
62 pinctrl-names = "default";
63 pinctrl-0 = <&hp_detect>;
64 simple-audio-card,name = "RK35
65 simple-audio-card,aux-devs = <
66 simple-audio-card,bitclock-mas
67 simple-audio-card,format = "i2
68 simple-audio-card,frame-master
69 simple-audio-card,hp-det-gpio
70 simple-audio-card,mclk-fs = <2
71 simple-audio-card,pin-switches
72 simple-audio-card,routing =
73 "Speaker Amplifier INL
74 "Speaker Amplifier INR
75 "Speaker", "Speaker Am
76 "Speaker", "Speaker Am
77 "Headphones Amplifier
78 "Headphones Amplifier
79 "Headphones", "Headpho
80 "Headphones", "Headpho
81 "LINPUT1", "Onboard Mi
82 "RINPUT1", "Onboard Mi
83 "LINPUT2", "Microphone
84 "RINPUT2", "Microphone
85 simple-audio-card,widgets =
86 "Microphone", "Microph
87 "Microphone", "Onboard
88 "Headphone", "Headphon
89 "Speaker", "Speaker";
90
91 simple-audio-card,cpu {
92 sound-dai = <&i2s0_8ch
93 };
94
95 masterdai: simple-audio-card,c
96 sound-dai = <&es8388>;
97 system-clock-frequency
98 };
99 };
100
101 amp_headphone: headphone-amplifier {
102 compatible = "simple-audio-amp
103 enable-gpios = <&gpio1 RK_PD2
104 pinctrl-names = "default";
105 pinctrl-0 = <&headphone_amplif
106 sound-name-prefix = "Headphone
107 };
108
109 amp_speaker: speaker-amplifier {
110 compatible = "simple-audio-amp
111 enable-gpios = <&gpio1 RK_PD3
112 pinctrl-names = "default";
113 pinctrl-0 = <&speaker_amplifie
114 sound-name-prefix = "Speaker A
115 };
116
117 backlight: backlight {
118 compatible = "pwm-backlight";
119 power-supply = <&vcc12v_dcin>;
120 pwms = <&pwm2 0 25000 0>;
121 };
122
123 pcie20_avdd0v85: pcie20-avdd0v85-regul
124 compatible = "regulator-fixed"
125 regulator-name = "pcie20_avdd0
126 regulator-always-on;
127 regulator-boot-on;
128 regulator-min-microvolt = <850
129 regulator-max-microvolt = <850
130 vin-supply = <&avdd_0v85_s0>;
131 };
132
133 pcie20_avdd1v8: pcie20-avdd1v8-regulat
134 compatible = "regulator-fixed"
135 regulator-name = "pcie20_avdd1
136 regulator-always-on;
137 regulator-boot-on;
138 regulator-min-microvolt = <180
139 regulator-max-microvolt = <180
140 vin-supply = <&avcc_1v8_s0>;
141 };
142
143 pcie30_avdd0v75: pcie30-avdd0v75-regul
144 compatible = "regulator-fixed"
145 regulator-name = "pcie30_avdd0
146 regulator-always-on;
147 regulator-boot-on;
148 regulator-min-microvolt = <750
149 regulator-max-microvolt = <750
150 vin-supply = <&avdd_0v75_s0>;
151 };
152
153 pcie30_avdd1v8: pcie30-avdd1v8-regulat
154 compatible = "regulator-fixed"
155 regulator-name = "pcie30_avdd1
156 regulator-always-on;
157 regulator-boot-on;
158 regulator-min-microvolt = <180
159 regulator-max-microvolt = <180
160 vin-supply = <&avcc_1v8_s0>;
161 };
162
163 vbus5v0_typec: vbus5v0-typec-regulator
164 compatible = "regulator-fixed"
165 enable-active-high;
166 gpio = <&gpio4 RK_PD0 GPIO_ACT
167 pinctrl-names = "default";
168 pinctrl-0 = <&typec5v_pwren>;
169 regulator-name = "vbus5v0_type
170 regulator-min-microvolt = <500
171 regulator-max-microvolt = <500
172 vin-supply = <&vcc5v0_usb>;
173 };
174
175 vcc12v_dcin: vcc12v-dcin-regulator {
176 compatible = "regulator-fixed"
177 regulator-name = "vcc12v_dcin"
178 regulator-always-on;
179 regulator-boot-on;
180 regulator-min-microvolt = <120
181 regulator-max-microvolt = <120
182 };
183
184 vcc3v3_pcie30: vcc3v3-pcie30-regulator
185 compatible = "regulator-fixed"
186 regulator-name = "vcc3v3_pcie3
187 regulator-min-microvolt = <330
188 regulator-max-microvolt = <330
189 enable-active-high;
190 gpios = <&gpio3 RK_PC3 GPIO_AC
191 startup-delay-us = <5000>;
192 vin-supply = <&vcc12v_dcin>;
193 pinctrl-names = "default";
194 pinctrl-0 = <&vcc3v3_pcie30_en
195 };
196
197 vcc5v0_host: vcc5v0-host-regulator {
198 compatible = "regulator-fixed"
199 regulator-name = "vcc5v0_host"
200 regulator-boot-on;
201 regulator-always-on;
202 regulator-min-microvolt = <500
203 regulator-max-microvolt = <500
204 enable-active-high;
205 gpio = <&gpio4 RK_PB0 GPIO_ACT
206 pinctrl-names = "default";
207 pinctrl-0 = <&vcc5v0_host_en>;
208 vin-supply = <&vcc5v0_usb>;
209 };
210
211 vcc5v0_sys: vcc5v0-sys-regulator {
212 compatible = "regulator-fixed"
213 regulator-name = "vcc5v0_sys";
214 regulator-always-on;
215 regulator-boot-on;
216 regulator-min-microvolt = <500
217 regulator-max-microvolt = <500
218 vin-supply = <&vcc12v_dcin>;
219 };
220
221 vcc5v0_usbdcin: vcc5v0-usbdcin-regulat
222 compatible = "regulator-fixed"
223 regulator-name = "vcc5v0_usbdc
224 regulator-always-on;
225 regulator-boot-on;
226 regulator-min-microvolt = <500
227 regulator-max-microvolt = <500
228 vin-supply = <&vcc12v_dcin>;
229 };
230
231 vcc5v0_usb: vcc5v0-usb-regulator {
232 compatible = "regulator-fixed"
233 regulator-name = "vcc5v0_usb";
234 regulator-always-on;
235 regulator-boot-on;
236 regulator-min-microvolt = <500
237 regulator-max-microvolt = <500
238 vin-supply = <&vcc5v0_usbdcin>
239 };
240 };
241
242 &combphy0_ps {
243 status = "okay";
244 };
245
246 &combphy2_psu {
247 status = "okay";
248 };
249
250 &cpu_b0 {
251 cpu-supply = <&vdd_cpu_big0_s0>;
252 };
253
254 &cpu_b1 {
255 cpu-supply = <&vdd_cpu_big0_s0>;
256 };
257
258 &cpu_b2 {
259 cpu-supply = <&vdd_cpu_big1_s0>;
260 };
261
262 &cpu_b3 {
263 cpu-supply = <&vdd_cpu_big1_s0>;
264 };
265
266 &cpu_l0 {
267 cpu-supply = <&vdd_cpu_lit_s0>;
268 };
269
270 &cpu_l1 {
271 cpu-supply = <&vdd_cpu_lit_s0>;
272 };
273
274 &cpu_l2 {
275 cpu-supply = <&vdd_cpu_lit_s0>;
276 };
277
278 &cpu_l3 {
279 cpu-supply = <&vdd_cpu_lit_s0>;
280 };
281
282 &gmac0 {
283 clock_in_out = "output";
284 phy-handle = <&rgmii_phy>;
285 phy-mode = "rgmii-rxid";
286 pinctrl-0 = <&gmac0_miim
287 &gmac0_tx_bus2
288 &gmac0_rx_bus2
289 &gmac0_rgmii_clk
290 &gmac0_rgmii_bus>;
291 pinctrl-names = "default";
292 rx_delay = <0x00>;
293 tx_delay = <0x43>;
294 status = "okay";
295 };
296
297 &gpu {
298 mali-supply = <&vdd_gpu_s0>;
299 sram-supply = <&vdd_gpu_mem_s0>;
300 status = "okay";
301 };
302
303 &i2c2 {
304 status = "okay";
305
306 usbc0: usb-typec@22 {
307 compatible = "fcs,fusb302";
308 reg = <0x22>;
309 interrupt-parent = <&gpio3>;
310 interrupts = <RK_PB4 IRQ_TYPE_
311 pinctrl-names = "default";
312 pinctrl-0 = <&usbc0_int>;
313 vbus-supply = <&vbus5v0_typec>
314 status = "okay";
315
316 usb_con: connector {
317 compatible = "usb-c-co
318 label = "USB-C";
319 data-role = "dual";
320 op-sink-microwatt = <1
321 power-role = "dual";
322 sink-pdos =
323 <PDO_FIXED(500
324 source-pdos =
325 <PDO_FIXED(500
326 try-power-role = "sour
327
328 ports {
329 #address-cells
330 #size-cells =
331
332 port@0 {
333 reg =
334
335 usbc0_
336
337 };
338 };
339
340 port@1 {
341 reg =
342
343 usbc0_
344
345 };
346 };
347
348 port@2 {
349 reg =
350
351 dp_alt
352
353 };
354 };
355 };
356 };
357 };
358
359 hym8563: rtc@51 {
360 compatible = "haoyu,hym8563";
361 reg = <0x51>;
362 #clock-cells = <0>;
363 clock-output-names = "hym8563"
364 pinctrl-names = "default";
365 pinctrl-0 = <&hym8563_int>;
366 interrupt-parent = <&gpio0>;
367 interrupts = <RK_PD4 IRQ_TYPE_
368 wakeup-source;
369 };
370 };
371
372 &i2c7 {
373 status = "okay";
374
375 es8388: audio-codec@11 {
376 compatible = "everest,es8388";
377 reg = <0x11>;
378 clocks = <&cru I2S0_8CH_MCLKOU
379 assigned-clocks = <&cru I2S0_8
380 assigned-clock-rates = <122880
381 AVDD-supply = <&avcc_1v8_codec
382 DVDD-supply = <&avcc_1v8_codec
383 HPVDD-supply = <&vcc_3v3_s0>;
384 PVDD-supply = <&vcc_3v3_s0>;
385 #sound-dai-cells = <0>;
386 };
387 };
388
389 &i2s0_8ch {
390 pinctrl-0 = <&i2s0_lrck
391 &i2s0_mclk
392 &i2s0_sclk
393 &i2s0_sdi0
394 &i2s0_sdo0>;
395 status = "okay";
396 };
397
398 &mdio0 {
399 rgmii_phy: ethernet-phy@1 {
400 /* RTL8211F */
401 compatible = "ethernet-phy-id0
402 reg = <0x1>;
403 pinctrl-names = "default";
404 pinctrl-0 = <&rtl8211f_rst>;
405 reset-assert-us = <20000>;
406 reset-deassert-us = <100000>;
407 reset-gpios = <&gpio4 RK_PB3 G
408 };
409 };
410
411 &pcie2x1l1 {
412 reset-gpios = <&gpio4 RK_PA2 GPIO_ACTI
413 pinctrl-names = "default";
414 pinctrl-0 = <&pcie2_1_rst>, <&rtl8111_
415 status = "okay";
416 };
417
418 &pcie30phy {
419 status = "okay";
420 };
421
422 &pcie3x4 {
423 pinctrl-names = "default";
424 pinctrl-0 = <&pcie3_reset>;
425 reset-gpios = <&gpio4 RK_PB6 GPIO_ACTI
426 vpcie3v3-supply = <&vcc3v3_pcie30>;
427 status = "okay";
428 };
429
430 &pinctrl {
431 audio {
432 hp_detect: headphone-detect {
433 rockchip,pins = <1 RK_
434 };
435
436 headphone_amplifier_en: headph
437 rockchip,pins = <1 RK_
438 };
439
440 speaker_amplifier_en: speaker-
441 rockchip,pins = <1 RK_
442 };
443 };
444
445 rtl8111 {
446 rtl8111_isolate: rtl8111-isola
447 rockchip,pins = <1 RK_
448 };
449 };
450
451 rtl8211f {
452 rtl8211f_rst: rtl8211f-rst {
453 rockchip,pins = <4 RK_
454 };
455
456 };
457
458 hym8563 {
459 hym8563_int: hym8563-int {
460 rockchip,pins = <0 RK_
461 };
462 };
463
464 pcie2 {
465 pcie2_1_rst: pcie2-1-rst {
466 rockchip,pins = <4 RK_
467 };
468 };
469
470 pcie3 {
471 pcie3_reset: pcie3-reset {
472 rockchip,pins = <4 RK_
473 };
474
475 vcc3v3_pcie30_en: vcc3v3-pcie3
476 rockchip,pins = <3 RK_
477 };
478 };
479
480 usb {
481 vcc5v0_host_en: vcc5v0-host-en
482 rockchip,pins = <4 RK_
483 };
484 };
485
486 usb-typec {
487 typec5v_pwren: typec5v-pwren {
488 rockchip,pins = <4 RK_
489 };
490
491 usbc0_int: usbc0-int {
492 rockchip,pins = <3 RK_
493 };
494 };
495 };
496
497 &pwm2 {
498 status = "okay";
499 };
500
501 &saradc {
502 vref-supply = <&vcc_1v8_s0>;
503 status = "okay";
504 };
505
506 &sdhci {
507 bus-width = <8>;
508 no-sdio;
509 no-sd;
510 non-removable;
511 mmc-hs400-1_8v;
512 mmc-hs400-enhanced-strobe;
513 status = "okay";
514 };
515
516 &spi2 {
517 status = "okay";
518 assigned-clocks = <&cru CLK_SPI2>;
519 assigned-clock-rates = <200000000>;
520 num-cs = <2>;
521
522 pmic@0 {
523 compatible = "rockchip,rk806";
524 reg = <0x0>;
525 #gpio-cells = <2>;
526 gpio-controller;
527 interrupt-parent = <&gpio0>;
528 interrupts = <7 IRQ_TYPE_LEVEL
529 pinctrl-0 = <&pmic_pins>, <&rk
530 <&rk806_dvs2_null>
531 pinctrl-names = "default";
532 spi-max-frequency = <1000000>;
533 system-power-controller;
534
535 vcc1-supply = <&vcc5v0_sys>;
536 vcc2-supply = <&vcc5v0_sys>;
537 vcc3-supply = <&vcc5v0_sys>;
538 vcc4-supply = <&vcc5v0_sys>;
539 vcc5-supply = <&vcc5v0_sys>;
540 vcc6-supply = <&vcc5v0_sys>;
541 vcc7-supply = <&vcc5v0_sys>;
542 vcc8-supply = <&vcc5v0_sys>;
543 vcc9-supply = <&vcc5v0_sys>;
544 vcc10-supply = <&vcc5v0_sys>;
545 vcc11-supply = <&vcc_2v0_pldo_
546 vcc12-supply = <&vcc5v0_sys>;
547 vcc13-supply = <&vcc5v0_sys>;
548 vcc14-supply = <&vcc_1v1_nldo_
549 vcca-supply = <&vcc5v0_sys>;
550
551 rk806_dvs1_null: dvs1-null-pin
552 pins = "gpio_pwrctrl1"
553 function = "pin_fun0";
554 };
555
556 rk806_dvs2_null: dvs2-null-pin
557 pins = "gpio_pwrctrl2"
558 function = "pin_fun0";
559 };
560
561 rk806_dvs3_null: dvs3-null-pin
562 pins = "gpio_pwrctrl3"
563 function = "pin_fun0";
564 };
565
566
567 regulators {
568 vdd_gpu_s0: dcdc-reg1
569 /* regulator c
570 regulator-alwa
571 regulator-boot
572 regulator-min-
573 regulator-max-
574 regulator-ramp
575 regulator-name
576 regulator-enab
577 regulator-coup
578 regulator-coup
579 regulator-stat
580 regula
581 };
582 };
583
584 vdd_npu_s0: dcdc-reg2
585 regulator-alwa
586 regulator-boot
587 regulator-min-
588 regulator-max-
589 regulator-ramp
590 regulator-name
591 regulator-stat
592 regula
593 };
594 };
595
596 vdd_log_s0: dcdc-reg3
597 regulator-alwa
598 regulator-boot
599 regulator-min-
600 regulator-max-
601 regulator-ramp
602 regulator-name
603 regulator-stat
604 regula
605 regula
606 };
607 };
608
609 vdd_vdenc_s0: dcdc-reg
610 regulator-alwa
611 regulator-boot
612 regulator-min-
613 regulator-max-
614 regulator-ramp
615 regulator-name
616 regulator-stat
617 regula
618 };
619
620 };
621
622 vdd_gpu_mem_s0: dcdc-r
623 /* regulator c
624 regulator-alwa
625 regulator-boot
626 regulator-min-
627 regulator-max-
628 regulator-ramp
629 regulator-enab
630 regulator-name
631 regulator-coup
632 regulator-coup
633 regulator-stat
634 regula
635 };
636
637 };
638
639 vdd_npu_mem_s0: dcdc-r
640 regulator-alwa
641 regulator-boot
642 regulator-min-
643 regulator-max-
644 regulator-ramp
645 regulator-name
646 regulator-stat
647 regula
648 };
649
650 };
651
652 vcc_2v0_pldo_s3: dcdc-
653 regulator-alwa
654 regulator-boot
655 regulator-min-
656 regulator-max-
657 regulator-ramp
658 regulator-name
659 regulator-stat
660 regula
661 regula
662 };
663 };
664
665 vdd_vdenc_mem_s0: dcdc
666 regulator-alwa
667 regulator-boot
668 regulator-min-
669 regulator-max-
670 regulator-ramp
671 regulator-name
672 regulator-stat
673 regula
674 };
675 };
676
677 vdd2_ddr_s3: dcdc-reg9
678 regulator-alwa
679 regulator-boot
680 regulator-name
681 regulator-stat
682 regula
683 };
684 };
685
686 vcc_1v1_nldo_s3: dcdc-
687 regulator-alwa
688 regulator-boot
689 regulator-min-
690 regulator-max-
691 regulator-ramp
692 regulator-name
693 regulator-stat
694 regula
695 regula
696 };
697 };
698
699 avcc_1v8_s0: pldo-reg1
700 regulator-alwa
701 regulator-boot
702 regulator-min-
703 regulator-max-
704 regulator-ramp
705 regulator-name
706 regulator-stat
707 regula
708 };
709 };
710
711 vdd1_1v8_ddr_s3: pldo-
712 regulator-alwa
713 regulator-boot
714 regulator-min-
715 regulator-max-
716 regulator-ramp
717 regulator-name
718 regulator-stat
719 regula
720 regula
721 };
722 };
723
724 avcc_1v8_codec_s0: pld
725 regulator-alwa
726 regulator-boot
727 regulator-min-
728 regulator-max-
729 regulator-ramp
730 regulator-name
731 regulator-stat
732 regula
733 };
734 };
735
736 vcc_3v3_s3: pldo-reg4
737 regulator-alwa
738 regulator-boot
739 regulator-min-
740 regulator-max-
741 regulator-ramp
742 regulator-name
743 regulator-stat
744 regula
745 regula
746 };
747 };
748
749 vccio_sd_s0: pldo-reg5
750 regulator-alwa
751 regulator-boot
752 regulator-min-
753 regulator-max-
754 regulator-ramp
755 regulator-name
756 regulator-stat
757 regula
758 };
759 };
760
761 vccio_1v8_s3: pldo-reg
762 regulator-alwa
763 regulator-boot
764 regulator-min-
765 regulator-max-
766 regulator-ramp
767 regulator-name
768 regulator-stat
769 regula
770 regula
771 };
772 };
773
774 vdd_0v75_s3: nldo-reg1
775 regulator-alwa
776 regulator-boot
777 regulator-min-
778 regulator-max-
779 regulator-ramp
780 regulator-name
781 regulator-stat
782 regula
783 regula
784 };
785 };
786
787 vdd2l_0v9_ddr_s3: nldo
788 regulator-alwa
789 regulator-boot
790 regulator-min-
791 regulator-max-
792 regulator-name
793 regulator-stat
794 regula
795 regula
796 };
797 };
798
799 vdd_0v75_hdmi_edp_s0:
800 regulator-alwa
801 regulator-boot
802 regulator-min-
803 regulator-max-
804 regulator-name
805 regulator-stat
806 regula
807 };
808 };
809
810 avdd_0v75_s0: nldo-reg
811 regulator-alwa
812 regulator-boot
813 regulator-min-
814 regulator-max-
815 regulator-name
816 regulator-stat
817 regula
818 };
819 };
820
821 vdd_0v85_s0: nldo-reg5
822 regulator-alwa
823 regulator-boot
824 regulator-min-
825 regulator-max-
826 regulator-name
827 regulator-stat
828 regula
829 };
830 };
831 };
832 };
833
834 pmic@1 {
835 compatible = "rockchip,rk806";
836 reg = <0x01>;
837 #gpio-cells = <2>;
838 gpio-controller;
839 interrupt-parent = <&gpio0>;
840 interrupts = <7 IRQ_TYPE_LEVEL
841 pinctrl-0 = <&rk806_slave_dvs1
842 <&rk806_slave_dvs3
843 pinctrl-names = "default";
844 spi-max-frequency = <1000000>;
845
846 vcc1-supply = <&vcc5v0_sys>;
847 vcc2-supply = <&vcc5v0_sys>;
848 vcc3-supply = <&vcc5v0_sys>;
849 vcc4-supply = <&vcc5v0_sys>;
850 vcc5-supply = <&vcc5v0_sys>;
851 vcc6-supply = <&vcc5v0_sys>;
852 vcc7-supply = <&vcc5v0_sys>;
853 vcc8-supply = <&vcc5v0_sys>;
854 vcc9-supply = <&vcc5v0_sys>;
855 vcc10-supply = <&vcc5v0_sys>;
856 vcc11-supply = <&vcc_2v0_pldo_
857 vcc12-supply = <&vcc5v0_sys>;
858 vcc13-supply = <&vcc_1v1_nldo_
859 vcc14-supply = <&vcc_2v0_pldo_
860 vcca-supply = <&vcc5v0_sys>;
861
862 rk806_slave_dvs1_null: dvs1-nu
863 pins = "gpio_pwrctrl1"
864 function = "pin_fun0";
865 };
866
867 rk806_slave_dvs2_null: dvs2-nu
868 pins = "gpio_pwrctrl2"
869 function = "pin_fun0";
870 };
871
872 rk806_slave_dvs3_null: dvs3-nu
873 pins = "gpio_pwrctrl3"
874 function = "pin_fun0";
875 };
876
877 regulators {
878 vdd_cpu_big1_s0: dcdc-
879 regulator-alwa
880 regulator-boot
881 regulator-coup
882 regulator-coup
883 regulator-min-
884 regulator-max-
885 regulator-ramp
886 regulator-name
887 regulator-stat
888 regula
889 };
890 };
891
892 vdd_cpu_big0_s0: dcdc-
893 regulator-alwa
894 regulator-boot
895 regulator-coup
896 regulator-coup
897 regulator-min-
898 regulator-max-
899 regulator-ramp
900 regulator-name
901 regulator-stat
902 regula
903 };
904 };
905
906 vdd_cpu_lit_s0: dcdc-r
907 regulator-alwa
908 regulator-boot
909 regulator-coup
910 regulator-coup
911 regulator-min-
912 regulator-max-
913 regulator-ramp
914 regulator-name
915 regulator-stat
916 regula
917 };
918 };
919
920 vcc_3v3_s0: dcdc-reg4
921 regulator-alwa
922 regulator-boot
923 regulator-min-
924 regulator-max-
925 regulator-ramp
926 regulator-name
927 regulator-stat
928 regula
929 };
930 };
931
932 vdd_cpu_big1_mem_s0: d
933 regulator-alwa
934 regulator-boot
935 regulator-coup
936 regulator-coup
937 regulator-min-
938 regulator-max-
939 regulator-ramp
940 regulator-name
941 regulator-stat
942 regula
943 };
944 };
945
946
947 vdd_cpu_big0_mem_s0: d
948 regulator-alwa
949 regulator-boot
950 regulator-coup
951 regulator-coup
952 regulator-min-
953 regulator-max-
954 regulator-ramp
955 regulator-name
956 regulator-stat
957 regula
958 };
959 };
960
961 vcc_1v8_s0: dcdc-reg7
962 regulator-alwa
963 regulator-boot
964 regulator-min-
965 regulator-max-
966 regulator-ramp
967 regulator-name
968 regulator-stat
969 regula
970 };
971 };
972
973 vdd_cpu_lit_mem_s0: dc
974 regulator-alwa
975 regulator-boot
976 regulator-coup
977 regulator-coup
978 regulator-min-
979 regulator-max-
980 regulator-ramp
981 regulator-name
982 regulator-stat
983 regula
984 };
985 };
986
987 vddq_ddr_s0: dcdc-reg9
988 regulator-alwa
989 regulator-boot
990 regulator-name
991 regulator-stat
992 regula
993 };
994 };
995
996 vdd_ddr_s0: dcdc-reg10
997 regulator-alwa
998 regulator-boot
999 regulator-min-
1000 regulator-max
1001 regulator-ram
1002 regulator-nam
1003 regulator-sta
1004 regul
1005 };
1006 };
1007
1008 vcc_1v8_cam_s0: pldo-
1009 regulator-alw
1010 regulator-boo
1011 regulator-min
1012 regulator-max
1013 regulator-ram
1014 regulator-nam
1015 regulator-sta
1016 regul
1017 };
1018 };
1019
1020 avdd1v8_ddr_pll_s0: p
1021 regulator-alw
1022 regulator-boo
1023 regulator-min
1024 regulator-max
1025 regulator-ram
1026 regulator-nam
1027 regulator-sta
1028 regul
1029 };
1030 };
1031
1032 vdd_1v8_pll_s0: pldo-
1033 regulator-alw
1034 regulator-boo
1035 regulator-min
1036 regulator-max
1037 regulator-ram
1038 regulator-nam
1039 regulator-sta
1040 regul
1041 };
1042 };
1043
1044 vcc_3v3_sd_s0: pldo-r
1045 regulator-alw
1046 regulator-boo
1047 regulator-min
1048 regulator-max
1049 regulator-ram
1050 regulator-nam
1051 regulator-sta
1052 regul
1053 };
1054 };
1055
1056 vcc_2v8_cam_s0: pldo-
1057 regulator-alw
1058 regulator-boo
1059 regulator-min
1060 regulator-max
1061 regulator-ram
1062 regulator-nam
1063 regulator-sta
1064 regul
1065 };
1066 };
1067
1068 pldo6_s3: pldo-reg6 {
1069 regulator-alw
1070 regulator-boo
1071 regulator-min
1072 regulator-max
1073 regulator-nam
1074 regulator-sta
1075 regul
1076 regul
1077 };
1078 };
1079
1080 vdd_0v75_pll_s0: nldo
1081 regulator-alw
1082 regulator-boo
1083 regulator-min
1084 regulator-max
1085 regulator-ram
1086 regulator-nam
1087 regulator-sta
1088 regul
1089 };
1090 };
1091
1092 vdd_ddr_pll_s0: nldo-
1093 regulator-alw
1094 regulator-boo
1095 regulator-min
1096 regulator-max
1097 regulator-nam
1098 regulator-sta
1099 regul
1100 };
1101 };
1102
1103 avdd_0v85_s0: nldo-re
1104 regulator-alw
1105 regulator-boo
1106 regulator-min
1107 regulator-max
1108 regulator-ram
1109 regulator-nam
1110 regulator-sta
1111 regul
1112 };
1113 };
1114
1115 avdd_1v2_cam_s0: nldo
1116 regulator-alw
1117 regulator-boo
1118 regulator-min
1119 regulator-max
1120 regulator-ram
1121 regulator-nam
1122 regulator-sta
1123 regul
1124 };
1125 };
1126
1127 avdd_1v2_s0: nldo-reg
1128 regulator-alw
1129 regulator-boo
1130 regulator-min
1131 regulator-max
1132 regulator-ram
1133 regulator-nam
1134 regulator-sta
1135 regul
1136 };
1137 };
1138 };
1139 };
1140 };
1141
1142 &sata0 {
1143 status = "okay";
1144 };
1145
1146 &tsadc {
1147 status = "okay";
1148 };
1149
1150 &u2phy0 {
1151 status = "okay";
1152 };
1153
1154 &u2phy0_otg {
1155 status = "okay";
1156 };
1157
1158 &u2phy1 {
1159 status = "okay";
1160 };
1161
1162 &u2phy1_otg {
1163 status = "okay";
1164 };
1165
1166 &u2phy2 {
1167 status = "okay";
1168 };
1169
1170 &u2phy2_host {
1171 phy-supply = <&vcc5v0_host>;
1172 status = "okay";
1173 };
1174
1175 &u2phy3 {
1176 status = "okay";
1177 };
1178
1179 &u2phy3_host {
1180 phy-supply = <&vcc5v0_host>;
1181 status = "okay";
1182 };
1183
1184 &uart2 {
1185 pinctrl-0 = <&uart2m0_xfer>;
1186 status = "okay";
1187 };
1188
1189 &usb_host0_ehci {
1190 status = "okay";
1191 };
1192
1193 &usb_host0_ohci {
1194 status = "okay";
1195 };
1196
1197 &usb_host1_ehci {
1198 status = "okay";
1199 };
1200
1201 &usb_host1_ohci {
1202 status = "okay";
1203 };
1204
1205 &usbdp_phy0 {
1206 mode-switch;
1207 orientation-switch;
1208 sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_A
1209 sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_A
1210 status = "okay";
1211
1212 port {
1213 #address-cells = <1>;
1214 #size-cells = <0>;
1215
1216 usbdp_phy0_orientation_switch
1217 reg = <0>;
1218 remote-endpoint = <&u
1219 };
1220
1221 usbdp_phy0_dp_altmode_mux: en
1222 reg = <1>;
1223 remote-endpoint = <&d
1224 };
1225 };
1226 };
1227
1228 &usbdp_phy1 {
1229 /*
1230 * USBDP PHY1 is wired to a female US
1231 * the differential pairs 2+3 and the
1232 * which converts the DP signal into
1233 * board via a female VGA connector.
1234 */
1235 rockchip,dp-lane-mux = <2 3>;
1236 status = "okay";
1237 };
1238
1239 &usb_host0_xhci {
1240 dr_mode = "otg";
1241 usb-role-switch;
1242 status = "okay";
1243
1244 port {
1245 #address-cells = <1>;
1246 #size-cells = <0>;
1247
1248 dwc3_0_role_switch: endpoint@
1249 reg = <0>;
1250 remote-endpoint = <&u
1251 };
1252 };
1253 };
1254
1255 &usb_host1_xhci {
1256 dr_mode = "host";
1257 status = "okay";
1258 };
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