1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
2 //
3 // Device Tree Source for UniPhier LD11 SoC
4 //
5 // Copyright (C) 2016 Socionext Inc.
6 // Author: Masahiro Yamada <yamada.masahiro@s
7
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/gpio/uniphier-gpio.h>
10 #include <dt-bindings/interrupt-controller/arm
11
12 / {
13 compatible = "socionext,uniphier-ld11"
14 #address-cells = <2>;
15 #size-cells = <2>;
16 interrupt-parent = <&gic>;
17
18 cpus {
19 #address-cells = <2>;
20 #size-cells = <0>;
21
22 cpu-map {
23 cluster0 {
24 core0 {
25 cpu =
26 };
27 core1 {
28 cpu =
29 };
30 };
31 };
32
33 cpu0: cpu@0 {
34 device_type = "cpu";
35 compatible = "arm,cort
36 reg = <0 0x000>;
37 clocks = <&sys_clk 33>
38 enable-method = "psci"
39 next-level-cache = <&l
40 operating-points-v2 =
41 };
42
43 cpu1: cpu@1 {
44 device_type = "cpu";
45 compatible = "arm,cort
46 reg = <0 0x001>;
47 clocks = <&sys_clk 33>
48 enable-method = "psci"
49 next-level-cache = <&l
50 operating-points-v2 =
51 };
52
53 l2: l2-cache {
54 compatible = "cache";
55 cache-level = <2>;
56 cache-unified;
57 };
58 };
59
60 cluster0_opp: opp-table {
61 compatible = "operating-points
62 opp-shared;
63
64 opp-245000000 {
65 opp-hz = /bits/ 64 <24
66 clock-latency-ns = <30
67 };
68 opp-250000000 {
69 opp-hz = /bits/ 64 <25
70 clock-latency-ns = <30
71 };
72 opp-490000000 {
73 opp-hz = /bits/ 64 <49
74 clock-latency-ns = <30
75 };
76 opp-500000000 {
77 opp-hz = /bits/ 64 <50
78 clock-latency-ns = <30
79 };
80 opp-653334000 {
81 opp-hz = /bits/ 64 <65
82 clock-latency-ns = <30
83 };
84 opp-666667000 {
85 opp-hz = /bits/ 64 <66
86 clock-latency-ns = <30
87 };
88 opp-980000000 {
89 opp-hz = /bits/ 64 <98
90 clock-latency-ns = <30
91 };
92 };
93
94 psci {
95 compatible = "arm,psci-1.0";
96 method = "smc";
97 };
98
99 clocks {
100 refclk: ref {
101 compatible = "fixed-cl
102 #clock-cells = <0>;
103 clock-frequency = <250
104 };
105 };
106
107 emmc_pwrseq: emmc-pwrseq {
108 compatible = "mmc-pwrseq-emmc"
109 reset-gpios = <&gpio UNIPHIER_
110 };
111
112 timer {
113 compatible = "arm,armv8-timer"
114 interrupts = <GIC_PPI 13 IRQ_T
115 <GIC_PPI 14 IRQ_T
116 <GIC_PPI 11 IRQ_T
117 <GIC_PPI 10 IRQ_T
118 };
119
120 reserved-memory {
121 #address-cells = <2>;
122 #size-cells = <2>;
123 ranges;
124
125 secure-memory@81000000 {
126 reg = <0x0 0x81000000
127 no-map;
128 };
129 };
130
131 soc@0 {
132 compatible = "simple-bus";
133 #address-cells = <1>;
134 #size-cells = <1>;
135 ranges = <0 0 0 0xffffffff>;
136
137 spi0: spi@54006000 {
138 compatible = "socionex
139 status = "disabled";
140 reg = <0x54006000 0x10
141 #address-cells = <1>;
142 #size-cells = <0>;
143 interrupts = <GIC_SPI
144 pinctrl-names = "defau
145 pinctrl-0 = <&pinctrl_
146 clocks = <&peri_clk 11
147 resets = <&peri_rst 11
148 };
149
150 spi1: spi@54006100 {
151 compatible = "socionex
152 status = "disabled";
153 reg = <0x54006100 0x10
154 #address-cells = <1>;
155 #size-cells = <0>;
156 interrupts = <GIC_SPI
157 pinctrl-names = "defau
158 pinctrl-0 = <&pinctrl_
159 clocks = <&peri_clk 12
160 resets = <&peri_rst 12
161 };
162
163 serial0: serial@54006800 {
164 compatible = "socionex
165 status = "disabled";
166 reg = <0x54006800 0x40
167 interrupts = <GIC_SPI
168 pinctrl-names = "defau
169 pinctrl-0 = <&pinctrl_
170 clocks = <&peri_clk 0>
171 resets = <&peri_rst 0>
172 };
173
174 serial1: serial@54006900 {
175 compatible = "socionex
176 status = "disabled";
177 reg = <0x54006900 0x40
178 interrupts = <GIC_SPI
179 pinctrl-names = "defau
180 pinctrl-0 = <&pinctrl_
181 clocks = <&peri_clk 1>
182 resets = <&peri_rst 1>
183 };
184
185 serial2: serial@54006a00 {
186 compatible = "socionex
187 status = "disabled";
188 reg = <0x54006a00 0x40
189 interrupts = <GIC_SPI
190 pinctrl-names = "defau
191 pinctrl-0 = <&pinctrl_
192 clocks = <&peri_clk 2>
193 resets = <&peri_rst 2>
194 };
195
196 serial3: serial@54006b00 {
197 compatible = "socionex
198 status = "disabled";
199 reg = <0x54006b00 0x40
200 interrupts = <GIC_SPI
201 pinctrl-names = "defau
202 pinctrl-0 = <&pinctrl_
203 clocks = <&peri_clk 3>
204 resets = <&peri_rst 3>
205 };
206
207 gpio: gpio@55000000 {
208 compatible = "socionex
209 reg = <0x55000000 0x20
210 interrupt-parent = <&a
211 interrupt-controller;
212 #interrupt-cells = <2>
213 gpio-controller;
214 #gpio-cells = <2>;
215 gpio-ranges = <&pinctr
216 <&pinctr
217 <&pinctr
218 <&pinctr
219 <&pinctr
220 <&pinctr
221 gpio-ranges-group-name
222
223
224
225
226
227 ngpios = <200>;
228 socionext,interrupt-ra
229
230 };
231
232 audio@56000000 {
233 compatible = "socionex
234 reg = <0x56000000 0x80
235 interrupts = <GIC_SPI
236 pinctrl-names = "defau
237 pinctrl-0 = <&pinctrl_
238 <&pinctrl_
239 clock-names = "aio";
240 clocks = <&sys_clk 40>
241 reset-names = "aio";
242 resets = <&sys_rst 40>
243 #sound-dai-cells = <1>
244 socionext,syscon = <&s
245
246 i2s_port0: port@0 {
247 i2s_hdmi: endp
248 };
249 };
250
251 i2s_port1: port@1 {
252 i2s_pcmin2: en
253 };
254 };
255
256 i2s_port2: port@2 {
257 i2s_line: endp
258 dai-fo
259 remote
260 };
261 };
262
263 i2s_port3: port@3 {
264 i2s_hpcmout1:
265 };
266 };
267
268 i2s_port4: port@4 {
269 i2s_hp: endpoi
270 dai-fo
271 remote
272 };
273 };
274
275 spdif_port0: port@5 {
276 spdif_hiecout1
277 };
278 };
279
280 src_port0: port@6 {
281 i2s_epcmout2:
282 };
283 };
284
285 src_port1: port@7 {
286 i2s_epcmout3:
287 };
288 };
289
290 comp_spdif_port0: port
291 comp_spdif_hie
292 };
293 };
294 };
295
296 codec@57900000 {
297 compatible = "socionex
298 reg = <0x57900000 0x10
299 clock-names = "evea",
300 clocks = <&sys_clk 41>
301 reset-names = "evea",
302 resets = <&sys_rst 41>
303 #sound-dai-cells = <1>
304
305 port@0 {
306 evea_line: end
307 remote
308 };
309 };
310
311 port@1 {
312 evea_hp: endpo
313 remote
314 };
315 };
316 };
317
318 syscon@57920000 {
319 compatible = "socionex
320 "simple-m
321 reg = <0x57920000 0x10
322
323 adamv_rst: reset-contr
324 compatible = "
325 #reset-cells =
326 };
327 };
328
329 i2c0: i2c@58780000 {
330 compatible = "socionex
331 status = "disabled";
332 reg = <0x58780000 0x80
333 #address-cells = <1>;
334 #size-cells = <0>;
335 interrupts = <GIC_SPI
336 pinctrl-names = "defau
337 pinctrl-0 = <&pinctrl_
338 clocks = <&peri_clk 4>
339 resets = <&peri_rst 4>
340 clock-frequency = <100
341 };
342
343 i2c1: i2c@58781000 {
344 compatible = "socionex
345 status = "disabled";
346 reg = <0x58781000 0x80
347 #address-cells = <1>;
348 #size-cells = <0>;
349 interrupts = <GIC_SPI
350 pinctrl-names = "defau
351 pinctrl-0 = <&pinctrl_
352 clocks = <&peri_clk 5>
353 resets = <&peri_rst 5>
354 clock-frequency = <100
355 };
356
357 i2c2: i2c@58782000 {
358 compatible = "socionex
359 reg = <0x58782000 0x80
360 #address-cells = <1>;
361 #size-cells = <0>;
362 interrupts = <GIC_SPI
363 clocks = <&peri_clk 6>
364 resets = <&peri_rst 6>
365 clock-frequency = <400
366 };
367
368 i2c3: i2c@58783000 {
369 compatible = "socionex
370 status = "disabled";
371 reg = <0x58783000 0x80
372 #address-cells = <1>;
373 #size-cells = <0>;
374 interrupts = <GIC_SPI
375 pinctrl-names = "defau
376 pinctrl-0 = <&pinctrl_
377 clocks = <&peri_clk 7>
378 resets = <&peri_rst 7>
379 clock-frequency = <100
380 };
381
382 i2c4: i2c@58784000 {
383 compatible = "socionex
384 status = "disabled";
385 reg = <0x58784000 0x80
386 #address-cells = <1>;
387 #size-cells = <0>;
388 interrupts = <GIC_SPI
389 pinctrl-names = "defau
390 pinctrl-0 = <&pinctrl_
391 clocks = <&peri_clk 8>
392 resets = <&peri_rst 8>
393 clock-frequency = <100
394 };
395
396 i2c5: i2c@58785000 {
397 compatible = "socionex
398 reg = <0x58785000 0x80
399 #address-cells = <1>;
400 #size-cells = <0>;
401 interrupts = <GIC_SPI
402 clocks = <&peri_clk 9>
403 resets = <&peri_rst 9>
404 clock-frequency = <400
405 };
406
407 system_bus: system-bus@58c0000
408 compatible = "socionex
409 status = "disabled";
410 reg = <0x58c00000 0x40
411 #address-cells = <2>;
412 #size-cells = <1>;
413 pinctrl-names = "defau
414 pinctrl-0 = <&pinctrl_
415 };
416
417 smpctrl@59801000 {
418 compatible = "socionex
419 reg = <0x59801000 0x40
420 };
421
422 syscon@59810000 {
423 compatible = "socionex
424 "simple-m
425 reg = <0x59810000 0x40
426
427 sd_rst: reset-controll
428 compatible = "
429 #reset-cells =
430 };
431 };
432
433 syscon@59820000 {
434 compatible = "socionex
435 "simple-m
436 reg = <0x59820000 0x20
437
438 peri_clk: clock-contro
439 compatible = "
440 #clock-cells =
441 };
442
443 peri_rst: reset-contro
444 compatible = "
445 #reset-cells =
446 };
447 };
448
449 emmc: mmc@5a000000 {
450 compatible = "socionex
451 reg = <0x5a000000 0x40
452 interrupts = <GIC_SPI
453 pinctrl-names = "defau
454 pinctrl-0 = <&pinctrl_
455 clocks = <&sys_clk 4>;
456 resets = <&sys_rst 4>;
457 bus-width = <8>;
458 mmc-ddr-1_8v;
459 mmc-hs200-1_8v;
460 mmc-pwrseq = <&emmc_pw
461 cdns,phy-input-delay-l
462 cdns,phy-input-delay-m
463 cdns,phy-input-delay-m
464 cdns,phy-dll-delay-sdc
465 cdns,phy-dll-delay-sdc
466 };
467
468 usb0: usb@5a800100 {
469 compatible = "socionex
470 status = "disabled";
471 reg = <0x5a800100 0x10
472 interrupts = <GIC_SPI
473 pinctrl-names = "defau
474 pinctrl-0 = <&pinctrl_
475 clocks = <&sys_clk 8>,
476 <&mio_clk 12>
477 resets = <&sys_rst 8>,
478 <&mio_rst 12>
479 phy-names = "usb";
480 phys = <&usb_phy0>;
481 has-transaction-transl
482 };
483
484 usb1: usb@5a810100 {
485 compatible = "socionex
486 status = "disabled";
487 reg = <0x5a810100 0x10
488 interrupts = <GIC_SPI
489 pinctrl-names = "defau
490 pinctrl-0 = <&pinctrl_
491 clocks = <&sys_clk 8>,
492 <&mio_clk 13>
493 resets = <&sys_rst 8>,
494 <&mio_rst 13>
495 phy-names = "usb";
496 phys = <&usb_phy1>;
497 has-transaction-transl
498 };
499
500 usb2: usb@5a820100 {
501 compatible = "socionex
502 status = "disabled";
503 reg = <0x5a820100 0x10
504 interrupts = <GIC_SPI
505 pinctrl-names = "defau
506 pinctrl-0 = <&pinctrl_
507 clocks = <&sys_clk 8>,
508 <&mio_clk 14>
509 resets = <&sys_rst 8>,
510 <&mio_rst 14>
511 phy-names = "usb";
512 phys = <&usb_phy2>;
513 has-transaction-transl
514 };
515
516 syscon@5b3e0000 {
517 compatible = "socionex
518 "simple-m
519 reg = <0x5b3e0000 0x80
520
521 mio_clk: clock-control
522 compatible = "
523 #clock-cells =
524 };
525
526 mio_rst: reset-control
527 compatible = "
528 #reset-cells =
529 resets = <&sys
530 };
531 };
532
533 soc_glue: syscon@5f800000 {
534 compatible = "socionex
535 "simple-m
536 reg = <0x5f800000 0x20
537
538 pinctrl: pinctrl {
539 compatible = "
540 };
541
542 usb-hub {
543 compatible = "
544 #address-cells
545 #size-cells =
546
547 usb_phy0: phy@
548 reg =
549 #phy-c
550 };
551
552 usb_phy1: phy@
553 reg =
554 #phy-c
555 };
556
557 usb_phy2: phy@
558 reg =
559 #phy-c
560 };
561 };
562 };
563
564 syscon@5f900000 {
565 compatible = "socionex
566 "simple-m
567 reg = <0x5f900000 0x20
568 #address-cells = <1>;
569 #size-cells = <1>;
570 ranges = <0 0x5f900000
571
572 efuse@100 {
573 compatible = "
574 reg = <0x100 0
575 };
576
577 efuse@200 {
578 compatible = "
579 reg = <0x200 0
580 };
581 };
582
583 xdmac: dma-controller@5fc10000
584 compatible = "socionex
585 reg = <0x5fc10000 0x53
586 interrupts = <GIC_SPI
587 dma-channels = <16>;
588 #dma-cells = <2>;
589 };
590
591 aidet: interrupt-controller@5f
592 compatible = "socionex
593 reg = <0x5fc20000 0x20
594 interrupt-controller;
595 #interrupt-cells = <2>
596 };
597
598 gic: interrupt-controller@5fe0
599 compatible = "arm,gic-
600 reg = <0x5fe00000 0x10
601 <0x5fe40000 0x80
602 interrupt-controller;
603 #interrupt-cells = <3>
604 interrupts = <GIC_PPI
605 };
606
607 syscon@61840000 {
608 compatible = "socionex
609 "simple-m
610 reg = <0x61840000 0x10
611
612 sys_clk: clock-control
613 compatible = "
614 #clock-cells =
615 };
616
617 sys_rst: reset-control
618 compatible = "
619 #reset-cells =
620 };
621
622 watchdog {
623 compatible = "
624 };
625 };
626
627 eth: ethernet@65000000 {
628 compatible = "socionex
629 status = "disabled";
630 reg = <0x65000000 0x85
631 interrupts = <GIC_SPI
632 clock-names = "ether";
633 clocks = <&sys_clk 6>;
634 reset-names = "ether";
635 resets = <&sys_rst 6>;
636 phy-mode = "internal";
637 local-mac-address = [0
638 socionext,syscon-phy-m
639
640 mdio: mdio {
641 #address-cells
642 #size-cells =
643 };
644 };
645
646 nand: nand-controller@68000000
647 compatible = "socionex
648 status = "disabled";
649 reg-names = "nand_data
650 reg = <0x68000000 0x20
651 #address-cells = <1>;
652 #size-cells = <0>;
653 interrupts = <GIC_SPI
654 pinctrl-names = "defau
655 pinctrl-0 = <&pinctrl_
656 clock-names = "nand",
657 clocks = <&sys_clk 2>,
658 reset-names = "nand",
659 resets = <&sys_rst 2>,
660 };
661 };
662 };
663
664 #include "uniphier-pinctrl.dtsi"
665
666 &pinctrl_aoutiec1 {
667 drive-strength = <4>; /* default: 4m
668
669 ao1arc {
670 pins = "AO1ARC";
671 drive-strength = <8>; /* 8mA
672 };
673 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.