1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
2 //
3 // Device Tree Source for UniPhier LD20 SoC
4 //
5 // Copyright (C) 2015-2016 Socionext Inc.
6 // Author: Masahiro Yamada <yamada.masahiro@s
7
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/gpio/uniphier-gpio.h>
10 #include <dt-bindings/interrupt-controller/arm
11 #include <dt-bindings/thermal/thermal.h>
12
13 / {
14 compatible = "socionext,uniphier-ld20"
15 #address-cells = <2>;
16 #size-cells = <2>;
17 interrupt-parent = <&gic>;
18
19 cpus {
20 #address-cells = <2>;
21 #size-cells = <0>;
22
23 cpu-map {
24 cluster0 {
25 core0 {
26 cpu =
27 };
28 core1 {
29 cpu =
30 };
31 };
32
33 cluster1 {
34 core0 {
35 cpu =
36 };
37 core1 {
38 cpu =
39 };
40 };
41 };
42
43 cpu0: cpu@0 {
44 device_type = "cpu";
45 compatible = "arm,cort
46 reg = <0 0x000>;
47 clocks = <&sys_clk 32>
48 enable-method = "psci"
49 next-level-cache = <&a
50 operating-points-v2 =
51 #cooling-cells = <2>;
52 };
53
54 cpu1: cpu@1 {
55 device_type = "cpu";
56 compatible = "arm,cort
57 reg = <0 0x001>;
58 clocks = <&sys_clk 32>
59 enable-method = "psci"
60 next-level-cache = <&a
61 operating-points-v2 =
62 #cooling-cells = <2>;
63 };
64
65 cpu2: cpu@100 {
66 device_type = "cpu";
67 compatible = "arm,cort
68 reg = <0 0x100>;
69 clocks = <&sys_clk 33>
70 enable-method = "psci"
71 next-level-cache = <&a
72 operating-points-v2 =
73 #cooling-cells = <2>;
74 };
75
76 cpu3: cpu@101 {
77 device_type = "cpu";
78 compatible = "arm,cort
79 reg = <0 0x101>;
80 clocks = <&sys_clk 33>
81 enable-method = "psci"
82 next-level-cache = <&a
83 operating-points-v2 =
84 #cooling-cells = <2>;
85 };
86
87 a72_l2: l2-cache0 {
88 compatible = "cache";
89 cache-level = <2>;
90 cache-unified;
91 };
92
93 a53_l2: l2-cache1 {
94 compatible = "cache";
95 cache-level = <2>;
96 cache-unified;
97 };
98 };
99
100 cluster0_opp: opp-table-0 {
101 compatible = "operating-points
102 opp-shared;
103
104 opp-250000000 {
105 opp-hz = /bits/ 64 <25
106 clock-latency-ns = <30
107 };
108 opp-275000000 {
109 opp-hz = /bits/ 64 <27
110 clock-latency-ns = <30
111 };
112 opp-500000000 {
113 opp-hz = /bits/ 64 <50
114 clock-latency-ns = <30
115 };
116 opp-550000000 {
117 opp-hz = /bits/ 64 <55
118 clock-latency-ns = <30
119 };
120 opp-666667000 {
121 opp-hz = /bits/ 64 <66
122 clock-latency-ns = <30
123 };
124 opp-733334000 {
125 opp-hz = /bits/ 64 <73
126 clock-latency-ns = <30
127 };
128 opp-1000000000 {
129 opp-hz = /bits/ 64 <10
130 clock-latency-ns = <30
131 };
132 opp-1100000000 {
133 opp-hz = /bits/ 64 <11
134 clock-latency-ns = <30
135 };
136 };
137
138 cluster1_opp: opp-table-1 {
139 compatible = "operating-points
140 opp-shared;
141
142 opp-250000000 {
143 opp-hz = /bits/ 64 <25
144 clock-latency-ns = <30
145 };
146 opp-275000000 {
147 opp-hz = /bits/ 64 <27
148 clock-latency-ns = <30
149 };
150 opp-500000000 {
151 opp-hz = /bits/ 64 <50
152 clock-latency-ns = <30
153 };
154 opp-550000000 {
155 opp-hz = /bits/ 64 <55
156 clock-latency-ns = <30
157 };
158 opp-666667000 {
159 opp-hz = /bits/ 64 <66
160 clock-latency-ns = <30
161 };
162 opp-733334000 {
163 opp-hz = /bits/ 64 <73
164 clock-latency-ns = <30
165 };
166 opp-1000000000 {
167 opp-hz = /bits/ 64 <10
168 clock-latency-ns = <30
169 };
170 opp-1100000000 {
171 opp-hz = /bits/ 64 <11
172 clock-latency-ns = <30
173 };
174 };
175
176 psci {
177 compatible = "arm,psci-1.0";
178 method = "smc";
179 };
180
181 clocks {
182 refclk: ref {
183 compatible = "fixed-cl
184 #clock-cells = <0>;
185 clock-frequency = <250
186 };
187 };
188
189 emmc_pwrseq: emmc-pwrseq {
190 compatible = "mmc-pwrseq-emmc"
191 reset-gpios = <&gpio UNIPHIER_
192 };
193
194 timer {
195 compatible = "arm,armv8-timer"
196 interrupts = <GIC_PPI 13 IRQ_T
197 <GIC_PPI 14 IRQ_T
198 <GIC_PPI 11 IRQ_T
199 <GIC_PPI 10 IRQ_T
200 };
201
202 thermal-zones {
203 cpu-thermal {
204 polling-delay-passive
205 polling-delay = <1000>
206 thermal-sensors = <&pv
207
208 trips {
209 cpu_crit: cpu-
210 temper
211 hyster
212 type =
213 };
214 cpu_alert: cpu
215 temper
216 hyster
217 type =
218 };
219 };
220
221 cooling-maps {
222 map0 {
223 trip =
224 coolin
225
226
227
228 };
229 };
230 };
231 };
232
233 reserved-memory {
234 #address-cells = <2>;
235 #size-cells = <2>;
236 ranges;
237
238 secure-memory@81000000 {
239 reg = <0x0 0x81000000
240 no-map;
241 };
242 };
243
244 soc@0 {
245 compatible = "simple-bus";
246 #address-cells = <1>;
247 #size-cells = <1>;
248 ranges = <0 0 0 0xffffffff>;
249
250 spi0: spi@54006000 {
251 compatible = "socionex
252 status = "disabled";
253 reg = <0x54006000 0x10
254 #address-cells = <1>;
255 #size-cells = <0>;
256 interrupts = <GIC_SPI
257 pinctrl-names = "defau
258 pinctrl-0 = <&pinctrl_
259 clocks = <&peri_clk 11
260 resets = <&peri_rst 11
261 };
262
263 spi1: spi@54006100 {
264 compatible = "socionex
265 status = "disabled";
266 reg = <0x54006100 0x10
267 #address-cells = <1>;
268 #size-cells = <0>;
269 interrupts = <GIC_SPI
270 pinctrl-names = "defau
271 pinctrl-0 = <&pinctrl_
272 clocks = <&peri_clk 12
273 resets = <&peri_rst 12
274 };
275
276 spi2: spi@54006200 {
277 compatible = "socionex
278 status = "disabled";
279 reg = <0x54006200 0x10
280 #address-cells = <1>;
281 #size-cells = <0>;
282 interrupts = <GIC_SPI
283 pinctrl-names = "defau
284 pinctrl-0 = <&pinctrl_
285 clocks = <&peri_clk 13
286 resets = <&peri_rst 13
287 };
288
289 spi3: spi@54006300 {
290 compatible = "socionex
291 status = "disabled";
292 reg = <0x54006300 0x10
293 #address-cells = <1>;
294 #size-cells = <0>;
295 interrupts = <GIC_SPI
296 pinctrl-names = "defau
297 pinctrl-0 = <&pinctrl_
298 clocks = <&peri_clk 14
299 resets = <&peri_rst 14
300 };
301
302 serial0: serial@54006800 {
303 compatible = "socionex
304 status = "disabled";
305 reg = <0x54006800 0x40
306 interrupts = <GIC_SPI
307 pinctrl-names = "defau
308 pinctrl-0 = <&pinctrl_
309 clocks = <&peri_clk 0>
310 resets = <&peri_rst 0>
311 };
312
313 serial1: serial@54006900 {
314 compatible = "socionex
315 status = "disabled";
316 reg = <0x54006900 0x40
317 interrupts = <GIC_SPI
318 pinctrl-names = "defau
319 pinctrl-0 = <&pinctrl_
320 clocks = <&peri_clk 1>
321 resets = <&peri_rst 1>
322 };
323
324 serial2: serial@54006a00 {
325 compatible = "socionex
326 status = "disabled";
327 reg = <0x54006a00 0x40
328 interrupts = <GIC_SPI
329 pinctrl-names = "defau
330 pinctrl-0 = <&pinctrl_
331 clocks = <&peri_clk 2>
332 resets = <&peri_rst 2>
333 };
334
335 serial3: serial@54006b00 {
336 compatible = "socionex
337 status = "disabled";
338 reg = <0x54006b00 0x40
339 interrupts = <GIC_SPI
340 pinctrl-names = "defau
341 pinctrl-0 = <&pinctrl_
342 clocks = <&peri_clk 3>
343 resets = <&peri_rst 3>
344 };
345
346 gpio: gpio@55000000 {
347 compatible = "socionex
348 reg = <0x55000000 0x20
349 interrupt-parent = <&a
350 interrupt-controller;
351 #interrupt-cells = <2>
352 gpio-controller;
353 #gpio-cells = <2>;
354 gpio-ranges = <&pinctr
355 <&pinctr
356 <&pinctr
357 gpio-ranges-group-name
358
359
360 ngpios = <205>;
361 socionext,interrupt-ra
362
363 };
364
365 audio@56000000 {
366 compatible = "socionex
367 reg = <0x56000000 0x80
368 interrupts = <GIC_SPI
369 pinctrl-names = "defau
370 pinctrl-0 = <&pinctrl_
371 <&pinctrl_
372 clock-names = "aio";
373 clocks = <&sys_clk 40>
374 reset-names = "aio";
375 resets = <&sys_rst 40>
376 #sound-dai-cells = <1>
377 socionext,syscon = <&s
378
379 i2s_port0: port@0 {
380 i2s_hdmi: endp
381 };
382 };
383
384 i2s_port1: port@1 {
385 i2s_pcmin2: en
386 };
387 };
388
389 i2s_port2: port@2 {
390 i2s_line: endp
391 dai-fo
392 remote
393 };
394 };
395
396 i2s_port3: port@3 {
397 i2s_hpcmout1:
398 };
399 };
400
401 i2s_port4: port@4 {
402 i2s_hp: endpoi
403 dai-fo
404 remote
405 };
406 };
407
408 spdif_port0: port@5 {
409 spdif_hiecout1
410 };
411 };
412
413 src_port0: port@6 {
414 i2s_epcmout2:
415 };
416 };
417
418 src_port1: port@7 {
419 i2s_epcmout3:
420 };
421 };
422
423 comp_spdif_port0: port
424 comp_spdif_hie
425 };
426 };
427 };
428
429 codec@57900000 {
430 compatible = "socionex
431 reg = <0x57900000 0x10
432 clock-names = "evea",
433 clocks = <&sys_clk 41>
434 reset-names = "evea",
435 resets = <&sys_rst 41>
436 #sound-dai-cells = <1>
437
438 port@0 {
439 evea_line: end
440 remote
441 };
442 };
443
444 port@1 {
445 evea_hp: endpo
446 remote
447 };
448 };
449 };
450
451 syscon@57920000 {
452 compatible = "socionex
453 "simple-m
454 reg = <0x57920000 0x10
455
456 adamv_rst: reset-contr
457 compatible = "
458 #reset-cells =
459 };
460 };
461
462 i2c0: i2c@58780000 {
463 compatible = "socionex
464 status = "disabled";
465 reg = <0x58780000 0x80
466 #address-cells = <1>;
467 #size-cells = <0>;
468 interrupts = <GIC_SPI
469 pinctrl-names = "defau
470 pinctrl-0 = <&pinctrl_
471 clocks = <&peri_clk 4>
472 resets = <&peri_rst 4>
473 clock-frequency = <100
474 };
475
476 i2c1: i2c@58781000 {
477 compatible = "socionex
478 status = "disabled";
479 reg = <0x58781000 0x80
480 #address-cells = <1>;
481 #size-cells = <0>;
482 interrupts = <GIC_SPI
483 pinctrl-names = "defau
484 pinctrl-0 = <&pinctrl_
485 clocks = <&peri_clk 5>
486 resets = <&peri_rst 5>
487 clock-frequency = <100
488 };
489
490 i2c2: i2c@58782000 {
491 compatible = "socionex
492 reg = <0x58782000 0x80
493 #address-cells = <1>;
494 #size-cells = <0>;
495 interrupts = <GIC_SPI
496 clocks = <&peri_clk 6>
497 resets = <&peri_rst 6>
498 clock-frequency = <400
499 };
500
501 i2c3: i2c@58783000 {
502 compatible = "socionex
503 status = "disabled";
504 reg = <0x58783000 0x80
505 #address-cells = <1>;
506 #size-cells = <0>;
507 interrupts = <GIC_SPI
508 pinctrl-names = "defau
509 pinctrl-0 = <&pinctrl_
510 clocks = <&peri_clk 7>
511 resets = <&peri_rst 7>
512 clock-frequency = <100
513 };
514
515 i2c4: i2c@58784000 {
516 compatible = "socionex
517 status = "disabled";
518 reg = <0x58784000 0x80
519 #address-cells = <1>;
520 #size-cells = <0>;
521 interrupts = <GIC_SPI
522 pinctrl-names = "defau
523 pinctrl-0 = <&pinctrl_
524 clocks = <&peri_clk 8>
525 resets = <&peri_rst 8>
526 clock-frequency = <100
527 };
528
529 i2c5: i2c@58785000 {
530 compatible = "socionex
531 reg = <0x58785000 0x80
532 #address-cells = <1>;
533 #size-cells = <0>;
534 interrupts = <GIC_SPI
535 clocks = <&peri_clk 9>
536 resets = <&peri_rst 9>
537 clock-frequency = <400
538 };
539
540 system_bus: system-bus@58c0000
541 compatible = "socionex
542 status = "disabled";
543 reg = <0x58c00000 0x40
544 #address-cells = <2>;
545 #size-cells = <1>;
546 pinctrl-names = "defau
547 pinctrl-0 = <&pinctrl_
548 };
549
550 smpctrl@59801000 {
551 compatible = "socionex
552 reg = <0x59801000 0x40
553 };
554
555 sdctrl: syscon@59810000 {
556 compatible = "socionex
557 "simple-m
558 reg = <0x59810000 0x40
559
560 sd_clk: clock-controll
561 compatible = "
562 #clock-cells =
563 };
564
565 sd_rst: reset-controll
566 compatible = "
567 #reset-cells =
568 };
569 };
570
571 syscon@59820000 {
572 compatible = "socionex
573 "simple-m
574 reg = <0x59820000 0x20
575
576 peri_clk: clock-contro
577 compatible = "
578 #clock-cells =
579 };
580
581 peri_rst: reset-contro
582 compatible = "
583 #reset-cells =
584 };
585 };
586
587 emmc: mmc@5a000000 {
588 compatible = "socionex
589 reg = <0x5a000000 0x40
590 interrupts = <GIC_SPI
591 pinctrl-names = "defau
592 pinctrl-0 = <&pinctrl_
593 clocks = <&sys_clk 4>;
594 resets = <&sys_rst 4>;
595 bus-width = <8>;
596 mmc-ddr-1_8v;
597 mmc-hs200-1_8v;
598 mmc-pwrseq = <&emmc_pw
599 cdns,phy-input-delay-l
600 cdns,phy-input-delay-m
601 cdns,phy-input-delay-m
602 cdns,phy-dll-delay-sdc
603 cdns,phy-dll-delay-sdc
604 };
605
606 sd: mmc@5a400000 {
607 compatible = "socionex
608 status = "disabled";
609 reg = <0x5a400000 0x80
610 interrupts = <GIC_SPI
611 pinctrl-names = "defau
612 pinctrl-0 = <&pinctrl_
613 clocks = <&sd_clk 0>;
614 reset-names = "host";
615 resets = <&sd_rst 0>;
616 bus-width = <4>;
617 cap-sd-highspeed;
618 socionext,syscon-uhs-m
619 };
620
621 soc_glue: syscon@5f800000 {
622 compatible = "socionex
623 "simple-m
624 reg = <0x5f800000 0x20
625
626 pinctrl: pinctrl {
627 compatible = "
628 };
629 };
630
631 syscon@5f900000 {
632 compatible = "socionex
633 "simple-m
634 reg = <0x5f900000 0x20
635 #address-cells = <1>;
636 #size-cells = <1>;
637 ranges = <0 0x5f900000
638
639 efuse@100 {
640 compatible = "
641 reg = <0x100 0
642 };
643
644 efuse@200 {
645 compatible = "
646 reg = <0x200 0
647 #address-cells
648 #size-cells =
649
650 /* USB cells *
651 usb_rterm0: tr
652 reg =
653 bits =
654 };
655 usb_rterm1: tr
656 reg =
657 bits =
658 };
659 usb_rterm2: tr
660 reg =
661 bits =
662 };
663 usb_rterm3: tr
664 reg =
665 bits =
666 };
667 usb_sel_t0: tr
668 reg =
669 bits =
670 };
671 usb_sel_t1: tr
672 reg =
673 bits =
674 };
675 usb_sel_t2: tr
676 reg =
677 bits =
678 };
679 usb_sel_t3: tr
680 reg =
681 bits =
682 };
683 usb_hs_i0: tri
684 reg =
685 bits =
686 };
687 usb_hs_i2: tri
688 reg =
689 bits =
690 };
691 };
692 };
693
694 xdmac: dma-controller@5fc10000
695 compatible = "socionex
696 reg = <0x5fc10000 0x53
697 interrupts = <GIC_SPI
698 dma-channels = <16>;
699 #dma-cells = <2>;
700 };
701
702 aidet: interrupt-controller@5f
703 compatible = "socionex
704 reg = <0x5fc20000 0x20
705 interrupt-controller;
706 #interrupt-cells = <2>
707 };
708
709 gic: interrupt-controller@5fe0
710 compatible = "arm,gic-
711 reg = <0x5fe00000 0x10
712 <0x5fe80000 0x80
713 interrupt-controller;
714 #interrupt-cells = <3>
715 interrupts = <GIC_PPI
716 };
717
718 syscon@61840000 {
719 compatible = "socionex
720 "simple-m
721 reg = <0x61840000 0x10
722
723 sys_clk: clock-control
724 compatible = "
725 #clock-cells =
726 };
727
728 sys_rst: reset-control
729 compatible = "
730 #reset-cells =
731 };
732
733 watchdog {
734 compatible = "
735 };
736
737 pvtctl: thermal-sensor
738 compatible = "
739 interrupts = <
740 #thermal-senso
741 socionext,tmod
742 };
743 };
744
745 eth: ethernet@65000000 {
746 compatible = "socionex
747 status = "disabled";
748 reg = <0x65000000 0x85
749 interrupts = <GIC_SPI
750 pinctrl-names = "defau
751 pinctrl-0 = <&pinctrl_
752 clock-names = "ether";
753 clocks = <&sys_clk 6>;
754 reset-names = "ether";
755 resets = <&sys_rst 6>;
756 phy-mode = "rgmii-id";
757 local-mac-address = [0
758 socionext,syscon-phy-m
759
760 mdio: mdio {
761 #address-cells
762 #size-cells =
763 };
764 };
765
766 usb: usb@65a00000 {
767 compatible = "socionex
768 status = "disabled";
769 reg = <0x65a00000 0xcd
770 interrupt-names = "hos
771 interrupts = <GIC_SPI
772 pinctrl-names = "defau
773 pinctrl-0 = <&pinctrl_
774 <&pinctrl_
775 clock-names = "ref", "
776 clocks = <&sys_clk 14>
777 resets = <&usb_rst 15>
778 phys = <&usb_hsphy0>,
779 <&usb_hsphy2>,
780 <&usb_ssphy0>,
781 dr_mode = "host";
782 };
783
784 usb-controller@65b00000 {
785 compatible = "socionex
786 "simple-m
787 reg = <0x65b00000 0x40
788 #address-cells = <1>;
789 #size-cells = <1>;
790 ranges = <0 0x65b00000
791
792 usb_rst: reset-control
793 compatible = "
794 reg = <0x0 0x4
795 #reset-cells =
796 clock-names =
797 clocks = <&sys
798 reset-names =
799 resets = <&sys
800 };
801
802 usb_vbus0: regulator@1
803 compatible = "
804 reg = <0x100 0
805 clock-names =
806 clocks = <&sys
807 reset-names =
808 resets = <&sys
809 };
810
811 usb_vbus1: regulator@1
812 compatible = "
813 reg = <0x110 0
814 clock-names =
815 clocks = <&sys
816 reset-names =
817 resets = <&sys
818 };
819
820 usb_vbus2: regulator@1
821 compatible = "
822 reg = <0x120 0
823 clock-names =
824 clocks = <&sys
825 reset-names =
826 resets = <&sys
827 };
828
829 usb_vbus3: regulator@1
830 compatible = "
831 reg = <0x130 0
832 clock-names =
833 clocks = <&sys
834 reset-names =
835 resets = <&sys
836 };
837
838 usb_hsphy0: phy@200 {
839 compatible = "
840 reg = <0x200 0
841 #phy-cells = <
842 clock-names =
843 clocks = <&sys
844 reset-names =
845 resets = <&sys
846 vbus-supply =
847 nvmem-cell-nam
848 nvmem-cells =
849
850 };
851
852 usb_hsphy1: phy@210 {
853 compatible = "
854 reg = <0x210 0
855 #phy-cells = <
856 clock-names =
857 clocks = <&sys
858 reset-names =
859 resets = <&sys
860 vbus-supply =
861 nvmem-cell-nam
862 nvmem-cells =
863
864 };
865
866 usb_hsphy2: phy@220 {
867 compatible = "
868 reg = <0x220 0
869 #phy-cells = <
870 clock-names =
871 clocks = <&sys
872 reset-names =
873 resets = <&sys
874 vbus-supply =
875 nvmem-cell-nam
876 nvmem-cells =
877
878 };
879
880 usb_hsphy3: phy@230 {
881 compatible = "
882 reg = <0x230 0
883 #phy-cells = <
884 clock-names =
885 clocks = <&sys
886 reset-names =
887 resets = <&sys
888 vbus-supply =
889 nvmem-cell-nam
890 nvmem-cells =
891
892 };
893
894 usb_ssphy0: phy@300 {
895 compatible = "
896 reg = <0x300 0
897 #phy-cells = <
898 clock-names =
899 clocks = <&sys
900 reset-names =
901 resets = <&sys
902 vbus-supply =
903 };
904
905 usb_ssphy1: phy@310 {
906 compatible = "
907 reg = <0x310 0
908 #phy-cells = <
909 clock-names =
910 clocks = <&sys
911 reset-names =
912 resets = <&sys
913 vbus-supply =
914 };
915 };
916
917 pcie: pcie@66000000 {
918 compatible = "socionex
919 status = "disabled";
920 reg-names = "dbi", "li
921 reg = <0x66000000 0x10
922 <0x2fff0000 0x10
923 #address-cells = <3>;
924 #size-cells = <2>;
925 clocks = <&sys_clk 24>
926 resets = <&sys_rst 24>
927 num-lanes = <1>;
928 num-viewport = <1>;
929 bus-range = <0x0 0xff>
930 device_type = "pci";
931 ranges =
932 /* downstream I/O */
933 <0x81000000 0
934 /* non-prefetchable me
935 <0x82000000 0
936 #interrupt-cells = <1>
937 interrupt-names = "dma
938 interrupts = <GIC_SPI
939 <GIC_SPI
940 interrupt-map-mask = <
941 interrupt-map = <0 0 0
942 <0 0 0
943 <0 0 0
944 <0 0 0
945 phy-names = "pcie-phy"
946 phys = <&pcie_phy>;
947
948 pcie_intc: legacy-inte
949 interrupt-cont
950 #interrupt-cel
951 interrupt-pare
952 interrupts = <
953 };
954 };
955
956 pcie_phy: phy@66038000 {
957 compatible = "socionex
958 reg = <0x66038000 0x40
959 #phy-cells = <0>;
960 clock-names = "link";
961 clocks = <&sys_clk 24>
962 reset-names = "link";
963 resets = <&sys_rst 24>
964 socionext,syscon = <&s
965 };
966
967 nand: nand-controller@68000000
968 compatible = "socionex
969 status = "disabled";
970 reg-names = "nand_data
971 reg = <0x68000000 0x20
972 #address-cells = <1>;
973 #size-cells = <0>;
974 interrupts = <GIC_SPI
975 pinctrl-names = "defau
976 pinctrl-0 = <&pinctrl_
977 clock-names = "nand",
978 clocks = <&sys_clk 2>,
979 reset-names = "nand",
980 resets = <&sys_rst 2>,
981 };
982 };
983 };
984
985 #include "uniphier-pinctrl.dtsi"
986
987 &pinctrl_aout1 {
988 drive-strength = <4>; /* default: 3.
989
990 ao1dacck {
991 pins = "AO1DACCK";
992 drive-strength = <5>; /* 5mA
993 };
994 };
995
996 &pinctrl_aoutiec1 {
997 drive-strength = <4>; /* default: 3.
998
999 ao1arc {
1000 pins = "AO1ARC";
1001 drive-strength = <11>; /* 11
1002 };
1003 };
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