1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /*
3 * Unisoc UMS512 SoC DTS file
4 *
5 * Copyright (C) 2021, Unisoc Inc.
6 */
7
8 #include <dt-bindings/clock/sprd,ums512-clk.h>
9 #include <dt-bindings/interrupt-controller/arm
10
11 / {
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
15
16 cpus {
17 #address-cells = <2>;
18 #size-cells = <0>;
19
20 cpu-map {
21 cluster0 {
22 core0 {
23 cpu =
24 };
25 core1 {
26 cpu =
27 };
28 core2 {
29 cpu =
30 };
31 core3 {
32 cpu =
33 };
34 core4 {
35 cpu =
36 };
37 core5 {
38 cpu =
39 };
40 core6 {
41 cpu =
42 };
43 core7 {
44 cpu =
45 };
46 };
47 };
48
49 CPU0: cpu@0 {
50 device_type = "cpu";
51 compatible = "arm,cort
52 reg = <0x0 0x0>;
53 enable-method = "psci"
54 cpu-idle-states = <&CO
55 };
56
57 CPU1: cpu@100 {
58 device_type = "cpu";
59 compatible = "arm,cort
60 reg = <0x0 0x100>;
61 enable-method = "psci"
62 cpu-idle-states = <&CO
63 };
64
65 CPU2: cpu@200 {
66 device_type = "cpu";
67 compatible = "arm,cort
68 reg = <0x0 0x200>;
69 enable-method = "psci"
70 cpu-idle-states = <&CO
71 };
72
73 CPU3: cpu@300 {
74 device_type = "cpu";
75 compatible = "arm,cort
76 reg = <0x0 0x300>;
77 enable-method = "psci"
78 cpu-idle-states = <&CO
79 };
80
81 CPU4: cpu@400 {
82 device_type = "cpu";
83 compatible = "arm,cort
84 reg = <0x0 0x400>;
85 enable-method = "psci"
86 cpu-idle-states = <&CO
87 };
88
89 CPU5: cpu@500 {
90 device_type = "cpu";
91 compatible = "arm,cort
92 reg = <0x0 0x500>;
93 enable-method = "psci"
94 cpu-idle-states = <&CO
95 };
96
97 CPU6: cpu@600 {
98 device_type = "cpu";
99 compatible = "arm,cort
100 reg = <0x0 0x600>;
101 enable-method = "psci"
102 cpu-idle-states = <&CO
103 };
104
105 CPU7: cpu@700 {
106 device_type = "cpu";
107 compatible = "arm,cort
108 reg = <0x0 0x700>;
109 enable-method = "psci"
110 cpu-idle-states = <&CO
111 };
112 };
113
114 idle-states {
115 entry-method = "psci";
116 CORE_PD: cpu-pd {
117 compatible = "arm,idle
118 entry-latency-us = <40
119 exit-latency-us = <400
120 min-residency-us = <10
121 local-timer-stop;
122 arm,psci-suspend-param
123 };
124 };
125
126 psci {
127 compatible = "arm,psci-0.2";
128 method = "smc";
129 };
130
131 timer {
132 compatible = "arm,armv8-timer"
133 interrupts = <GIC_PPI 13 IRQ_T
134 <GIC_PPI 14 IRQ_T
135 <GIC_PPI 11 IRQ_T
136 <GIC_PPI 10 IRQ_T
137 };
138
139 pmu-a55 {
140 compatible = "arm,cortex-a55-p
141 interrupts = <GIC_SPI 112 IRQ_
142 <GIC_SPI 113 IRQ_
143 <GIC_SPI 114 IRQ_
144 <GIC_SPI 115 IRQ_
145 <GIC_SPI 116 IRQ_
146 <GIC_SPI 117 IRQ_
147 interrupt-affinity = <&CPU0>,
148 };
149
150 pmu-a75 {
151 compatible = "arm,cortex-a75-p
152 interrupts = <GIC_SPI 118 IRQ_
153 <GIC_SPI 119 IRQ_
154 interrupt-affinity = <&CPU6>,
155 };
156
157 soc: soc {
158 compatible = "simple-bus";
159 #address-cells = <2>;
160 #size-cells = <2>;
161 ranges;
162
163 gic: interrupt-controller@1200
164 compatible = "arm,gic-
165 reg = <0x0 0x12000000
166 <0x0 0x12040000
167 #interrupt-cells = <3>
168 #address-cells = <2>;
169 #size-cells = <2>;
170 ranges;
171 redistributor-stride =
172 #redistributor-regions
173 interrupt-controller;
174 interrupts = <GIC_PPI
175 };
176
177 ap_ahb_regs: syscon@20100000 {
178 compatible = "sprd,ums
179 "simple-m
180 reg = <0 0x20100000 0
181 #address-cells = <1>;
182 #size-cells = <1>;
183 ranges = <0 0 0x201000
184
185 apahb_gate: clock-cont
186 compatible = "
187 reg = <0x0 0x3
188 clocks = <&ext
189 clock-names =
190 #clock-cells =
191 };
192 };
193
194 pub_apb_regs: syscon@31050000
195 compatible = "sprd,ums
196 "simple-m
197 reg = <0 0x31050000 0
198 };
199
200 top_dvfs_apb_regs: syscon@322a
201 compatible = "sprd,ums
202 "simple-m
203 reg = <0 0x322a0000 0
204 };
205
206 ap_intc0_regs: syscon@32310000
207 compatible = "sprd,ums
208 "simple-m
209 reg = <0 0x32310000 0
210 };
211
212 ap_intc1_regs: syscon@32320000
213 compatible = "sprd,ums
214 "simple-m
215 reg = <0 0x32320000 0
216 };
217
218 ap_intc2_regs: syscon@32330000
219 compatible = "sprd,ums
220 "simple-m
221 reg = <0 0x32330000 0
222 };
223
224 ap_intc3_regs: syscon@32340000
225 compatible = "sprd,ums
226 "simple-m
227 reg = <0 0x32340000 0
228 };
229
230 ap_intc4_regs: syscon@32350000
231 compatible = "sprd,ums
232 "simple-m
233 reg = <0 0x32350000 0
234 };
235
236 ap_intc5_regs: syscon@32360000
237 compatible = "sprd,ums
238 "simple-m
239 reg = <0 0x32360000 0
240 };
241
242 anlg_phy_g0_regs: syscon@32390
243 compatible = "sprd,ums
244 "simple-m
245 reg = <0 0x32390000 0
246 #address-cells = <1>;
247 #size-cells = <1>;
248 ranges = <0 0 0x323900
249
250 dpll0: clock-controlle
251 compatible = "
252 reg = <0x0 0x1
253 #clock-cells =
254 };
255 };
256
257 anlg_phy_g2_regs: syscon@323b0
258 compatible = "sprd,ums
259 "simple-m
260 reg = <0 0x323b0000 0
261 #address-cells = <1>;
262 #size-cells = <1>;
263 ranges = <0 0 0x323b00
264
265 mpll1: clock-controlle
266 compatible = "
267 reg = <0x0 0x1
268 #clock-cells =
269 };
270 };
271
272 anlg_phy_g3_regs: syscon@323c0
273 compatible = "sprd,ums
274 "simple-m
275 reg = <0 0x323c0000 0
276 #address-cells = <1>;
277 #size-cells = <1>;
278 ranges = <0 0 0x323c00
279
280 pll1: clock-controller
281 compatible = "
282 reg = <0x0 0x3
283 clocks = <&ext
284 clock-names =
285 #clock-cells =
286 };
287 };
288
289 anlg_phy_gc_regs: syscon@323e0
290 compatible = "sprd,ums
291 "simple-m
292 reg = <0 0x323e0000 0
293 #address-cells = <1>;
294 #size-cells = <1>;
295 ranges = <0 0 0x323e00
296
297 pll2: clock-controller
298 compatible = "
299 reg = <0x0 0x1
300 clocks = <&ext
301 clock-names =
302 #clock-cells =
303 };
304 };
305
306 anlg_phy_g10_regs: syscon@323f
307 compatible = "sprd,ums
308 "simple-m
309 reg = <0 0x323f0000 0
310 };
311
312 aon_apb_regs: syscon@327d0000
313 compatible = "sprd,ums
314 "simple-m
315 reg = <0 0x327d0000 0
316 #address-cells = <1>;
317 #size-cells = <1>;
318 ranges = <0 0 0x327d00
319
320 aonapb_gate: clock-con
321 compatible = "
322 reg = <0x0 0x3
323 clocks = <&ext
324 clock-names =
325 #clock-cells =
326 };
327 };
328
329 pmu_apb_regs: syscon@327e0000
330 compatible = "sprd,ums
331 "simple-m
332 reg = <0 0x327e0000 0
333 #address-cells = <1>;
334 #size-cells = <1>;
335 ranges = <0 0 0x327e00
336
337 pmu_gate: clock-contro
338 compatible = "
339 reg = <0x0 0x3
340 clocks = <&ext
341 clock-names =
342 #clock-cells =
343 };
344 };
345
346 audcp_apb_regs: syscon@3350d00
347 compatible = "sprd,ums
348 "simple-m
349 reg = <0 0x3350d000 0
350 #address-cells = <1>;
351 #size-cells = <1>;
352 ranges = <0 0 0x3350d0
353
354 audcpapb_gate: clock-c
355 compatible = "
356 reg = <0x0 0x3
357 #clock-cells =
358 };
359 };
360
361 audcp_ahb_regs: syscon@335e000
362 compatible = "sprd,ums
363 "simple-m
364 reg = <0 0x335e0000 0
365 #address-cells = <1>;
366 #size-cells = <1>;
367 ranges = <0 0 0x335e00
368
369 audcpahb_gate: clock-c
370 compatible = "
371 reg = <0x0 0x3
372 #clock-cells =
373 };
374 };
375
376 gpu_apb_regs: syscon@60100000
377 compatible = "sprd,ums
378 "simple-m
379 reg = <0 0x60100000 0
380 #address-cells = <1>;
381 #size-cells = <1>;
382 ranges = <0 0 0x601000
383
384 gpu_clk: clock-control
385 compatible = "
386 clocks = <&ext
387 clock-names =
388 reg = <0x0 0x1
389 #clock-cells =
390 };
391 };
392
393 gpu_dvfs_apb_regs: syscon@6011
394 compatible = "sprd,ums
395 "simple-m
396 reg = <0 0x60110000 0
397 };
398
399 mm_ahb_regs: syscon@62200000 {
400 compatible = "sprd,ums
401 "simple-m
402 reg = <0 0x62200000 0
403 #address-cells = <1>;
404 #size-cells = <1>;
405 ranges = <0 0 0x622000
406
407 mm_gate: clock-control
408 compatible = "
409 reg = <0x0 0x3
410 #clock-cells =
411 };
412 };
413
414 ap_apb_regs: syscon@71000000 {
415 compatible = "sprd,ums
416 "simple-m
417 reg = <0 0x71000000 0
418 #address-cells = <1>;
419 #size-cells = <1>;
420 ranges = <0 0 0x710000
421
422 apapb_gate: clock-cont
423 compatible = "
424 reg = <0x0 0x3
425 #clock-cells =
426 };
427 };
428
429 ap_clk: clock-controller@20200
430 compatible = "sprd,ums
431 reg = <0 0x20200000 0
432 clocks = <&ext_26m>;
433 clock-names = "ext-26m
434 #clock-cells = <1>;
435 };
436
437 aon_clk: clock-controller@3208
438 compatible = "sprd,ums
439 reg = <0 0x32080000 0
440 clocks = <&ext_26m>, <
441 <&ext_4m>, <&
442 clock-names = "ext-26m
443 "ext-4m"
444 #clock-cells = <1>;
445 };
446
447 mm_clk: clock-controller@62100
448 compatible = "sprd,ums
449 reg = <0 0x62100000 0
450 clocks = <&ext_26m>;
451 clock-names = "ext-26m
452 #clock-cells = <1>;
453 };
454
455 /* SoC Funnel */
456 funnel@3c002000 {
457 compatible = "arm,core
458 reg = <0 0x3c002000 0
459 clocks = <&ext_26m>;
460 clock-names = "apb_pcl
461
462 out-ports {
463 port {
464 funnel
465
466 };
467 };
468 };
469
470 in-ports {
471 #address-cells
472 #size-cells =
473
474 port@1 {
475 reg =
476 funnel
477
478
479 };
480 };
481 };
482 };
483
484 /* SoC ETF */
485 soc_etb: etb@3c003000 {
486 compatible = "arm,core
487 reg = <0 0x3c003000 0
488 clocks = <&ext_26m>;
489 clock-names = "apb_pcl
490
491 in-ports {
492 port {
493 etb_in
494
495
496 };
497 };
498 };
499 };
500
501 /* AP-CPU Funnel for core3/4/5
502 funnel@3e001000 {
503 compatible = "arm,core
504 reg = <0 0x3e001000 0
505 clocks = <&ext_26m>;
506 clock-names = "apb_pcl
507
508 out-ports {
509 port {
510 funnel
511
512
513 };
514 };
515 };
516
517 in-ports {
518 #address-cells
519 #size-cells =
520
521 port@0 {
522 reg =
523 funnel
524
525 };
526 };
527
528 port@1 {
529 reg =
530 funnel
531
532 };
533 };
534
535 port@2 {
536 reg =
537 funnel
538
539 };
540 };
541
542 port@3 {
543 reg =
544 funnel
545
546 };
547 };
548 };
549 };
550
551 /* AP-CPU ETF for little cores
552 etf@3e002000 {
553 compatible = "arm,core
554 reg = <0 0x3e002000 0
555 clocks = <&ext_26m>;
556 clock-names = "apb_pcl
557
558 out-ports {
559 port {
560 corint
561
562
563 };
564 };
565 };
566
567 in-ports {
568 port {
569 corint
570
571
572 };
573 };
574 };
575 };
576
577 /* AP-CPU ETF for big cores */
578 etf@3e003000 {
579 compatible = "arm,core
580 reg = <0 0x3e003000 0
581 clocks = <&ext_26m>;
582 clock-names = "apb_pcl
583
584 out-ports {
585 port {
586 corint
587
588
589 };
590 };
591 };
592
593 in-ports {
594 port {
595 corint
596
597
598 };
599 };
600 };
601 };
602
603 /* Funnel to SoC */
604 funnel@3e004000 {
605 compatible = "arm,core
606 reg = <0 0x3e004000 0
607 clocks = <&ext_26m>;
608 clock-names = "apb_pcl
609
610 out-ports {
611 port {
612 funnel
613
614
615 };
616 };
617 };
618
619 in-ports {
620 #address-cells
621 #size-cells =
622
623 port@0 {
624 reg =
625 funnel
626
627 };
628 };
629
630 port@1 {
631 reg =
632 funnel
633
634 };
635 };
636 };
637 };
638
639 /* AP-CPU Funnel for core0/1/2
640 funnel@3e005000 {
641 compatible = "arm,core
642 reg = <0 0x3e005000 0
643 clocks = <&ext_26m>;
644 clock-names = "apb_pcl
645
646 out-ports {
647 port {
648 funnel
649
650 };
651 };
652 };
653
654 in-ports {
655 #address-cells
656 #size-cells =
657
658 port@0 {
659 reg =
660 funnel
661
662 };
663 };
664
665 port@1 {
666 reg =
667 funnel
668
669 };
670 };
671
672 port@2 {
673 reg =
674 funnel
675
676 };
677 };
678
679 port@3 {
680 reg =
681 funnel
682
683 };
684 };
685 };
686 };
687
688 etm0: etm@3f040000 {
689 compatible = "arm,core
690 reg = <0 0x3f040000 0
691 cpu = <&CPU0>;
692 clocks = <&ext_26m>;
693 clock-names = "apb_pcl
694
695 out-ports {
696 port {
697 etm0_o
698
699
700 };
701 };
702 };
703 };
704
705 etm1: etm@3f140000 {
706 compatible = "arm,core
707 reg = <0 0x3f140000 0
708 cpu = <&CPU1>;
709 clocks = <&ext_26m>;
710 clock-names = "apb_pcl
711
712 out-ports {
713 port {
714 etm1_o
715
716
717 };
718 };
719 };
720 };
721
722 etm2: etm@3f240000 {
723 compatible = "arm,core
724 reg = <0 0x3f240000 0
725 cpu = <&CPU2>;
726 clocks = <&ext_26m>;
727 clock-names = "apb_pcl
728
729 out-ports {
730 port {
731 etm2_o
732
733
734 };
735 };
736 };
737 };
738
739 etm3: etm@3f340000 {
740 compatible = "arm,core
741 reg = <0 0x3f340000 0
742 cpu = <&CPU3>;
743 clocks = <&ext_26m>;
744 clock-names = "apb_pcl
745
746 out-ports {
747 port {
748 etm3_o
749
750
751 };
752 };
753 };
754 };
755
756 etm4: etm@3f440000 {
757 compatible = "arm,core
758 reg = <0 0x3f440000 0
759 cpu = <&CPU4>;
760 clocks = <&ext_26m>;
761 clock-names = "apb_pcl
762
763 out-ports {
764 port {
765 etm4_o
766
767
768 };
769 };
770 };
771 };
772
773 etm5: etm@3f540000 {
774 compatible = "arm,core
775 reg = <0 0x3f540000 0
776 cpu = <&CPU5>;
777 clocks = <&ext_26m>;
778 clock-names = "apb_pcl
779
780 out-ports {
781 port {
782 etm5_o
783
784
785 };
786 };
787 };
788 };
789
790 etm6: etm@3f640000 {
791 compatible = "arm,core
792 reg = <0 0x3f640000 0
793 cpu = <&CPU6>;
794 clocks = <&ext_26m>;
795 clock-names = "apb_pcl
796
797 out-ports {
798 port {
799 etm6_o
800
801
802 };
803 };
804 };
805 };
806
807 etm7: etm@3f740000 {
808 compatible = "arm,core
809 reg = <0 0x3f740000 0
810 cpu = <&CPU7>;
811 clocks = <&ext_26m>;
812 clock-names = "apb_pcl
813
814 out-ports {
815 port {
816 etm7_o
817
818
819 };
820 };
821 };
822 };
823
824 apb@70000000 {
825 compatible = "simple-b
826 #address-cells = <1>;
827 #size-cells = <1>;
828 ranges = <0 0x0 0x7000
829
830 uart0: serial@0 {
831 compatible = "
832 "
833 reg = <0x0 0x1
834 interrupts = <
835 clocks = <&ext
836 status = "disa
837 };
838
839 uart1: serial@100000 {
840 compatible = "
841 "
842 reg = <0x10000
843 interrupts = <
844 clocks = <&ext
845 status = "disa
846 };
847
848 sdio0: mmc@1100000 {
849 compatible = "
850 reg = <0x11000
851 interrupts = <
852 clocks = <&ap_
853 <&apa
854 clock-names =
855 assigned-clock
856 assigned-clock
857 status = "disa
858 };
859
860 sdio3: mmc@1400000 {
861 compatible = "
862 reg = <0x14000
863 interrupts = <
864 clocks = <&ap_
865 <&apa
866 clock-names =
867 assigned-clock
868 assigned-clock
869 status = "disa
870 };
871 };
872
873 aon: bus@32000000 {
874 compatible = "simple-b
875 #address-cells = <1>;
876 #size-cells = <1>;
877 ranges = <0 0x0 0x3200
878
879 adi_bus: spi@100000 {
880 compatible = "
881 reg = <0x10000
882 #address-cells
883 #size-cells =
884 sprd,hw-channe
885 <17 0x
886 <35 0x
887 };
888 };
889 };
890
891 ext_26m: clk-26m {
892 compatible = "fixed-clock";
893 #clock-cells = <0>;
894 clock-frequency = <26000000>;
895 clock-output-names = "ext-26m"
896 };
897
898 ext_32k: clk-32k {
899 compatible = "fixed-clock";
900 #clock-cells = <0>;
901 clock-frequency = <32768>;
902 clock-output-names = "ext-32k"
903 };
904
905 ext_4m: clk-4m {
906 compatible = "fixed-clock";
907 #clock-cells = <0>;
908 clock-frequency = <4000000>;
909 clock-output-names = "ext-4m";
910 };
911
912 rco_100m: clk-100m {
913 compatible = "fixed-clock";
914 #clock-cells = <0>;
915 clock-frequency = <100000000>;
916 clock-output-names = "rco-100m
917 };
918 };
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