1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Spreadtrum Whale2 platform peripherals
4 *
5 * Copyright (C) 2016, Spreadtrum Communicatio
6 */
7
8 #include <dt-bindings/clock/sprd,sc9860-clk.h>
9
10 / {
11 interrupt-parent = <&gic>;
12 #address-cells = <2>;
13 #size-cells = <2>;
14
15 soc: soc {
16 compatible = "simple-bus";
17 #address-cells = <2>;
18 #size-cells = <2>;
19 ranges;
20
21 ap_ahb_regs: syscon@20210000 {
22 compatible = "syscon";
23 reg = <0 0x20210000 0
24 };
25
26 pmu_regs: syscon@402b0000 {
27 compatible = "syscon";
28 reg = <0 0x402b0000 0
29 };
30
31 aon_regs: syscon@402e0000 {
32 compatible = "syscon";
33 reg = <0 0x402e0000 0
34 };
35
36 ana_regs: syscon@40400000 {
37 compatible = "syscon";
38 reg = <0 0x40400000 0
39 };
40
41 agcp_regs: syscon@415e0000 {
42 compatible = "syscon";
43 reg = <0 0x415e0000 0
44 };
45
46 vsp_regs: syscon@61100000 {
47 compatible = "syscon";
48 reg = <0 0x61100000 0
49 };
50
51 cam_regs: syscon@62100000 {
52 compatible = "syscon";
53 reg = <0 0x62100000 0
54 };
55
56 disp_regs: syscon@63100000 {
57 compatible = "syscon";
58 reg = <0 0x63100000 0
59 };
60
61 ap_apb_regs: syscon@70b00000 {
62 compatible = "syscon";
63 reg = <0 0x70b00000 0
64 };
65
66 ap-apb@70000000 {
67 compatible = "simple-b
68 #address-cells = <1>;
69 #size-cells = <1>;
70 ranges = <0 0x0 0x7000
71
72 uart0: serial@0 {
73 compatible = "
74 "
75 reg = <0x0 0x1
76 interrupts = <
77 clocks = <&apa
78 <&ap_
79 <&ext
80 clock-names =
81 status = "disa
82 };
83
84 uart1: serial@100000 {
85 compatible = "
86 "
87 reg = <0x10000
88 interrupts = <
89 clocks = <&apa
90 <&ap_
91 <&ext
92 clock-names =
93 status = "disa
94 };
95
96 uart2: serial@200000 {
97 compatible = "
98 "
99 reg = <0x20000
100 interrupts = <
101 clocks = <&apa
102 <&ap_
103 <&ext
104 clock-names =
105 status = "disa
106 };
107
108 uart3: serial@300000 {
109 compatible = "
110 "
111 reg = <0x30000
112 interrupts = <
113 clocks = <&apa
114 <&ap_
115 <&ext
116 clock-names =
117 status = "disa
118 };
119 };
120
121 ap-ahb {
122 compatible = "simple-b
123 #address-cells = <2>;
124 #size-cells = <2>;
125 ranges;
126
127 ap_dma: dma-controller
128 compatible = "
129 reg = <0 0x201
130 interrupts = <
131 #dma-cells = <
132 /* For backwar
133 #dma-channels
134 dma-channels =
135 clocks = <&apa
136 clock-names =
137 };
138
139 sdio3: mmc@50430000 {
140 compatible = "
141 reg = <0 0x504
142 interrupts = <
143
144 clocks = <&aon
145 <&apa
146 <&aon
147 clock-names =
148 assigned-clock
149 assigned-clock
150
151 sprd,phy-delay
152 sprd,phy-delay
153 sprd,phy-delay
154 sprd,phy-delay
155 vmmc-supply =
156 bus-width = <8
157 non-removable;
158 no-sdio;
159 no-sd;
160 cap-mmc-hw-res
161 mmc-hs400-enha
162 mmc-hs400-1_8v
163 mmc-hs200-1_8v
164 mmc-ddr-1_8v;
165 };
166 };
167
168 aon {
169 compatible = "simple-b
170 #address-cells = <2>;
171 #size-cells = <2>;
172 ranges;
173
174 adi_bus: spi@40030000
175 compatible = "
176 reg = <0 0x400
177 hwlocks = <&hw
178 hwlock-names =
179 #address-cells
180 #size-cells =
181 };
182
183 timer@40050000 {
184 compatible = "
185 reg = <0 0x400
186 interrupts = <
187 clocks = <&ext
188 };
189
190 timer@40050020 {
191 compatible = "
192 reg = <0 0x400
193 clocks = <&ext
194 };
195
196 hwlock: hwspinlock@405
197 compatible = "
198 reg = <0 0x405
199 #hwlock-cells
200 clocks = <&aon
201 clock-names =
202 };
203
204 eic_debounce: gpio@402
205 compatible = "
206 reg = <0 0x402
207 gpio-controlle
208 #gpio-cells =
209 interrupt-cont
210 #interrupt-cel
211 interrupts = <
212 };
213
214 eic_latch: gpio@402100
215 compatible = "
216 reg = <0 0x402
217 gpio-controlle
218 #gpio-cells =
219 interrupt-cont
220 #interrupt-cel
221 interrupts = <
222 };
223
224 eic_async: gpio@402100
225 compatible = "
226 reg = <0 0x402
227 gpio-controlle
228 #gpio-cells =
229 interrupt-cont
230 #interrupt-cel
231 interrupts = <
232 };
233
234 eic_sync: gpio@402100c
235 compatible = "
236 reg = <0 0x402
237 gpio-controlle
238 #gpio-cells =
239 interrupt-cont
240 #interrupt-cel
241 interrupts = <
242 };
243
244 ap_gpio: gpio@40280000
245 compatible = "
246 reg = <0 0x402
247 gpio-controlle
248 #gpio-cells =
249 interrupt-cont
250 #interrupt-cel
251 interrupts = <
252 };
253
254 pin_controller: pinctr
255 compatible = "
256 reg = <0 0x402
257 };
258
259 watchdog@40310000 {
260 compatible = "
261 reg = <0 0x403
262 interrupts = <
263 timeout-sec =
264 clocks = <&aon
265 <&aon
266 clock-names =
267 };
268 };
269
270 agcp {
271 compatible = "simple-b
272 #address-cells = <2>;
273 #size-cells = <2>;
274 ranges;
275
276 agcp_dma: dma-controll
277 compatible = "
278 reg = <0 0x415
279 #dma-cells = <
280 /* For backwar
281 #dma-channels
282 dma-channels =
283 clocks = <&agc
284 <&agc
285 clock-names =
286 };
287 };
288 };
289
290 ext_32k: ext_32k {
291 compatible = "fixed-clock";
292 #clock-cells = <0>;
293 clock-frequency = <32768>;
294 clock-output-names = "ext-32k"
295 };
296
297 ext_26m: ext_26m {
298 compatible = "fixed-clock";
299 #clock-cells = <0>;
300 clock-frequency = <26000000>;
301 clock-output-names = "ext-26m"
302 };
303
304 ext_rco_100m: ext_rco_100m {
305 compatible = "fixed-clock";
306 #clock-cells = <0>;
307 clock-frequency = <100000000>;
308 clock-output-names = "ext-rco-
309 };
310
311 clk_l0_409m6: clk_l0_409m6 {
312 compatible = "fixed-clock";
313 #clock-cells = <0>;
314 clock-frequency = <409600000>;
315 clock-output-names = "ext-409m
316 };
317 };
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