1 // SPDX-License-Identifier: (GPL-2.0-or-later
2 /*
3 * Copyright (C) STMicroelectronics 2023 - All
4 * Author: Alexandre Torgue <alexandre.torgue@f
5 */
6 #include <dt-bindings/clock/st,stm32mp25-rcc.h
7 #include <dt-bindings/interrupt-controller/arm
8 #include <dt-bindings/reset/st,stm32mp25-rcc.h
9 #include <dt-bindings/regulator/st,stm32mp25-r
10
11 / {
12 #address-cells = <2>;
13 #size-cells = <2>;
14
15 cpus {
16 #address-cells = <1>;
17 #size-cells = <0>;
18
19 cpu0: cpu@0 {
20 compatible = "arm,cort
21 device_type = "cpu";
22 reg = <0>;
23 enable-method = "psci"
24 power-domains = <&CPU_
25 power-domain-names = "
26 };
27 };
28
29 arm-pmu {
30 compatible = "arm,cortex-a35-p
31 interrupts = <GIC_SPI 368 IRQ_
32 interrupt-affinity = <&cpu0>;
33 interrupt-parent = <&intc>;
34 };
35
36 arm_wdt: watchdog {
37 compatible = "arm,smc-wdt";
38 arm,smc-id = <0xb200005a>;
39 status = "disabled";
40 };
41
42 clocks {
43 clk_dsi_txbyte: txbyteclk {
44 #clock-cells = <0>;
45 compatible = "fixed-cl
46 clock-frequency = <0>;
47 };
48
49 clk_rcbsec: clk-rcbsec {
50 #clock-cells = <0>;
51 compatible = "fixed-cl
52 clock-frequency = <640
53 };
54 };
55
56 firmware {
57 optee: optee {
58 compatible = "linaro,o
59 method = "smc";
60 interrupt-parent = <&i
61 interrupts = <GIC_PPI
62 };
63
64 scmi {
65 compatible = "linaro,s
66 #address-cells = <1>;
67 #size-cells = <0>;
68 linaro,optee-channel-i
69
70 scmi_clk: protocol@14
71 reg = <0x14>;
72 #clock-cells =
73 };
74
75 scmi_reset: protocol@1
76 reg = <0x16>;
77 #reset-cells =
78 };
79
80 scmi_voltd: protocol@1
81 reg = <0x17>;
82
83 scmi_regu: reg
84 #addre
85 #size-
86
87 scmi_v
88
89
90 };
91 scmi_v
92
93
94 };
95 scmi_v
96
97
98 };
99 scmi_v
100
101
102 };
103 scmi_v
104
105
106 };
107 scmi_v
108
109
110 };
111 };
112 };
113 };
114 };
115
116 intc: interrupt-controller@4ac00000 {
117 compatible = "arm,cortex-a7-gi
118 #interrupt-cells = <3>;
119 #address-cells = <1>;
120 interrupt-controller;
121 reg = <0x0 0x4ac10000 0x0 0x10
122 <0x0 0x4ac20000 0x0 0x20
123 <0x0 0x4ac40000 0x0 0x20
124 <0x0 0x4ac60000 0x0 0x20
125 };
126
127 psci {
128 compatible = "arm,psci-1.0";
129 method = "smc";
130
131 CPU_PD0: power-domain-cpu0 {
132 #power-domain-cells =
133 power-domains = <&CLUS
134 };
135
136 CLUSTER_PD: power-domain-clust
137 #power-domain-cells =
138 power-domains = <&RET_
139 };
140
141 RET_PD: power-domain-retention
142 #power-domain-cells =
143 };
144 };
145
146 timer {
147 compatible = "arm,armv8-timer"
148 interrupt-parent = <&intc>;
149 interrupts = <GIC_PPI 13 (GIC_
150 <GIC_PPI 14 (GIC_
151 <GIC_PPI 11 (GIC_
152 <GIC_PPI 10 (GIC_
153 always-on;
154 };
155
156 soc@0 {
157 compatible = "simple-bus";
158 #address-cells = <1>;
159 #size-cells = <1>;
160 interrupt-parent = <&intc>;
161 ranges = <0x0 0x0 0x0 0x800000
162
163 hpdma: dma-controller@40400000
164 compatible = "st,stm32
165 reg = <0x40400000 0x10
166 interrupts = <GIC_SPI
167 <GIC_SPI
168 <GIC_SPI
169 <GIC_SPI
170 <GIC_SPI
171 <GIC_SPI
172 <GIC_SPI
173 <GIC_SPI
174 <GIC_SPI
175 <GIC_SPI
176 <GIC_SPI
177 <GIC_SPI
178 <GIC_SPI
179 <GIC_SPI
180 <GIC_SPI
181 <GIC_SPI
182 clocks = <&scmi_clk CK
183 #dma-cells = <3>;
184 };
185
186 hpdma2: dma-controller@4041000
187 compatible = "st,stm32
188 reg = <0x40410000 0x10
189 interrupts = <GIC_SPI
190 <GIC_SPI
191 <GIC_SPI
192 <GIC_SPI
193 <GIC_SPI
194 <GIC_SPI
195 <GIC_SPI
196 <GIC_SPI
197 <GIC_SPI
198 <GIC_SPI
199 <GIC_SPI
200 <GIC_SPI
201 <GIC_SPI
202 <GIC_SPI
203 <GIC_SPI
204 <GIC_SPI
205 clocks = <&scmi_clk CK
206 #dma-cells = <3>;
207 };
208
209 hpdma3: dma-controller@4042000
210 compatible = "st,stm32
211 reg = <0x40420000 0x10
212 interrupts = <GIC_SPI
213 <GIC_SPI
214 <GIC_SPI
215 <GIC_SPI
216 <GIC_SPI
217 <GIC_SPI
218 <GIC_SPI
219 <GIC_SPI
220 <GIC_SPI
221 <GIC_SPI
222 <GIC_SPI
223 <GIC_SPI
224 <GIC_SPI
225 <GIC_SPI
226 <GIC_SPI
227 <GIC_SPI
228 clocks = <&scmi_clk CK
229 #dma-cells = <3>;
230 };
231
232 rifsc: bus@42080000 {
233 compatible = "st,stm32
234 reg = <0x42080000 0x10
235 #address-cells = <1>;
236 #size-cells = <1>;
237 #access-controller-cel
238 ranges;
239
240 spi2: spi@400b0000 {
241 #address-cells
242 #size-cells =
243 compatible = "
244 reg = <0x400b0
245 interrupts = <
246 clocks = <&rcc
247 resets = <&rcc
248 access-control
249 status = "disa
250 };
251
252 spi3: spi@400c0000 {
253 #address-cells
254 #size-cells =
255 compatible = "
256 reg = <0x400c0
257 interrupts = <
258 clocks = <&rcc
259 resets = <&rcc
260 access-control
261 status = "disa
262 };
263
264 usart2: serial@400e000
265 compatible = "
266 reg = <0x400e0
267 interrupts = <
268 clocks = <&rcc
269 access-control
270 status = "disa
271 };
272
273 usart3: serial@400f000
274 compatible = "
275 reg = <0x400f0
276 interrupts = <
277 clocks = <&rcc
278 access-control
279 status = "disa
280 };
281
282 uart4: serial@40100000
283 compatible = "
284 reg = <0x40100
285 interrupts = <
286 clocks = <&rcc
287 access-control
288 status = "disa
289 };
290
291 uart5: serial@40110000
292 compatible = "
293 reg = <0x40110
294 interrupts = <
295 clocks = <&rcc
296 access-control
297 status = "disa
298 };
299
300 i2c1: i2c@40120000 {
301 compatible = "
302 reg = <0x40120
303 interrupt-name
304 interrupts = <
305 clocks = <&rcc
306 resets = <&rcc
307 #address-cells
308 #size-cells =
309 access-control
310 status = "disa
311 };
312
313 i2c2: i2c@40130000 {
314 compatible = "
315 reg = <0x40130
316 interrupt-name
317 interrupts = <
318 clocks = <&rcc
319 resets = <&rcc
320 #address-cells
321 #size-cells =
322 access-control
323 status = "disa
324 };
325
326 i2c3: i2c@40140000 {
327 compatible = "
328 reg = <0x40140
329 interrupt-name
330 interrupts = <
331 clocks = <&rcc
332 resets = <&rcc
333 #address-cells
334 #size-cells =
335 access-control
336 status = "disa
337 };
338
339 i2c4: i2c@40150000 {
340 compatible = "
341 reg = <0x40150
342 interrupt-name
343 interrupts = <
344 clocks = <&rcc
345 resets = <&rcc
346 #address-cells
347 #size-cells =
348 access-control
349 status = "disa
350 };
351
352 i2c5: i2c@40160000 {
353 compatible = "
354 reg = <0x40160
355 interrupt-name
356 interrupts = <
357 clocks = <&rcc
358 resets = <&rcc
359 #address-cells
360 #size-cells =
361 access-control
362 status = "disa
363 };
364
365 i2c6: i2c@40170000 {
366 compatible = "
367 reg = <0x40170
368 interrupt-name
369 interrupts = <
370 clocks = <&rcc
371 resets = <&rcc
372 #address-cells
373 #size-cells =
374 access-control
375 status = "disa
376 };
377
378 i2c7: i2c@40180000 {
379 compatible = "
380 reg = <0x40180
381 interrupt-name
382 interrupts = <
383 clocks = <&rcc
384 resets = <&rcc
385 #address-cells
386 #size-cells =
387 access-control
388 status = "disa
389 };
390
391 usart6: serial@4022000
392 compatible = "
393 reg = <0x40220
394 interrupts = <
395 clocks = <&rcc
396 access-control
397 status = "disa
398 };
399
400 spi1: spi@40230000 {
401 #address-cells
402 #size-cells =
403 compatible = "
404 reg = <0x40230
405 interrupts = <
406 clocks = <&rcc
407 resets = <&rcc
408 access-control
409 status = "disa
410 };
411
412 spi4: spi@40240000 {
413 #address-cells
414 #size-cells =
415 compatible = "
416 reg = <0x40240
417 interrupts = <
418 clocks = <&rcc
419 resets = <&rcc
420 access-control
421 status = "disa
422 };
423
424 spi5: spi@40280000 {
425 #address-cells
426 #size-cells =
427 compatible = "
428 reg = <0x40280
429 interrupts = <
430 clocks = <&rcc
431 resets = <&rcc
432 access-control
433 status = "disa
434 };
435
436 uart9: serial@402c0000
437 compatible = "
438 reg = <0x402c0
439 interrupts = <
440 clocks = <&rcc
441 access-control
442 status = "disa
443 };
444
445 usart1: serial@4033000
446 compatible = "
447 reg = <0x40330
448 interrupts = <
449 clocks = <&rcc
450 access-control
451 status = "disa
452 };
453
454 spi6: spi@40350000 {
455 #address-cells
456 #size-cells =
457 compatible = "
458 reg = <0x40350
459 interrupts = <
460 clocks = <&rcc
461 resets = <&rcc
462 access-control
463 status = "disa
464 };
465
466 spi7: spi@40360000 {
467 #address-cells
468 #size-cells =
469 compatible = "
470 reg = <0x40360
471 interrupts = <
472 clocks = <&rcc
473 resets = <&rcc
474 access-control
475 status = "disa
476 };
477
478 uart7: serial@40370000
479 compatible = "
480 reg = <0x40370
481 interrupts = <
482 clocks = <&rcc
483 access-control
484 status = "disa
485 };
486
487 uart8: serial@40380000
488 compatible = "
489 reg = <0x40380
490 interrupts = <
491 clocks = <&rcc
492 access-control
493 status = "disa
494 };
495
496 spi8: spi@46020000 {
497 #address-cells
498 #size-cells =
499 compatible = "
500 reg = <0x46020
501 interrupts = <
502 clocks = <&rcc
503 resets = <&rcc
504 access-control
505 status = "disa
506 };
507
508 i2c8: i2c@46040000 {
509 compatible = "
510 reg = <0x46040
511 interrupt-name
512 interrupts = <
513 clocks = <&rcc
514 resets = <&rcc
515 #address-cells
516 #size-cells =
517 access-control
518 status = "disa
519 };
520
521 sdmmc1: mmc@48220000 {
522 compatible = "
523 arm,primecell-
524 reg = <0x48220
525 interrupts = <
526 clocks = <&rcc
527 clock-names =
528 resets = <&rcc
529 cap-sd-highspe
530 cap-mmc-highsp
531 max-frequency
532 access-control
533 status = "disa
534 };
535
536 ethernet1: ethernet@48
537 compatible = "
538 reg = <0x482c0
539 reg-names = "s
540 interrupts-ext
541 interrupt-name
542 clock-names =
543
544
545
546
547
548 clocks = <&rcc
549 <&rcc
550 <&rcc
551 <&rcc
552 <&rcc
553 <&rcc
554 snps,axi-confi
555 snps,mixed-bur
556 snps,mtl-rx-co
557 snps,mtl-tx-co
558 snps,pbl = <2>
559 snps,tso;
560 st,syscon = <&
561 access-control
562 status = "disa
563
564 mtl_rx_setup_1
565 snps,r
566 queue0
567 queue1
568 };
569
570 mtl_tx_setup_1
571 snps,t
572 queue0
573 queue1
574 queue2
575 queue3
576 };
577
578 stmmac_axi_con
579 snps,b
580 snps,r
581 snps,w
582 };
583 };
584 };
585
586 bsec: efuse@44000000 {
587 compatible = "st,stm32
588 reg = <0x44000000 0x10
589 #address-cells = <1>;
590 #size-cells = <1>;
591
592 part_number_otp@24 {
593 reg = <0x24 0x
594 };
595
596 package_otp@1e8 {
597 reg = <0x1e8 0
598 bits = <0 3>;
599 };
600 };
601
602 rcc: clock-controller@44200000
603 compatible = "st,stm32
604 reg = <0x44200000 0x10
605 #clock-cells = <1>;
606 #reset-cells = <1>;
607 clocks = <&scmi_clk CK
608 <&scmi_clk CK_
609 <&scmi_clk CK_
610 <&scmi_clk CK_
611 <&scmi_clk CK_
612 <&scmi_clk CK_
613 <&scmi_clk CK_
614 <&scmi_clk CK_
615 <&scmi_clk CK_
616 <&scmi_clk CK_
617 <&scmi_clk CK_
618 <&scmi_clk CK_
619 <&scmi_clk CK_
620 <&scmi_clk CK_
621 <&scmi_clk CK_
622 <&scmi_clk CK_
623 <&scmi_clk CK_
624 <&scmi_clk CK_
625 <&scmi_clk CK_
626 <&scmi_clk CK_
627 <&scmi_clk CK_
628 <&scmi_clk CK_
629 <&scmi_clk CK_
630 <&scmi_clk CK_
631 <&scmi_clk CK_
632 <&scmi_clk CK_
633 <&scmi_clk CK_
634 <&scmi_clk CK_
635 <&scmi_clk CK_
636 <&scmi_clk CK_
637 <&scmi_clk CK_
638 <&scmi_clk CK_
639 <&scmi_clk CK_
640 <&scmi_clk CK_
641 <&scmi_clk CK_
642 <&scmi_clk CK_
643 <&scmi_clk CK_
644 <&scmi_clk CK_
645 <&scmi_clk CK_
646 <&scmi_clk CK_
647 <&scmi_clk CK_
648 <&scmi_clk CK_
649 <&scmi_clk CK_
650 <&scmi_clk CK_
651 <&scmi_clk CK_
652 <&scmi_clk CK_
653 <&scmi_clk CK_
654 <&scmi_clk CK_
655 <&scmi_clk CK_
656 <&scmi_clk CK_
657 <&scmi_clk CK_
658 <&scmi_clk CK_
659 <&scmi_clk CK_
660 <&scmi_clk CK_
661 <&scmi_clk CK_
662 <&scmi_clk CK_
663 <&scmi_clk CK_
664 <&scmi_clk CK_
665 <&scmi_clk CK_
666 <&scmi_clk CK_
667 <&scmi_clk CK_
668 <&scmi_clk CK_
669 <&scmi_clk CK_
670 <&scmi_clk CK_
671 <&scmi_clk CK_
672 <&scmi_clk CK_
673 <&scmi_clk CK_
674 <&scmi_clk CK_
675 <&scmi_clk CK_
676 <&scmi_clk CK_
677 <&scmi_clk CK_
678 <&scmi_clk CK_
679 <&scmi_clk CK_
680 <&scmi_clk CK_
681 <&scmi_clk CK_
682 <&scmi_clk CK_
683 <&scmi_clk CK_
684 <&scmi_clk CK_
685 <&scmi_clk CK_
686 <&clk_dsi_txby
687 access-control
688 };
689
690 exti1: interrupt-controller@44
691 compatible = "st,stm32
692 interrupt-controller;
693 #interrupt-cells = <2>
694 reg = <0x44220000 0x40
695 interrupts-extended =
696 <&intc GIC_SPI
697 <&intc GIC_SPI
698 <&intc GIC_SPI
699 <&intc GIC_SPI
700 <&intc GIC_SPI
701 <&intc GIC_SPI
702 <&intc GIC_SPI
703 <&intc GIC_SPI
704 <&intc GIC_SPI
705 <&intc GIC_SPI
706 <&intc GIC_SPI
707 <&intc GIC_SPI
708 <&intc GIC_SPI
709 <&intc GIC_SPI
710 <&intc GIC_SPI
711 <&intc GIC_SPI
712 <&intc GIC_SPI
713 <&intc GIC_SPI
714 <&intc GIC_SPI
715 <&intc GIC_SPI
716 <0>,
717 <&intc GIC_SPI
718 <&intc GIC_SPI
719 <&intc GIC_SPI
720 <&intc GIC_SPI
721 <&intc GIC_SPI
722 <&intc GIC_SPI
723 <&intc GIC_SPI
724 <&intc GIC_SPI
725 <&intc GIC_SPI
726 <&intc GIC_SPI
727 <&intc GIC_SPI
728 <&intc GIC_SPI
729 <&intc GIC_SPI
730 <&intc GIC_SPI
731 <0>,
732 <&intc GIC_SPI
733 <&intc GIC_SPI
734 <&intc GIC_SPI
735 <&intc GIC_SPI
736 <&intc GIC_SPI
737 <&intc GIC_SPI
738 <&intc GIC_SPI
739 <&intc GIC_SPI
740 <&intc GIC_SPI
741 <&intc GIC_SPI
742 <&intc GIC_SPI
743 <&intc GIC_SPI
744 <&intc GIC_SPI
745 <&intc GIC_SPI
746 <&intc GIC_SPI
747 <0>,
748 <0>,
749 <0>,
750 <0>,
751 <0>,
752 <0>,
753 <0>,
754 <0>,
755 <&intc GIC_SPI
756 <0>,
757 <&intc GIC_SPI
758 <0>,
759 <0>,
760 <&intc GIC_SPI
761 <0>,
762 <0>,
763 <&intc GIC_SPI
764 <&intc GIC_SPI
765 <0>,
766 <&intc GIC_SPI
767 <0>,
768 <&intc GIC_SPI
769 <&intc GIC_SPI
770 <&intc GIC_SPI
771 <&intc GIC_SPI
772 <&intc GIC_SPI
773 <&intc GIC_SPI
774 <&intc GIC_SPI
775 <&intc GIC_SPI
776 <0>,
777 <0>,
778 <0>,
779 <&intc GIC_SPI
780 <&intc GIC_SPI
781 };
782
783 syscfg: syscon@44230000 {
784 compatible = "st,stm32
785 reg = <0x44230000 0x10
786 };
787
788 pinctrl: pinctrl@44240000 {
789 #address-cells = <1>;
790 #size-cells = <1>;
791 compatible = "st,stm32
792 ranges = <0 0x44240000
793 interrupt-parent = <&e
794 st,syscfg = <&exti1 0x
795 pins-are-numbered;
796
797 gpioa: gpio@44240000 {
798 gpio-controlle
799 #gpio-cells =
800 interrupt-cont
801 #interrupt-cel
802 reg = <0x0 0x4
803 clocks = <&scm
804 st,bank-name =
805 status = "disa
806 };
807
808 gpiob: gpio@44250000 {
809 gpio-controlle
810 #gpio-cells =
811 interrupt-cont
812 #interrupt-cel
813 reg = <0x10000
814 clocks = <&scm
815 st,bank-name =
816 status = "disa
817 };
818
819 gpioc: gpio@44260000 {
820 gpio-controlle
821 #gpio-cells =
822 interrupt-cont
823 #interrupt-cel
824 reg = <0x20000
825 clocks = <&scm
826 st,bank-name =
827 status = "disa
828 };
829
830 gpiod: gpio@44270000 {
831 gpio-controlle
832 #gpio-cells =
833 interrupt-cont
834 #interrupt-cel
835 reg = <0x30000
836 clocks = <&scm
837 st,bank-name =
838 status = "disa
839 };
840
841 gpioe: gpio@44280000 {
842 gpio-controlle
843 #gpio-cells =
844 interrupt-cont
845 #interrupt-cel
846 reg = <0x40000
847 clocks = <&scm
848 st,bank-name =
849 status = "disa
850 };
851
852 gpiof: gpio@44290000 {
853 gpio-controlle
854 #gpio-cells =
855 interrupt-cont
856 #interrupt-cel
857 reg = <0x50000
858 clocks = <&scm
859 st,bank-name =
860 status = "disa
861 };
862
863 gpiog: gpio@442a0000 {
864 gpio-controlle
865 #gpio-cells =
866 interrupt-cont
867 #interrupt-cel
868 reg = <0x60000
869 clocks = <&scm
870 st,bank-name =
871 status = "disa
872 };
873
874 gpioh: gpio@442b0000 {
875 gpio-controlle
876 #gpio-cells =
877 interrupt-cont
878 #interrupt-cel
879 reg = <0x70000
880 clocks = <&scm
881 st,bank-name =
882 status = "disa
883 };
884
885 gpioi: gpio@442c0000 {
886 gpio-controlle
887 #gpio-cells =
888 interrupt-cont
889 #interrupt-cel
890 reg = <0x80000
891 clocks = <&scm
892 st,bank-name =
893 status = "disa
894 };
895
896 gpioj: gpio@442d0000 {
897 gpio-controlle
898 #gpio-cells =
899 interrupt-cont
900 #interrupt-cel
901 reg = <0x90000
902 clocks = <&scm
903 st,bank-name =
904 status = "disa
905 };
906
907 gpiok: gpio@442e0000 {
908 gpio-controlle
909 #gpio-cells =
910 interrupt-cont
911 #interrupt-cel
912 reg = <0xa0000
913 clocks = <&scm
914 st,bank-name =
915 status = "disa
916 };
917 };
918
919 pinctrl_z: pinctrl@46200000 {
920 #address-cells = <1>;
921 #size-cells = <1>;
922 compatible = "st,stm32
923 ranges = <0 0x46200000
924 interrupt-parent = <&e
925 st,syscfg = <&exti1 0x
926 pins-are-numbered;
927
928 gpioz: gpio@46200000 {
929 gpio-controlle
930 #gpio-cells =
931 interrupt-cont
932 #interrupt-cel
933 reg = <0 0x400
934 clocks = <&scm
935 st,bank-name =
936 st,bank-ioport
937 status = "disa
938 };
939
940 };
941
942 exti2: interrupt-controller@46
943 compatible = "st,stm32
944 interrupt-controller;
945 #interrupt-cells = <2>
946 reg = <0x46230000 0x40
947 interrupts-extended =
948 <&intc GIC_SPI
949 <&intc GIC_SPI
950 <&intc GIC_SPI
951 <&intc GIC_SPI
952 <&intc GIC_SPI
953 <&intc GIC_SPI
954 <&intc GIC_SPI
955 <&intc GIC_SPI
956 <&intc GIC_SPI
957 <&intc GIC_SPI
958 <&intc GIC_SPI
959 <&intc GIC_SPI
960 <&intc GIC_SPI
961 <&intc GIC_SPI
962 <&intc GIC_SPI
963 <&intc GIC_SPI
964 <&intc GIC_SPI
965 <&intc GIC_SPI
966 <0>,
967 <0>,
968 <0>,
969 <&intc GIC_SPI
970 <&intc GIC_SPI
971 <0>,
972 <0>,
973 <&intc GIC_SPI
974 <&intc GIC_SPI
975 <&intc GIC_SPI
976 <0>,
977 <&intc GIC_SPI
978 <&intc GIC_SPI
979 <&intc GIC_SPI
980 <0>,
981 <&intc GIC_SPI
982 <&intc GIC_SPI
983 <0>,
984 <0>,
985 <&intc GIC_SPI
986 <0>,
987 <0>,
988 <&intc GIC_SPI
989 <0>,
990 <0>,
991 <&intc GIC_SPI
992 <0>,
993 <0>,
994 <&intc GIC_SPI
995 <0>,
996 <&intc GIC_SPI
997 <&intc GIC_SPI
998 <&intc GIC_SPI
999 <&intc GIC_SPI
1000 <&intc GIC_SP
1001 <&intc GIC_SP
1002 <0>,
1003 <0>,
1004 <0>,
1005 <0>,
1006 <0>,
1007 <0>,
1008 <0>,
1009 <&intc GIC_SP
1010 <&intc GIC_SP
1011 <0>,
1012 <&intc GIC_SP
1013 <&intc GIC_SP
1014 <&intc GIC_SP
1015 <&intc GIC_SP
1016 <0>,
1017 <0>,
1018 <&intc GIC_SP
1019 };
1020 };
1021 };
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