1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2023 Josua Mayer <josua@solid-
4 *
5 */
6
7 #include <dt-bindings/net/ti-dp83869.h>
8
9 / {
10 model = "SolidRun AM642 SoM";
11 compatible = "solidrun,am642-sr-som",
12
13 aliases {
14 ethernet0 = &cpsw_port1;
15 ethernet1 = &icssg1_emac0;
16 ethernet2 = &icssg1_emac1;
17 mmc0 = &sdhci0;
18 mmc1 = &sdhci1;
19 serial2 = &main_uart0;
20 };
21
22 chosen {
23 /* SoC default UART console */
24 stdout-path = "serial2:115200n
25 };
26
27 /* PRU Ethernet Controller */
28 ethernet {
29 compatible = "ti,am642-icssg-p
30 pinctrl-names = "default";
31 pinctrl-0 = <&pru_rgmii1_defau
32
33 sram = <&oc_sram>;
34 ti,prus = <&pru1_0>, <&rtu1_0>
35 firmware-name = "ti-pruss/am65
36 "ti-pruss/am65
37 "ti-pruss/am65
38 "ti-pruss/am65
39 "ti-pruss/am65
40 "ti-pruss/am65
41
42 /* configure internal pinmux f
43 ti,pruss-gp-mux-sel = <2>, <2>
44
45 ti,mii-g-rt = <&icssg1_mii_g_r
46 ti,mii-rt = <&icssg1_mii_rt>;
47 ti,iep = <&icssg1_iep0>, <&ics
48
49 /*
50 * Configure icssg interrupt c
51 * interrupts 8/9 via channels
52 *
53 * For details see interrupt c
54 * Documentation/devicetree/bi
55 */
56 interrupt-parent = <&icssg1_in
57 interrupts = <24 0 2>, <25 1 3
58 interrupt-names = "tx_ts0", "t
59
60 dmas = <&main_pktdma 0xc200 15
61 <&main_pktdma 0xc201 15
62 <&main_pktdma 0xc202 15
63 <&main_pktdma 0xc203 15
64 <&main_pktdma 0xc204 15
65 <&main_pktdma 0xc205 15
66 <&main_pktdma 0xc206 15
67 <&main_pktdma 0xc207 15
68 <&main_pktdma 0x4200 15
69 <&main_pktdma 0x4201 15
70 dma-names = "tx0-0", "tx0-1",
71 "tx1-0", "tx1-1",
72 "rx0", "rx1";
73
74 ethernet-ports {
75 #address-cells = <1>;
76 #size-cells = <0>;
77
78 icssg1_emac0: port@0 {
79 reg = <0>;
80 ti,syscon-rgmi
81 /* Filled in b
82 local-mac-addr
83 phy-handle = <
84 phy-mode = "rg
85 };
86
87 icssg1_emac1: port@1 {
88 reg = <1>;
89 ti,syscon-rgmi
90 /* Filled in b
91 local-mac-addr
92 phy-handle = <
93 phy-mode = "rg
94 };
95 };
96 };
97
98 /* DDR16SS0:
99 * - Bank 1 @ 0x080000000-0x0FFFFFFFF:
100 * - Bank 2 @ 0x880000000-0x9FFFFFFFF:
101 */
102 memory@80000000 {
103 reg = <0x00000000 0x80000000 0
104 <0x00000008 0x80000000 0
105 device_type = "memory";
106 };
107
108 reserved-memory {
109 #address-cells = <2>;
110 #size-cells = <2>;
111 ranges;
112
113 secure_ddr: optee@9e800000 {
114 reg = <0x00 0x9e800000
115 no-map;
116 };
117
118 main_r5fss0_core0_dma_memory_r
119 compatible = "shared-d
120 reg = <0x00 0xa0000000
121 no-map;
122 };
123
124 main_r5fss0_core0_memory_regio
125 compatible = "shared-d
126 reg = <0x00 0xa0100000
127 no-map;
128 };
129
130 main_r5fss0_core1_dma_memory_r
131 compatible = "shared-d
132 reg = <0x00 0xa1000000
133 no-map;
134 };
135
136 main_r5fss0_core1_memory_regio
137 compatible = "shared-d
138 reg = <0x00 0xa1100000
139 no-map;
140 };
141
142 main_r5fss1_core0_dma_memory_r
143 compatible = "shared-d
144 reg = <0x00 0xa2000000
145 no-map;
146 };
147
148 main_r5fss1_core0_memory_regio
149 compatible = "shared-d
150 reg = <0x00 0xa2100000
151 no-map;
152 };
153
154 main_r5fss1_core1_dma_memory_r
155 compatible = "shared-d
156 reg = <0x00 0xa3000000
157 no-map;
158 };
159
160 main_r5fss1_core1_memory_regio
161 compatible = "shared-d
162 reg = <0x00 0xa3100000
163 no-map;
164 };
165 };
166
167 vdd_mmc0: regulator-vdd-mmc0 {
168 compatible = "regulator-fixed"
169 regulator-name = "vdd-mmc0";
170 regulator-min-microvolt = <180
171 regulator-max-microvolt = <180
172 regulator-always-on;
173 regulator-boot-on;
174 };
175 };
176
177 &cpsw3g {
178 pinctrl-names = "default";
179 pinctrl-0 = <&rgmii1_default_pins>;
180 };
181
182 &cpsw3g_mdio {
183 pinctrl-names = "default";
184 pinctrl-0 = <&mdio0_default_pins>;
185 status = "okay";
186
187 ethernet_phy0: ethernet-phy@0 {
188 compatible = "ethernet-phy-id2
189 reg = <0>;
190 pinctrl-names = "default";
191 pinctrl-0 = <ðernet_phy0_de
192 ti,clk-output-sel = <DP83869_C
193 ti,op-mode = <DP83869_RGMII_CO
194 /*
195 * Disable interrupts because
196 *
197 * interrupt-parent = <&main_g
198 * interrupts = <70 IRQ_TYPE_L
199 */
200 /*
201 * Disable HW Reset because cl
202 *
203 * reset-gpios = <&main_gpio0
204 * reset-assert-us = <1>;
205 * reset-deassert-us = <30>;
206 */
207 };
208 };
209
210 &cpsw_port1 {
211 phy-mode = "rgmii-id";
212 phy-handle = <ðernet_phy0>;
213 };
214
215 &cpsw_port2 {
216 status = "disabled";
217 };
218
219 &icssg1_mdio {
220 pinctrl-names = "default";
221 pinctrl-0 = <&pru1_mdio0_default_pins>
222 status = "okay";
223
224 ethernet_phy1: ethernet-phy@3 {
225 compatible = "ethernet-phy-id2
226 reg = <3>;
227 pinctrl-names = "default";
228 pinctrl-0 = <ðernet_phy1_de
229 ti,clk-output-sel = <DP83869_C
230 ti,op-mode = <DP83869_RGMII_CO
231 /*
232 * Disable interrupts because
233 *
234 * interrupt-parent = <&main_g
235 * interrupts = <70 IRQ_TYPE_L
236 */
237 /*
238 * Disable HW Reset because cl
239 *
240 * reset-gpios = <&main_gpio0
241 * reset-assert-us = <1>;
242 * reset-deassert-us = <30>;
243 */
244 };
245
246 ethernet_phy2: ethernet-phy@f {
247 compatible = "ethernet-phy-id2
248 reg = <0xf>;
249 pinctrl-names = "default";
250 pinctrl-0 = <ðernet_phy2_de
251 ti,op-mode = <DP83869_RGMII_CO
252 /*
253 * Disable interrupts because
254 *
255 * interrupt-parent = <&main_g
256 * interrupts = <70 IRQ_TYPE_L
257 */
258 /*
259 * Disable HW Reset because cl
260 *
261 * reset-gpios = <&main_gpio0
262 * reset-assert-us = <1>;
263 * reset-deassert-us = <30>;
264 */
265 };
266 };
267
268 &mailbox0_cluster2 {
269 status = "okay";
270
271 mbox_main_r5fss0_core0: mbox-main-r5fs
272 ti,mbox-rx = <0 0 2>;
273 ti,mbox-tx = <1 0 2>;
274 };
275
276 mbox_main_r5fss0_core1: mbox-main-r5fs
277 ti,mbox-rx = <2 0 2>;
278 ti,mbox-tx = <3 0 2>;
279 };
280 };
281
282 &mailbox0_cluster4 {
283 status = "okay";
284
285 mbox_main_r5fss1_core0: mbox-main-r5fs
286 ti,mbox-rx = <0 0 2>;
287 ti,mbox-tx = <1 0 2>;
288 };
289
290 mbox_main_r5fss1_core1: mbox-main-r5fs
291 ti,mbox-rx = <2 0 2>;
292 ti,mbox-tx = <3 0 2>;
293 };
294 };
295
296 &main_i2c0 {
297 pinctrl-names = "default";
298 pinctrl-0 = <&main_i2c0_default_pins>;
299 status = "okay";
300
301 som_eeprom: eeprom@50 {
302 compatible = "atmel,24c01";
303 reg = <0x50>;
304 pagesize = <8>;
305 };
306 };
307
308 &main_pmx0 {
309 /* hog global functions */
310 pinctrl-names = "default";
311 pinctrl-0 = <ðernet_phy_default_pin
312
313 ethernet_phy_default_pins: ethernet-ph
314 pinctrl-single,pins = <
315 /* interrupt / power-d
316 AM64X_IOPAD(0x0278, PI
317 >;
318 };
319
320 ethernet_phy0_default_pins: ethernet-p
321 pinctrl-single,pins = <
322 /* reset */
323 AM64X_IOPAD(0x0154, PI
324 /* reference clock */
325 AM64X_IOPAD(0x0274, PI
326 >;
327 };
328
329 ethernet_phy1_default_pins: ethernet-p
330 pinctrl-single,pins = <
331 /* reset */
332 AM64X_IOPAD(0x0150, PI
333 /* led0, external pull
334 AM64X_IOPAD(0x0128, PI
335 /* led1/rxer */
336 AM64X_IOPAD(0x011c, PI
337 >;
338 };
339
340 ethernet_phy2_default_pins: ethernet-p
341 pinctrl-single,pins = <
342 /* reset */
343 AM64X_IOPAD(0x00d4, PI
344 /* led0, external pull
345 AM64X_IOPAD(0x00d8, PI
346 /* led1/rxer */
347 AM64X_IOPAD(0x00cc, PI
348 >;
349 };
350
351 main_i2c0_default_pins: main-i2c0-defa
352 pinctrl-single,pins = <
353 /* external pull-up on
354 AM64X_IOPAD(0x0260, PI
355 AM64X_IOPAD(0x0264, PI
356 >;
357 };
358
359 /*
360 * main_mmc0_default_pins: main-mmc0-d
361 *
362 * MMC0_CMD: no padconfig
363 * MMC0_CLK: no padconfig, external pu
364 * MMC0_DAT0: no padconfig
365 * MMC0_DAT1: no padconfig
366 * MMC0_DAT2: no padconfig
367 * MMC0_DAT3: no padconfig
368 * MMC0_DAT4: no padconfig
369 * MMC0_DAT5: no padconfig
370 * MMC0_DAT6: no padconfig
371 * MMC0_DAT7: no padconfig
372 * MMC0_DS: no padconfig, external pul
373 */
374
375 main_mmc1_default_pins: main-mmc1-defa
376 pinctrl-single,pins = <
377 AM64X_IOPAD(0x0294, PI
378 AM64X_IOPAD(0x028c, PI
379 AM64X_IOPAD(0x0288, PI
380 AM64X_IOPAD(0x0284, PI
381 AM64X_IOPAD(0x0280, PI
382 AM64X_IOPAD(0x027c, PI
383 /* external pull-down
384 AM64X_IOPAD(0x0298, PI
385 AM64X_IOPAD(0x0290, PI
386 >;
387 };
388
389 main_uart0_default_pins: main-uart0-de
390 pinctrl-single,pins = <
391 AM64X_IOPAD(0x0230, PI
392 AM64X_IOPAD(0x0234, PI
393 >;
394 };
395
396 mdio0_default_pins: mdio0-default-pins
397 pinctrl-single,pins = <
398 AM64X_IOPAD(0x01fc, PI
399 AM64X_IOPAD(0x01f8, PI
400 >;
401 };
402
403 ospi0_default_pins: ospi0-default-pins
404 pinctrl-single,pins = <
405 /* external pull-down
406 AM64X_IOPAD(0x0000, PI
407 AM64X_IOPAD(0x0008, PI
408 /* external pull-up on
409 AM64X_IOPAD(0x002c, PI
410 AM64X_IOPAD(0x000c, PI
411 AM64X_IOPAD(0x0010, PI
412 AM64X_IOPAD(0x0014, PI
413 AM64X_IOPAD(0x0018, PI
414 AM64X_IOPAD(0x001c, PI
415 AM64X_IOPAD(0x0020, PI
416 AM64X_IOPAD(0x0024, PI
417 AM64X_IOPAD(0x0028, PI
418 >;
419 };
420
421 ospi0_flash0_default_pins: ospi0-flash
422 pinctrl-single,pins = <
423 AM64X_IOPAD(0x0034, PI
424 AM64X_IOPAD(0x0038, PI
425 >;
426 };
427
428 pru1_mdio0_default_pins: pru1-mdio0-de
429 pinctrl-single,pins = <
430 AM64X_IOPAD(0x015c, PI
431 AM64X_IOPAD(0x0158, PI
432 >;
433 };
434
435 pru_rgmii1_default_pins: pru-rgmii1-de
436 pinctrl-single,pins = <
437 AM64X_IOPAD(0x00b8, PI
438 AM64X_IOPAD(0x00bc, PI
439 AM64X_IOPAD(0x00c0, PI
440 AM64X_IOPAD(0x00c4, PI
441 AM64X_IOPAD(0x00d0, PI
442 AM64X_IOPAD(0x00c8, PI
443 AM64X_IOPAD(0x00e4, PI
444 AM64X_IOPAD(0x00e8, PI
445 AM64X_IOPAD(0x00ec, PI
446 AM64X_IOPAD(0x00f0, PI
447 AM64X_IOPAD(0x00f8, PI
448 AM64X_IOPAD(0x00f4, PI
449 >;
450 };
451
452 pru_rgmii2_default_pins: pru-rgmii2-de
453 pinctrl-single,pins = <
454 AM64X_IOPAD(0x0108, PI
455 AM64X_IOPAD(0x010c, PI
456 AM64X_IOPAD(0x0110, PI
457 AM64X_IOPAD(0x0114, PI
458 AM64X_IOPAD(0x0120, PI
459 AM64X_IOPAD(0x0118, PI
460 AM64X_IOPAD(0x0134, PI
461 AM64X_IOPAD(0x0138, PI
462 AM64X_IOPAD(0x013c, PI
463 AM64X_IOPAD(0x0140, PI
464 AM64X_IOPAD(0x0148, PI
465 AM64X_IOPAD(0x0144, PI
466 >;
467 };
468
469 rgmii1_default_pins: rgmii1-default-pi
470 pinctrl-single,pins = <
471 AM64X_IOPAD(0x01cc, PI
472 AM64X_IOPAD(0x01d4, PI
473 AM64X_IOPAD(0x01d8, PI
474 AM64X_IOPAD(0x01f4, PI
475 AM64X_IOPAD(0x0188, PI
476 AM64X_IOPAD(0x0184, PI
477 AM64X_IOPAD(0x0124, PI
478 AM64X_IOPAD(0x012c, PI
479 AM64X_IOPAD(0x0130, PI
480 AM64X_IOPAD(0x014c, PI
481 AM64X_IOPAD(0x00e0, PI
482 AM64X_IOPAD(0x00dc, PI
483 >;
484 };
485
486 usb0_default_pins: usb0-default-pins {
487 pinctrl-single,pins = <
488 AM64X_IOPAD(0x02a8, PI
489 >;
490 };
491 };
492
493 &main_r5fss0_core0 {
494 mboxes = <&mailbox0_cluster2 &mbox_mai
495 memory-region = <&main_r5fss0_core0_dm
496 <&main_r5fss0_core0_me
497 };
498
499 &main_r5fss0_core1 {
500 mboxes = <&mailbox0_cluster2 &mbox_mai
501 memory-region = <&main_r5fss0_core1_dm
502 <&main_r5fss0_core1_me
503 };
504
505 &main_r5fss1_core0 {
506 mboxes = <&mailbox0_cluster4 &mbox_mai
507 memory-region = <&main_r5fss1_core0_dm
508 <&main_r5fss1_core0_me
509 };
510
511 &main_r5fss1_core1 {
512 mboxes = <&mailbox0_cluster4 &mbox_mai
513 memory-region = <&main_r5fss1_core1_dm
514 <&main_r5fss1_core1_me
515 };
516
517 /* SoC default UART console */
518 &main_uart0 {
519 pinctrl-names = "default";
520 pinctrl-0 = <&main_uart0_default_pins>
521 status = "okay";
522 };
523
524 &ospi0 {
525 pinctrl-names = "default";
526 pinctrl-0 = <&ospi0_default_pins>;
527 num-cs = <1>;
528 status = "okay";
529
530 flash@0 {
531 compatible = "jedec,spi-nor";
532 reg = <0>;
533 pinctrl-names = "default";
534 pinctrl-0 = <&ospi0_flash0_def
535 spi-tx-bus-width = <8>;
536 spi-rx-bus-width = <8>;
537 spi-max-frequency = <200000000
538 cdns,tshsl-ns = <50>;
539 cdns,tsd2d-ns = <50>;
540 cdns,tchsh-ns = <4>;
541 cdns,tslch-ns = <4>;
542 cdns,read-delay = <0>;
543 interrupt-parent = <&main_gpio
544 interrupts = <14 IRQ_TYPE_LEVE
545 reset-gpios = <&main_gpio0 13
546 };
547 };
548
549 &sdhci0 {
550 /* mmc0 pins have no padconfig */
551 bus-width = <8>;
552 ti,driver-strength-ohm = <50>;
553 disable-wp;
554 non-removable;
555 cap-mmc-hw-reset;
556 no-sd;
557 /*
558 * MMC controller supports switching b
559 * However MMC0 (unlike MMC1) does not
560 * Explicitly link a regulator node fo
561 * voltages are actually usable.
562 */
563 vqmmc-supply = <&vdd_mmc0>;
564 status = "okay";
565 };
566
567 /*
568 * microSD is on carrier - however since SoC c
569 * configure it just in case.
570 */
571 &sdhci1 {
572 pinctrl-names = "default";
573 pinctrl-0 = <&main_mmc1_default_pins>;
574 bus-width = <4>;
575 ti,driver-strength-ohm = <50>;
576 disable-wp;
577 status = "okay";
578 };
579
580 /*
581 * USB settings are a carrier choice - however
582 * configure as USB-2.0 OTG here, keeping USB-
583 */
584 &usb0 {
585 pinctrl-names = "default";
586 pinctrl-0 = <&usb0_default_pins>;
587 dr_mode = "otg";
588 maximum-speed = "high-speed";
589 };
590
591 &usbss0 {
592 ti,vbus-divider;
593 ti,usb2-only;
594 };
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