1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2023 Josua Mayer <josua@solid-
4 *
5 */
6
7 #include <dt-bindings/net/ti-dp83869.h>
8
9 / {
10 model = "SolidRun AM642 SoM";
11 compatible = "solidrun,am642-sr-som",
12
13 aliases {
14 ethernet0 = &cpsw_port1;
15 ethernet1 = &icssg1_emac0;
16 ethernet2 = &icssg1_emac1;
17 mmc0 = &sdhci0;
18 mmc1 = &sdhci1;
19 serial2 = &main_uart0;
20 };
21
22 chosen {
23 /* SoC default UART console */
24 stdout-path = "serial2:115200n
25 };
26
27 /* PRU Ethernet Controller */
28 ethernet {
29 compatible = "ti,am642-icssg-p
30 pinctrl-names = "default";
31 pinctrl-0 = <&pru_rgmii1_defau
32
33 sram = <&oc_sram>;
34 ti,prus = <&pru1_0>, <&rtu1_0>
35 firmware-name = "ti-pruss/am65
36 "ti-pruss/am65
37 "ti-pruss/am65
38 "ti-pruss/am65
39 "ti-pruss/am65
40 "ti-pruss/am65
41
42 /* configure internal pinmux f
43 ti,pruss-gp-mux-sel = <2>, <2>
44
45 ti,mii-g-rt = <&icssg1_mii_g_r
46 ti,mii-rt = <&icssg1_mii_rt>;
47 ti,iep = <&icssg1_iep0>, <&ics
48
49 /*
50 * Configure icssg interrupt c
51 * interrupts 8/9 via channels
52 *
53 * For details see interrupt c
54 * Documentation/devicetree/bi
55 */
56 interrupt-parent = <&icssg1_in
57 interrupts = <24 0 2>, <25 1 3
58 interrupt-names = "tx_ts0", "t
59
60 dmas = <&main_pktdma 0xc200 15
61 <&main_pktdma 0xc201 15
62 <&main_pktdma 0xc202 15
63 <&main_pktdma 0xc203 15
64 <&main_pktdma 0xc204 15
65 <&main_pktdma 0xc205 15
66 <&main_pktdma 0xc206 15
67 <&main_pktdma 0xc207 15
68 <&main_pktdma 0x4200 15
69 <&main_pktdma 0x4201 15
70 dma-names = "tx0-0", "tx0-1",
71 "tx1-0", "tx1-1",
72 "rx0", "rx1";
73
74 ethernet-ports {
75 #address-cells = <1>;
76 #size-cells = <0>;
77
78 icssg1_emac0: port@0 {
79 reg = <0>;
80 ti,syscon-rgmi
81 /* Filled in b
82 local-mac-addr
83 phy-handle = <
84 phy-mode = "rg
85 };
86
87 icssg1_emac1: port@1 {
88 reg = <1>;
89 ti,syscon-rgmi
90 /* Filled in b
91 local-mac-addr
92 phy-handle = <
93 phy-mode = "rg
94 };
95 };
96 };
97
98 /* DDR16SS0:
99 * - Bank 1 @ 0x080000000-0x0FFFFFFFF:
100 * - Bank 2 @ 0x880000000-0x9FFFFFFFF:
101 */
102 memory@80000000 {
103 reg = <0x00000000 0x80000000 0
104 <0x00000008 0x80000000 0
105 device_type = "memory";
106 };
107
108 reserved-memory {
109 #address-cells = <2>;
110 #size-cells = <2>;
111 ranges;
112
113 secure_ddr: optee@9e800000 {
114 reg = <0x00 0x9e800000
115 no-map;
116 };
117
118 main_r5fss0_core0_dma_memory_r
119 compatible = "shared-d
120 reg = <0x00 0xa0000000
121 no-map;
122 };
123
124 main_r5fss0_core0_memory_regio
125 compatible = "shared-d
126 reg = <0x00 0xa0100000
127 no-map;
128 };
129
130 main_r5fss0_core1_dma_memory_r
131 compatible = "shared-d
132 reg = <0x00 0xa1000000
133 no-map;
134 };
135
136 main_r5fss0_core1_memory_regio
137 compatible = "shared-d
138 reg = <0x00 0xa1100000
139 no-map;
140 };
141
142 main_r5fss1_core0_dma_memory_r
143 compatible = "shared-d
144 reg = <0x00 0xa2000000
145 no-map;
146 };
147
148 main_r5fss1_core0_memory_regio
149 compatible = "shared-d
150 reg = <0x00 0xa2100000
151 no-map;
152 };
153
154 main_r5fss1_core1_dma_memory_r
155 compatible = "shared-d
156 reg = <0x00 0xa3000000
157 no-map;
158 };
159
160 main_r5fss1_core1_memory_regio
161 compatible = "shared-d
162 reg = <0x00 0xa3100000
163 no-map;
164 };
165 };
166
167 vdd_mmc0: regulator-vdd-mmc0 {
168 compatible = "regulator-fixed"
169 regulator-name = "vdd-mmc0";
170 regulator-min-microvolt = <180
171 regulator-max-microvolt = <180
172 regulator-always-on;
173 regulator-boot-on;
174 };
175 };
176
177 &cpsw3g {
178 pinctrl-names = "default";
179 pinctrl-0 = <&rgmii1_default_pins>;
180 status = "okay";
181 };
182
183 &cpsw3g_mdio {
184 pinctrl-names = "default";
185 pinctrl-0 = <&mdio0_default_pins>;
186 status = "okay";
187
188 ethernet_phy0: ethernet-phy@0 {
189 compatible = "ethernet-phy-id2
190 reg = <0>;
191 pinctrl-names = "default";
192 pinctrl-0 = <ðernet_phy0_de
193 ti,clk-output-sel = <DP83869_C
194 ti,op-mode = <DP83869_RGMII_CO
195 /*
196 * Disable interrupts because
197 *
198 * interrupt-parent = <&main_g
199 * interrupts = <70 IRQ_TYPE_L
200 */
201 /*
202 * Disable HW Reset because cl
203 *
204 * reset-gpios = <&main_gpio0
205 * reset-assert-us = <1>;
206 * reset-deassert-us = <30>;
207 */
208 };
209 };
210
211 &cpsw_port1 {
212 phy-mode = "rgmii-id";
213 phy-handle = <ðernet_phy0>;
214 status = "okay";
215 };
216
217 &icssg1_mdio {
218 pinctrl-names = "default";
219 pinctrl-0 = <&pru1_mdio0_default_pins>
220 status = "okay";
221
222 ethernet_phy1: ethernet-phy@3 {
223 compatible = "ethernet-phy-id2
224 reg = <3>;
225 pinctrl-names = "default";
226 pinctrl-0 = <ðernet_phy1_de
227 ti,clk-output-sel = <DP83869_C
228 ti,op-mode = <DP83869_RGMII_CO
229 /*
230 * Disable interrupts because
231 *
232 * interrupt-parent = <&main_g
233 * interrupts = <70 IRQ_TYPE_L
234 */
235 /*
236 * Disable HW Reset because cl
237 *
238 * reset-gpios = <&main_gpio0
239 * reset-assert-us = <1>;
240 * reset-deassert-us = <30>;
241 */
242 };
243
244 ethernet_phy2: ethernet-phy@f {
245 compatible = "ethernet-phy-id2
246 reg = <0xf>;
247 pinctrl-names = "default";
248 pinctrl-0 = <ðernet_phy2_de
249 ti,op-mode = <DP83869_RGMII_CO
250 /*
251 * Disable interrupts because
252 *
253 * interrupt-parent = <&main_g
254 * interrupts = <70 IRQ_TYPE_L
255 */
256 /*
257 * Disable HW Reset because cl
258 *
259 * reset-gpios = <&main_gpio0
260 * reset-assert-us = <1>;
261 * reset-deassert-us = <30>;
262 */
263 };
264 };
265
266 &mailbox0_cluster2 {
267 status = "okay";
268
269 mbox_main_r5fss0_core0: mbox-main-r5fs
270 ti,mbox-rx = <0 0 2>;
271 ti,mbox-tx = <1 0 2>;
272 };
273
274 mbox_main_r5fss0_core1: mbox-main-r5fs
275 ti,mbox-rx = <2 0 2>;
276 ti,mbox-tx = <3 0 2>;
277 };
278 };
279
280 &mailbox0_cluster4 {
281 status = "okay";
282
283 mbox_main_r5fss1_core0: mbox-main-r5fs
284 ti,mbox-rx = <0 0 2>;
285 ti,mbox-tx = <1 0 2>;
286 };
287
288 mbox_main_r5fss1_core1: mbox-main-r5fs
289 ti,mbox-rx = <2 0 2>;
290 ti,mbox-tx = <3 0 2>;
291 };
292 };
293
294 &main_i2c0 {
295 pinctrl-names = "default";
296 pinctrl-0 = <&main_i2c0_default_pins>;
297 status = "okay";
298
299 som_eeprom: eeprom@50 {
300 compatible = "atmel,24c01";
301 reg = <0x50>;
302 pagesize = <8>;
303 };
304 };
305
306 &main_pmx0 {
307 /* hog global functions */
308 pinctrl-names = "default";
309 pinctrl-0 = <ðernet_phy_default_pin
310
311 ethernet_phy_default_pins: ethernet-ph
312 pinctrl-single,pins = <
313 /* interrupt / power-d
314 AM64X_IOPAD(0x0278, PI
315 >;
316 };
317
318 ethernet_phy0_default_pins: ethernet-p
319 pinctrl-single,pins = <
320 /* reset */
321 AM64X_IOPAD(0x0154, PI
322 /* reference clock */
323 AM64X_IOPAD(0x0274, PI
324 >;
325 };
326
327 ethernet_phy1_default_pins: ethernet-p
328 pinctrl-single,pins = <
329 /* reset */
330 AM64X_IOPAD(0x0150, PI
331 /* led0, external pull
332 AM64X_IOPAD(0x0128, PI
333 /* led1/rxer */
334 AM64X_IOPAD(0x011c, PI
335 >;
336 };
337
338 ethernet_phy2_default_pins: ethernet-p
339 pinctrl-single,pins = <
340 /* reset */
341 AM64X_IOPAD(0x00d4, PI
342 /* led0, external pull
343 AM64X_IOPAD(0x00d8, PI
344 /* led1/rxer */
345 AM64X_IOPAD(0x00cc, PI
346 >;
347 };
348
349 main_i2c0_default_pins: main-i2c0-defa
350 pinctrl-single,pins = <
351 /* external pull-up on
352 AM64X_IOPAD(0x0260, PI
353 AM64X_IOPAD(0x0264, PI
354 >;
355 };
356
357 /*
358 * main_mmc0_default_pins: main-mmc0-d
359 *
360 * MMC0_CMD: no padconfig
361 * MMC0_CLK: no padconfig, external pu
362 * MMC0_DAT0: no padconfig
363 * MMC0_DAT1: no padconfig
364 * MMC0_DAT2: no padconfig
365 * MMC0_DAT3: no padconfig
366 * MMC0_DAT4: no padconfig
367 * MMC0_DAT5: no padconfig
368 * MMC0_DAT6: no padconfig
369 * MMC0_DAT7: no padconfig
370 * MMC0_DS: no padconfig, external pul
371 */
372
373 main_mmc1_default_pins: main-mmc1-defa
374 pinctrl-single,pins = <
375 AM64X_IOPAD(0x0294, PI
376 AM64X_IOPAD(0x028c, PI
377 AM64X_IOPAD(0x0288, PI
378 AM64X_IOPAD(0x0284, PI
379 AM64X_IOPAD(0x0280, PI
380 AM64X_IOPAD(0x027c, PI
381 /* external pull-down
382 AM64X_IOPAD(0x0298, PI
383 AM64X_IOPAD(0x0290, PI
384 >;
385 };
386
387 main_uart0_default_pins: main-uart0-de
388 pinctrl-single,pins = <
389 AM64X_IOPAD(0x0230, PI
390 AM64X_IOPAD(0x0234, PI
391 >;
392 };
393
394 mdio0_default_pins: mdio0-default-pins
395 pinctrl-single,pins = <
396 AM64X_IOPAD(0x01fc, PI
397 AM64X_IOPAD(0x01f8, PI
398 >;
399 };
400
401 ospi0_default_pins: ospi0-default-pins
402 pinctrl-single,pins = <
403 /* external pull-down
404 AM64X_IOPAD(0x0000, PI
405 AM64X_IOPAD(0x0008, PI
406 /* external pull-up on
407 AM64X_IOPAD(0x002c, PI
408 AM64X_IOPAD(0x000c, PI
409 AM64X_IOPAD(0x0010, PI
410 AM64X_IOPAD(0x0014, PI
411 AM64X_IOPAD(0x0018, PI
412 AM64X_IOPAD(0x001c, PI
413 AM64X_IOPAD(0x0020, PI
414 AM64X_IOPAD(0x0024, PI
415 AM64X_IOPAD(0x0028, PI
416 >;
417 };
418
419 ospi0_flash0_default_pins: ospi0-flash
420 pinctrl-single,pins = <
421 AM64X_IOPAD(0x0034, PI
422 AM64X_IOPAD(0x0038, PI
423 >;
424 };
425
426 pru1_mdio0_default_pins: pru1-mdio0-de
427 pinctrl-single,pins = <
428 AM64X_IOPAD(0x015c, PI
429 AM64X_IOPAD(0x0158, PI
430 >;
431 };
432
433 pru_rgmii1_default_pins: pru-rgmii1-de
434 pinctrl-single,pins = <
435 AM64X_IOPAD(0x00b8, PI
436 AM64X_IOPAD(0x00bc, PI
437 AM64X_IOPAD(0x00c0, PI
438 AM64X_IOPAD(0x00c4, PI
439 AM64X_IOPAD(0x00d0, PI
440 AM64X_IOPAD(0x00c8, PI
441 AM64X_IOPAD(0x00e4, PI
442 AM64X_IOPAD(0x00e8, PI
443 AM64X_IOPAD(0x00ec, PI
444 AM64X_IOPAD(0x00f0, PI
445 AM64X_IOPAD(0x00f8, PI
446 AM64X_IOPAD(0x00f4, PI
447 >;
448 };
449
450 pru_rgmii2_default_pins: pru-rgmii2-de
451 pinctrl-single,pins = <
452 AM64X_IOPAD(0x0108, PI
453 AM64X_IOPAD(0x010c, PI
454 AM64X_IOPAD(0x0110, PI
455 AM64X_IOPAD(0x0114, PI
456 AM64X_IOPAD(0x0120, PI
457 AM64X_IOPAD(0x0118, PI
458 AM64X_IOPAD(0x0134, PI
459 AM64X_IOPAD(0x0138, PI
460 AM64X_IOPAD(0x013c, PI
461 AM64X_IOPAD(0x0140, PI
462 AM64X_IOPAD(0x0148, PI
463 AM64X_IOPAD(0x0144, PI
464 >;
465 };
466
467 rgmii1_default_pins: rgmii1-default-pi
468 pinctrl-single,pins = <
469 AM64X_IOPAD(0x01cc, PI
470 AM64X_IOPAD(0x01d4, PI
471 AM64X_IOPAD(0x01d8, PI
472 AM64X_IOPAD(0x01f4, PI
473 AM64X_IOPAD(0x0188, PI
474 AM64X_IOPAD(0x0184, PI
475 AM64X_IOPAD(0x0124, PI
476 AM64X_IOPAD(0x012c, PI
477 AM64X_IOPAD(0x0130, PI
478 AM64X_IOPAD(0x014c, PI
479 AM64X_IOPAD(0x00e0, PI
480 AM64X_IOPAD(0x00dc, PI
481 >;
482 };
483
484 usb0_default_pins: usb0-default-pins {
485 pinctrl-single,pins = <
486 AM64X_IOPAD(0x02a8, PI
487 >;
488 };
489 };
490
491 &main_r5fss0_core0 {
492 mboxes = <&mailbox0_cluster2 &mbox_mai
493 memory-region = <&main_r5fss0_core0_dm
494 <&main_r5fss0_core0_me
495 };
496
497 &main_r5fss0_core1 {
498 mboxes = <&mailbox0_cluster2 &mbox_mai
499 memory-region = <&main_r5fss0_core1_dm
500 <&main_r5fss0_core1_me
501 };
502
503 &main_r5fss1_core0 {
504 mboxes = <&mailbox0_cluster4 &mbox_mai
505 memory-region = <&main_r5fss1_core0_dm
506 <&main_r5fss1_core0_me
507 };
508
509 &main_r5fss1_core1 {
510 mboxes = <&mailbox0_cluster4 &mbox_mai
511 memory-region = <&main_r5fss1_core1_dm
512 <&main_r5fss1_core1_me
513 };
514
515 /* SoC default UART console */
516 &main_uart0 {
517 pinctrl-names = "default";
518 pinctrl-0 = <&main_uart0_default_pins>
519 status = "okay";
520 };
521
522 &ospi0 {
523 pinctrl-names = "default";
524 pinctrl-0 = <&ospi0_default_pins>;
525 num-cs = <1>;
526 status = "okay";
527
528 flash@0 {
529 compatible = "jedec,spi-nor";
530 reg = <0>;
531 pinctrl-names = "default";
532 pinctrl-0 = <&ospi0_flash0_def
533 spi-tx-bus-width = <8>;
534 spi-rx-bus-width = <8>;
535 spi-max-frequency = <200000000
536 cdns,tshsl-ns = <50>;
537 cdns,tsd2d-ns = <50>;
538 cdns,tchsh-ns = <4>;
539 cdns,tslch-ns = <4>;
540 cdns,read-delay = <0>;
541 interrupt-parent = <&main_gpio
542 interrupts = <14 IRQ_TYPE_LEVE
543 reset-gpios = <&main_gpio0 13
544 };
545 };
546
547 &sdhci0 {
548 /* mmc0 pins have no padconfig */
549 bus-width = <8>;
550 ti,driver-strength-ohm = <50>;
551 disable-wp;
552 non-removable;
553 cap-mmc-hw-reset;
554 no-sd;
555 /*
556 * MMC controller supports switching b
557 * However MMC0 (unlike MMC1) does not
558 * Explicitly link a regulator node fo
559 * voltages are actually usable.
560 */
561 vqmmc-supply = <&vdd_mmc0>;
562 status = "okay";
563 };
564
565 /*
566 * microSD is on carrier - however since SoC c
567 * configure it just in case.
568 */
569 &sdhci1 {
570 pinctrl-names = "default";
571 pinctrl-0 = <&main_mmc1_default_pins>;
572 bus-width = <4>;
573 ti,driver-strength-ohm = <50>;
574 disable-wp;
575 status = "okay";
576 };
577
578 /*
579 * USB settings are a carrier choice - however
580 * configure as USB-2.0 OTG here, keeping USB-
581 */
582 &usb0 {
583 pinctrl-names = "default";
584 pinctrl-0 = <&usb0_default_pins>;
585 dr_mode = "otg";
586 maximum-speed = "high-speed";
587 };
588
589 &usbss0 {
590 ti,vbus-divider;
591 ti,usb2-only;
592 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.