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Linux/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2.dts

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Diff markup

Differences between /arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2.dts (Version linux-6.12-rc7) and /arch/i386/boot/dts/ti/k3-am6548-iot2050-advanced-m2.dts (Version linux-5.4.285)


  1 // SPDX-License-Identifier: GPL-2.0-only          
  2 /*                                                
  3  * Copyright (c) Siemens AG, 2018-2023            
  4  *                                                
  5  * Authors:                                       
  6  *   Chao Zeng <chao.zeng@siemens.com>             
  7  *   Jan Kiszka <jan.kiszka@siemens.com>           
  8  *                                                
  9  * AM6548-based (quad-core) IOT2050 M.2 varian    
 10  * Generation 2), 2 GB RAM, 16 GB eMMC, USB-se    
 11  *                                                
 12  * Product homepage:                              
 13  * https://new.siemens.com/global/en/products/    
 14  */                                               
 15                                                   
 16 #include "k3-am6548-iot2050-advanced-common.dt    
 17 #include "k3-am65-iot2050-common-pg2.dtsi"        
 18 #include "k3-am65-iot2050-arduino-connector.dt    
 19 #include "k3-am65-iot2050-dp.dtsi"                
 20                                                   
 21 / {                                               
 22         compatible = "siemens,iot2050-advanced    
 23         model = "SIMATIC IOT2050 Advanced M2";    
 24 };                                                
 25                                                   
 26 &main_pmx0 {                                      
 27         main_bkey_pcie_reset: main-bkey-pcie-r    
 28                 pinctrl-single,pins = <           
 29                         AM65X_IOPAD(0x01bc, PI    
 30                 >;                                
 31         };                                        
 32                                                   
 33         main_pmx0_m2_config_pins_default: main    
 34                 pinctrl-single,pins = <           
 35                         AM65X_IOPAD(0x01c8, PI    
 36                         AM65X_IOPAD(0x01cc, PI    
 37                 >;                                
 38         };                                        
 39                                                   
 40         main_m2_pcie_mux_control: main-m2-pcie    
 41                 pinctrl-single,pins = <           
 42                         AM65X_IOPAD(0x0148, PI    
 43                         AM65X_IOPAD(0x0160, PI    
 44                         AM65X_IOPAD(0x0164, PI    
 45                 >;                                
 46         };                                        
 47 };                                                
 48                                                   
 49 &main_pmx1 {                                      
 50         main_pmx1_m2_config_pins_default: main    
 51                 pinctrl-single,pins = <           
 52                         AM65X_IOPAD(0x0018, PI    
 53                         AM65X_IOPAD(0x001c, PI    
 54                 >;                                
 55         };                                        
 56 };                                                
 57                                                   
 58 &main_gpio0 {                                     
 59         pinctrl-names = "default";                
 60         pinctrl-0 = <&main_m2_pcie_mux_control    
 61 };                                                
 62                                                   
 63 &main_gpio1 {                                     
 64         pinctrl-names = "default";                
 65         pinctrl-0 =                               
 66                 <&main_pcie_enable_pins_defaul    
 67                 <&main_pmx0_m2_config_pins_def    
 68                 <&main_pmx1_m2_config_pins_def    
 69                 <&cp2102n_reset_pin_default>;     
 70 };                                                
 71                                                   
 72 /*                                                
 73  * Base configuration for B-key slot with PCIe    
 74  * Firmware switches to other modes via device    
 75  */                                               
 76                                                   
 77 &serdes0 {                                        
 78         assigned-clocks = <&k3_clks 153 4>, <&    
 79         assigned-clock-parents = <&k3_clks 153    
 80 };                                                
 81                                                   
 82 &pcie0_rc {                                       
 83         pinctrl-names = "default";                
 84         pinctrl-0 = <&main_bkey_pcie_reset>;      
 85                                                   
 86         num-lanes = <2>;                          
 87         phys = <&serdes0 PHY_TYPE_PCIE 1>, <&s    
 88         phy-names = "pcie-phy0","pcie-phy1";      
 89         reset-gpios = <&main_gpio1 15 GPIO_ACT    
 90         status = "okay";                          
 91 };                                                
 92                                                   
 93 &pcie1_rc {                                       
 94         status = "disabled";                      
 95 };                                                
                                                      

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