1 // SPDX-License-Identifier: GPL-2.0-only OR MI
2 /*
3 * Device Tree Source for J721E SoC Family
4 *
5 * Copyright (C) 2016-2024 Texas Instruments I
6 */
7
8 #include <dt-bindings/interrupt-controller/irq
9 #include <dt-bindings/interrupt-controller/arm
10 #include <dt-bindings/soc/ti,sci_pm_domain.h>
11
12 #include "k3-pinctrl.h"
13
14 / {
15 model = "Texas Instruments K3 J721E So
16 compatible = "ti,j721e";
17 interrupt-parent = <&gic500>;
18 #address-cells = <2>;
19 #size-cells = <2>;
20
21 chosen { };
22
23 cpus {
24 #address-cells = <1>;
25 #size-cells = <0>;
26 cpu-map {
27 cluster0: cluster0 {
28 core0 {
29 cpu =
30 };
31
32 core1 {
33 cpu =
34 };
35 };
36
37 };
38
39 cpu0: cpu@0 {
40 compatible = "arm,cort
41 reg = <0x000>;
42 device_type = "cpu";
43 enable-method = "psci"
44 i-cache-size = <0xC000
45 i-cache-line-size = <6
46 i-cache-sets = <256>;
47 d-cache-size = <0x8000
48 d-cache-line-size = <6
49 d-cache-sets = <256>;
50 next-level-cache = <&L
51 };
52
53 cpu1: cpu@1 {
54 compatible = "arm,cort
55 reg = <0x001>;
56 device_type = "cpu";
57 enable-method = "psci"
58 i-cache-size = <0xC000
59 i-cache-line-size = <6
60 i-cache-sets = <256>;
61 d-cache-size = <0x8000
62 d-cache-line-size = <6
63 d-cache-sets = <256>;
64 next-level-cache = <&L
65 };
66 };
67
68 L2_0: l2-cache0 {
69 compatible = "cache";
70 cache-level = <2>;
71 cache-unified;
72 cache-size = <0x100000>;
73 cache-line-size = <64>;
74 cache-sets = <1024>;
75 next-level-cache = <&msmc_l3>;
76 };
77
78 msmc_l3: l3-cache0 {
79 compatible = "cache";
80 cache-level = <3>;
81 cache-unified;
82 };
83
84 firmware {
85 optee {
86 compatible = "linaro,o
87 method = "smc";
88 };
89
90 psci: psci {
91 compatible = "arm,psci
92 method = "smc";
93 };
94 };
95
96 a72_timer0: timer-cl0-cpu0 {
97 compatible = "arm,armv8-timer"
98 interrupts = <GIC_PPI 13 IRQ_T
99 <GIC_PPI 14 IRQ_T
100 <GIC_PPI 11 IRQ_T
101 <GIC_PPI 10 IRQ_T
102 };
103
104 pmu: pmu {
105 compatible = "arm,cortex-a72-p
106 /* Recommendation from GIC500
107 interrupts = <GIC_PPI 7 IRQ_TY
108 };
109
110 cbass_main: bus@100000 {
111 compatible = "simple-bus";
112 #address-cells = <2>;
113 #size-cells = <2>;
114 ranges = <0x00 0x00100000 0x00
115 <0x00 0x00600000 0x00
116 <0x00 0x00700000 0x00
117 <0x00 0x00900000 0x00
118 <0x00 0x00a40000 0x00
119 <0x00 0x06000000 0x00
120 <0x00 0x06400000 0x00
121 <0x00 0x01000000 0x00
122 <0x00 0x0c000000 0x00
123 <0x00 0x30000000 0x00
124 <0x00 0x0d000000 0x00
125 <0x00 0x0e000000 0x00
126 <0x00 0x10000000 0x00
127 <0x00 0x64800000 0x00
128 <0x00 0x6f000000 0x00
129 <0x44 0x00000000 0x44
130 <0x44 0x10000000 0x44
131 <0x4d 0x80800000 0x4d
132 <0x4d 0x81800000 0x4d
133 <0x4e 0x20000000 0x4e
134 <0x00 0x70000000 0x00
135
136 /* MCUSS_WKUP Range *
137 <0x00 0x28380000 0x00
138 <0x00 0x40200000 0x00
139 <0x00 0x40f00000 0x00
140 <0x00 0x41000000 0x00
141 <0x00 0x41400000 0x00
142 <0x00 0x41c00000 0x00
143 <0x00 0x42040000 0x00
144 <0x00 0x45100000 0x00
145 <0x00 0x46000000 0x00
146 <0x00 0x47000000 0x00
147 <0x00 0x50000000 0x00
148 <0x05 0x00000000 0x05
149 <0x07 0x00000000 0x07
150
151 cbass_mcu_wakeup: bus@28380000
152 compatible = "simple-b
153 #address-cells = <2>;
154 #size-cells = <2>;
155 ranges = <0x00 0x28380
156 <0x00 0x40200
157 <0x00 0x40f00
158 <0x00 0x41000
159 <0x00 0x41400
160 <0x00 0x41c00
161 <0x00 0x42040
162 <0x00 0x45100
163 <0x00 0x46000
164 <0x00 0x47000
165 <0x00 0x50000
166 <0x05 0x00000
167 <0x07 0x00000
168 };
169 };
170
171 #include "k3-j721e-thermal.dtsi"
172 };
173
174 /* Now include the peripherals for each bus se
175 #include "k3-j721e-main.dtsi"
176 #include "k3-j721e-mcu-wakeup.dtsi"
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