1 // SPDX-License-Identifier: GPL-2.0-only OR MI
2 /*
3 * Copyright (C) 2021-2024 Texas Instruments I
4 *
5 * Common Processor Board: https://www.ti.com/
6 */
7
8 /dts-v1/;
9
10 #include "k3-j721s2-som-p0.dtsi"
11 #include <dt-bindings/net/ti-dp83867.h>
12 #include <dt-bindings/phy/phy-cadence.h>
13 #include <dt-bindings/phy/phy.h>
14
15 #include "k3-serdes.h"
16
17 / {
18 compatible = "ti,j721s2-evm", "ti,j721
19 model = "Texas Instruments J721S2 EVM"
20
21 chosen {
22 stdout-path = "serial2:115200n
23 };
24
25 aliases {
26 serial1 = &mcu_uart0;
27 serial2 = &main_uart8;
28 mmc0 = &main_sdhci0;
29 mmc1 = &main_sdhci1;
30 can0 = &main_mcan16;
31 can1 = &mcu_mcan0;
32 can2 = &mcu_mcan1;
33 can3 = &main_mcan3;
34 can4 = &main_mcan5;
35 };
36
37 evm_12v0: fixedregulator-evm12v0 {
38 /* main supply */
39 compatible = "regulator-fixed"
40 regulator-name = "evm_12v0";
41 regulator-min-microvolt = <120
42 regulator-max-microvolt = <120
43 regulator-always-on;
44 regulator-boot-on;
45 };
46
47 vsys_3v3: fixedregulator-vsys3v3 {
48 /* Output of LM5140 */
49 compatible = "regulator-fixed"
50 regulator-name = "vsys_3v3";
51 regulator-min-microvolt = <330
52 regulator-max-microvolt = <330
53 vin-supply = <&evm_12v0>;
54 regulator-always-on;
55 regulator-boot-on;
56 };
57
58 vsys_5v0: fixedregulator-vsys5v0 {
59 /* Output of LM5140 */
60 compatible = "regulator-fixed"
61 regulator-name = "vsys_5v0";
62 regulator-min-microvolt = <500
63 regulator-max-microvolt = <500
64 vin-supply = <&evm_12v0>;
65 regulator-always-on;
66 regulator-boot-on;
67 };
68
69 vdd_mmc1: fixedregulator-sd {
70 /* Output of TPS22918 */
71 compatible = "regulator-fixed"
72 regulator-name = "vdd_mmc1";
73 regulator-min-microvolt = <330
74 regulator-max-microvolt = <330
75 regulator-boot-on;
76 enable-active-high;
77 vin-supply = <&vsys_3v3>;
78 gpio = <&exp2 2 GPIO_ACTIVE_HI
79 };
80
81 vdd_sd_dv: gpio-regulator-TLV71033 {
82 /* Output of TLV71033 */
83 compatible = "regulator-gpio";
84 regulator-name = "tlv71033";
85 pinctrl-names = "default";
86 pinctrl-0 = <&vdd_sd_dv_pins_d
87 regulator-min-microvolt = <180
88 regulator-max-microvolt = <330
89 regulator-boot-on;
90 vin-supply = <&vsys_5v0>;
91 gpios = <&main_gpio0 8 GPIO_AC
92 states = <1800000 0x0>,
93 <3300000 0x1>;
94 };
95
96 transceiver1: can-phy1 {
97 compatible = "ti,tcan1043";
98 #phy-cells = <0>;
99 max-bitrate = <5000000>;
100 pinctrl-names = "default";
101 pinctrl-0 = <&mcu_mcan0_gpio_p
102 standby-gpios = <&wkup_gpio0 6
103 enable-gpios = <&wkup_gpio0 0
104 };
105
106 transceiver2: can-phy2 {
107 compatible = "ti,tcan1042";
108 #phy-cells = <0>;
109 max-bitrate = <5000000>;
110 pinctrl-names = "default";
111 pinctrl-0 = <&mcu_mcan1_gpio_p
112 standby-gpios = <&wkup_gpio0 2
113 };
114
115 transceiver3: can-phy3 {
116 compatible = "ti,tcan1043";
117 #phy-cells = <0>;
118 max-bitrate = <5000000>;
119 standby-gpios = <&exp2 7 GPIO_
120 enable-gpios = <&exp2 6 GPIO_A
121 mux-states = <&mux0 1>;
122 };
123
124 transceiver4: can-phy4 {
125 compatible = "ti,tcan1042";
126 #phy-cells = <0>;
127 max-bitrate = <5000000>;
128 standby-gpios = <&exp_som 7 GP
129 mux-states = <&mux1 1>;
130 };
131 };
132
133 &main_pmx0 {
134 main_uart8_pins_default: main-uart8-de
135 pinctrl-single,pins = <
136 J721S2_IOPAD(0x040, PI
137 J721S2_IOPAD(0x044, PI
138 J721S2_IOPAD(0x0d0, PI
139 J721S2_IOPAD(0x0d4, PI
140 >;
141 };
142
143 main_i2c3_pins_default: main-i2c3-defa
144 pinctrl-single,pins = <
145 J721S2_IOPAD(0x064, PI
146 J721S2_IOPAD(0x060, PI
147 >;
148 };
149
150 main_i2c5_pins_default: main-i2c5-defa
151 pinctrl-single,pins = <
152 J721S2_IOPAD(0x01c, PI
153 J721S2_IOPAD(0x018, PI
154 >;
155 };
156
157 main_mmc1_pins_default: main-mmc1-defa
158 pinctrl-single,pins = <
159 J721S2_IOPAD(0x104, PI
160 J721S2_IOPAD(0x108, PI
161 J721S2_IOPAD(0x100, PI
162 J721S2_IOPAD(0x0fc, PI
163 J721S2_IOPAD(0x0f8, PI
164 J721S2_IOPAD(0x0f4, PI
165 J721S2_IOPAD(0x0f0, PI
166 J721S2_IOPAD(0x0e8, PI
167 >;
168 };
169
170 vdd_sd_dv_pins_default: vdd-sd-dv-defa
171 pinctrl-single,pins = <
172 J721S2_IOPAD(0x020, PI
173 >;
174 };
175
176 main_usbss0_pins_default: main-usbss0-
177 pinctrl-single,pins = <
178 J721S2_IOPAD(0x0ec, PI
179 >;
180 };
181
182 main_mcan3_pins_default: main-mcan3-de
183 pinctrl-single,pins = <
184 J721S2_IOPAD(0x080, PI
185 J721S2_IOPAD(0x07c, PI
186 >;
187 };
188
189 main_mcan5_pins_default: main-mcan5-de
190 pinctrl-single,pins = <
191 J721S2_IOPAD(0x03c, PI
192 J721S2_IOPAD(0x038, PI
193 >;
194 };
195 };
196
197 &wkup_pmx2 {
198 wkup_uart0_pins_default: wkup-uart0-de
199 pinctrl-single,pins = <
200 J721S2_WKUP_IOPAD(0x04
201 J721S2_WKUP_IOPAD(0x04
202 >;
203 };
204
205 mcu_uart0_pins_default: mcu-uart0-defa
206 pinctrl-single,pins = <
207 J721S2_WKUP_IOPAD(0x09
208 J721S2_WKUP_IOPAD(0x09
209 J721S2_WKUP_IOPAD(0x08
210 J721S2_WKUP_IOPAD(0x08
211 >;
212 };
213
214 mcu_cpsw_pins_default: mcu-cpsw-defaul
215 pinctrl-single,pins = <
216 J721S2_WKUP_IOPAD(0x02
217 J721S2_WKUP_IOPAD(0x02
218 J721S2_WKUP_IOPAD(0x02
219 J721S2_WKUP_IOPAD(0x02
220 J721S2_WKUP_IOPAD(0x01
221 J721S2_WKUP_IOPAD(0x00
222 J721S2_WKUP_IOPAD(0x01
223 J721S2_WKUP_IOPAD(0x01
224 J721S2_WKUP_IOPAD(0x00
225 J721S2_WKUP_IOPAD(0x00
226 J721S2_WKUP_IOPAD(0x01
227 J721S2_WKUP_IOPAD(0x00
228 >;
229 };
230
231 mcu_mdio_pins_default: mcu-mdio-defaul
232 pinctrl-single,pins = <
233 J721S2_WKUP_IOPAD(0x03
234 J721S2_WKUP_IOPAD(0x03
235 >;
236 };
237
238 mcu_mcan0_pins_default: mcu-mcan0-defa
239 pinctrl-single,pins = <
240 J721S2_WKUP_IOPAD(0x05
241 J721S2_WKUP_IOPAD(0x05
242 >;
243 };
244
245 mcu_mcan1_pins_default: mcu-mcan1-defa
246 pinctrl-single,pins = <
247 J721S2_WKUP_IOPAD(0x06
248 J721S2_WKUP_IOPAD(0x06
249 >;
250 };
251
252 mcu_mcan0_gpio_pins_default: mcu-mcan0
253 pinctrl-single,pins = <
254 J721S2_WKUP_IOPAD(0x05
255 J721S2_WKUP_IOPAD(0x04
256 >;
257 };
258
259 mcu_mcan1_gpio_pins_default: mcu-mcan1
260 pinctrl-single,pins = <
261 J721S2_WKUP_IOPAD(0x06
262 >;
263 };
264
265 mcu_adc0_pins_default: mcu-adc0-defaul
266 pinctrl-single,pins = <
267 J721S2_WKUP_IOPAD(0x0c
268 J721S2_WKUP_IOPAD(0x0d
269 J721S2_WKUP_IOPAD(0x0d
270 J721S2_WKUP_IOPAD(0x0d
271 J721S2_WKUP_IOPAD(0x0d
272 J721S2_WKUP_IOPAD(0x0e
273 J721S2_WKUP_IOPAD(0x0e
274 J721S2_WKUP_IOPAD(0x0e
275 >;
276 };
277
278 mcu_adc1_pins_default: mcu-adc1-defaul
279 pinctrl-single,pins = <
280 J721S2_WKUP_IOPAD(0x0e
281 J721S2_WKUP_IOPAD(0x0f
282 J721S2_WKUP_IOPAD(0x0f
283 J721S2_WKUP_IOPAD(0x0f
284 J721S2_WKUP_IOPAD(0x0f
285 J721S2_WKUP_IOPAD(0x10
286 J721S2_WKUP_IOPAD(0x10
287 J721S2_WKUP_IOPAD(0x10
288 >;
289 };
290 };
291
292 &wkup_pmx1 {
293 mcu_fss0_ospi1_pins_default: mcu-fss0-
294 pinctrl-single,pins = <
295 J721S2_WKUP_IOPAD(0x00
296 J721S2_WKUP_IOPAD(0x02
297 J721S2_WKUP_IOPAD(0x01
298 J721S2_WKUP_IOPAD(0x01
299 J721S2_WKUP_IOPAD(0x01
300 J721S2_WKUP_IOPAD(0x02
301 J721S2_WKUP_IOPAD(0x01
302 J721S2_WKUP_IOPAD(0x00
303 >;
304 };
305 };
306
307 &main_gpio0 {
308 status = "okay";
309 };
310
311 &wkup_gpio0 {
312 status = "okay";
313 };
314
315 &wkup_uart0 {
316 status = "reserved";
317 pinctrl-names = "default";
318 pinctrl-0 = <&wkup_uart0_pins_default>
319 };
320
321 &mcu_uart0 {
322 status = "okay";
323 pinctrl-names = "default";
324 pinctrl-0 = <&mcu_uart0_pins_default>;
325 };
326
327 &main_uart8 {
328 status = "okay";
329 pinctrl-names = "default";
330 pinctrl-0 = <&main_uart8_pins_default>
331 /* Shared with TFA on this platform */
332 power-domains = <&k3_pds 357 TI_SCI_PD
333 };
334
335 &main_i2c0 {
336 clock-frequency = <400000>;
337
338 exp1: gpio@20 {
339 compatible = "ti,tca6416";
340 reg = <0x20>;
341 gpio-controller;
342 #gpio-cells = <2>;
343 gpio-line-names = "PCIE_2L_MOD
344 "PCIE_2L_EP_
345 "PCIE_1L_RC_
346 "PCIE_1L_PRS
347 "EXP_MUX2",
348 };
349
350 exp2: gpio@22 {
351 compatible = "ti,tca6424";
352 reg = <0x22>;
353 gpio-controller;
354 #gpio-cells = <2>;
355 gpio-line-names = "APPLE_AUTH_
356 "USBC_MODE_S
357 "MUX_SPAREMU
358 "MLB_MUX_SEL
359 "CDCI2_RSTZ"
360 "ENET_EXP_SP
361 };
362 };
363
364 &main_i2c5 {
365 pinctrl-names = "default";
366 pinctrl-0 = <&main_i2c5_pins_default>;
367 clock-frequency = <400000>;
368 status = "okay";
369
370 exp5: gpio@20 {
371 compatible = "ti,tca6408";
372 reg = <0x20>;
373 gpio-controller;
374 #gpio-cells = <2>;
375 gpio-line-names = "CSI2_EXP_RS
376 "CSI2_EXP_A_
377 "CSI2_EXP_B_
378 "CSI2_EXP_B_
379 };
380 };
381
382 &main_sdhci0 {
383 /* eMMC */
384 status = "okay";
385 non-removable;
386 ti,driver-strength-ohm = <50>;
387 disable-wp;
388 };
389
390 &main_sdhci1 {
391 /* SD card */
392 status = "okay";
393 pinctrl-0 = <&main_mmc1_pins_default>;
394 pinctrl-names = "default";
395 disable-wp;
396 vmmc-supply = <&vdd_mmc1>;
397 vqmmc-supply = <&vdd_sd_dv>;
398 };
399
400 &mcu_cpsw {
401 pinctrl-names = "default";
402 pinctrl-0 = <&mcu_cpsw_pins_default>,
403 };
404
405 &davinci_mdio {
406 phy0: ethernet-phy@0 {
407 reg = <0>;
408 ti,rx-internal-delay = <DP8386
409 ti,fifo-depth = <DP83867_PHYCR
410 ti,min-output-impedance;
411 };
412 };
413
414 &cpsw_port1 {
415 phy-mode = "rgmii-rxid";
416 phy-handle = <&phy0>;
417 };
418
419 &serdes_ln_ctrl {
420 idle-states = <J721S2_SERDES0_LANE0_PC
421 <J721S2_SERDES0_LANE2_ED
422 };
423
424 &serdes_refclk {
425 clock-frequency = <100000000>;
426 };
427
428 &serdes0 {
429 status = "okay";
430 serdes0_pcie_link: phy@0 {
431 reg = <0>;
432 cdns,num-lanes = <1>;
433 #phy-cells = <0>;
434 cdns,phy-type = <PHY_TYPE_PCIE
435 resets = <&serdes_wiz0 1>;
436 };
437 };
438
439 &usb_serdes_mux {
440 idle-states = <1>; /* USB0 to SERDES l
441 };
442
443 &usbss0 {
444 status = "okay";
445 pinctrl-0 = <&main_usbss0_pins_default
446 pinctrl-names = "default";
447 ti,vbus-divider;
448 ti,usb2-only;
449 };
450
451 &usb0 {
452 dr_mode = "otg";
453 maximum-speed = "high-speed";
454 };
455
456 &ospi1 {
457 status = "okay";
458 pinctrl-names = "default";
459 pinctrl-0 = <&mcu_fss0_ospi1_pins_defa
460
461 flash@0 {
462 compatible = "jedec,spi-nor";
463 reg = <0x0>;
464 spi-tx-bus-width = <1>;
465 spi-rx-bus-width = <4>;
466 spi-max-frequency = <40000000>
467 cdns,tshsl-ns = <60>;
468 cdns,tsd2d-ns = <60>;
469 cdns,tchsh-ns = <60>;
470 cdns,tslch-ns = <60>;
471 cdns,read-delay = <2>;
472 };
473 };
474
475 &pcie1_rc {
476 status = "okay";
477 reset-gpios = <&exp1 2 GPIO_ACTIVE_HIG
478 phys = <&serdes0_pcie_link>;
479 phy-names = "pcie-phy";
480 num-lanes = <1>;
481 };
482
483 &mcu_mcan0 {
484 status = "okay";
485 pinctrl-names = "default";
486 pinctrl-0 = <&mcu_mcan0_pins_default>;
487 phys = <&transceiver1>;
488 };
489
490 &mcu_mcan1 {
491 status = "okay";
492 pinctrl-names = "default";
493 pinctrl-0 = <&mcu_mcan1_pins_default>;
494 phys = <&transceiver2>;
495 };
496
497 &tscadc0 {
498 pinctrl-0 = <&mcu_adc0_pins_default>;
499 pinctrl-names = "default";
500 status = "okay";
501 adc {
502 ti,adc-channels = <0 1 2 3 4 5
503 };
504 };
505
506 &tscadc1 {
507 pinctrl-0 = <&mcu_adc1_pins_default>;
508 pinctrl-names = "default";
509 status = "okay";
510 adc {
511 ti,adc-channels = <0 1 2 3 4 5
512 };
513 };
514
515 &main_mcan3 {
516 status = "okay";
517 pinctrl-names = "default";
518 pinctrl-0 = <&main_mcan3_pins_default>
519 phys = <&transceiver3>;
520 };
521
522 &main_mcan5 {
523 status = "okay";
524 pinctrl-names = "default";
525 pinctrl-0 = <&main_mcan5_pins_default>
526 phys = <&transceiver4>;
527 };
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