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Linux/arch/arm64/boot/dts/ti/k3-j721s2-evm-gesi-exp-board.dtso

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Diff markup

Differences between /arch/arm64/boot/dts/ti/k3-j721s2-evm-gesi-exp-board.dtso (Architecture i386) and /arch/alpha/boot/dts/ti/k3-j721s2-evm-gesi-exp-board.dtso (Architecture alpha)


  1 // SPDX-License-Identifier: GPL-2.0-only OR MI    
  2 /**                                               
  3  * DT Overlay for MAIN CPSW2G using GESI Expan    
  4  *                                                
  5  * GESI Board Product Link: https://www.ti.com    
  6  *                                                
  7  * Copyright (C) 2023-2024 Texas Instruments I    
  8  */                                               
  9                                                   
 10 /dts-v1/;                                         
 11 /plugin/;                                         
 12                                                   
 13 #include <dt-bindings/gpio/gpio.h>                
 14 #include <dt-bindings/net/ti-dp83867.h>           
 15                                                   
 16 #include "k3-pinctrl.h"                           
 17                                                   
 18 &{/} {                                            
 19         aliases {                                 
 20                 ethernet1 = "/bus@100000/ether    
 21         };                                        
 22 };                                                
 23                                                   
 24 &main_pmx0 {                                      
 25         main_cpsw_mdio_default_pins: main-cpsw    
 26                 pinctrl-single,pins = <           
 27                         J721S2_IOPAD(0x0c0, PI    
 28                         J721S2_IOPAD(0x0bc, PI    
 29                 >;                                
 30         };                                        
 31                                                   
 32         rgmii1_default_pins: rgmii1-default-pi    
 33                 pinctrl-single,pins = <           
 34                         J721S2_IOPAD(0x0b8, PI    
 35                         J721S2_IOPAD(0x0a0, PI    
 36                         J721S2_IOPAD(0x0a4, PI    
 37                         J721S2_IOPAD(0x0a8, PI    
 38                         J721S2_IOPAD(0x0b0, PI    
 39                         J721S2_IOPAD(0x0ac, PI    
 40                         J721S2_IOPAD(0x08c, PI    
 41                         J721S2_IOPAD(0x090, PI    
 42                         J721S2_IOPAD(0x094, PI    
 43                         J721S2_IOPAD(0x098, PI    
 44                         J721S2_IOPAD(0x0b4, PI    
 45                         J721S2_IOPAD(0x09c, PI    
 46                 >;                                
 47         };                                        
 48 };                                                
 49                                                   
 50 &exp1 {                                           
 51         p15-hog {                                 
 52                 /* P15 - EXP_MUX2 */              
 53                 gpio-hog;                         
 54                 gpios = <13 GPIO_ACTIVE_HIGH>;    
 55                 output-high;                      
 56                 line-name = "EXP_MUX2";           
 57         };                                        
 58 };                                                
 59                                                   
 60 &main_cpsw {                                      
 61         status = "okay";                          
 62         pinctrl-names = "default";                
 63         pinctrl-0 = <&rgmii1_default_pins>;       
 64 };                                                
 65                                                   
 66 &main_cpsw_mdio {                                 
 67         status = "okay";                          
 68         pinctrl-names = "default";                
 69         pinctrl-0 = <&main_cpsw_mdio_default_p    
 70         #address-cells = <1>;                     
 71         #size-cells = <0>;                        
 72                                                   
 73         main_cpsw_phy0: ethernet-phy@0 {          
 74                 reg = <0>;                        
 75                 ti,rx-internal-delay = <DP8386    
 76                 ti,fifo-depth = <DP83867_PHYCR    
 77                 ti,min-output-impedance;          
 78         };                                        
 79 };                                                
 80                                                   
 81 &main_cpsw_port1 {                                
 82         status = "okay";                          
 83         phy-mode = "rgmii-rxid";                  
 84         phy-handle = <&main_cpsw_phy0>;           
 85 };                                                
                                                      

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