1 // SPDX-License-Identifier: GPL-2.0-only OR MI
2 /*
3 * Device Tree Source for J721S2 SoC Family Ma
4 *
5 * Copyright (C) 2021-2024 Texas Instruments I
6 */
7
8 #include <dt-bindings/phy/phy-cadence.h>
9 #include <dt-bindings/phy/phy-ti.h>
10
11 / {
12 serdes_refclk: clock-cmnrefclk {
13 #clock-cells = <0>;
14 compatible = "fixed-clock";
15 clock-frequency = <0>;
16 };
17 };
18
19 &cbass_main {
20 msmc_ram: sram@70000000 {
21 compatible = "mmio-sram";
22 reg = <0x0 0x70000000 0x0 0x40
23 #address-cells = <1>;
24 #size-cells = <1>;
25 ranges = <0x0 0x0 0x70000000 0
26
27 atf-sram@0 {
28 reg = <0x0 0x20000>;
29 };
30
31 tifs-sram@1f0000 {
32 reg = <0x1f0000 0x1000
33 };
34
35 l3cache-sram@200000 {
36 reg = <0x200000 0x2000
37 };
38 };
39
40 scm_conf: syscon@104000 {
41 compatible = "ti,j721e-system-
42 reg = <0x00 0x00104000 0x00 0x
43 #address-cells = <1>;
44 #size-cells = <1>;
45 ranges = <0x00 0x00 0x00104000
46
47 usb_serdes_mux: mux-controller
48 compatible = "reg-mux"
49 reg = <0x0 0x4>;
50 #mux-control-cells = <
51 mux-reg-masks = <0x0 0
52 };
53
54 phy_gmii_sel_cpsw: phy@34 {
55 compatible = "ti,am654
56 reg = <0x34 0x4>;
57 #phy-cells = <1>;
58 };
59
60 serdes_ln_ctrl: mux-controller
61 compatible = "reg-mux"
62 reg = <0x80 0x10>;
63 #mux-control-cells = <
64 mux-reg-masks = <0x0 0
65 <0x8 0
66 };
67
68 ehrpwm_tbclk: clock-controller
69 compatible = "ti,am654
70 reg = <0x140 0x18>;
71 #clock-cells = <1>;
72 };
73 };
74
75 main_ehrpwm0: pwm@3000000 {
76 compatible = "ti,am654-ehrpwm"
77 #pwm-cells = <3>;
78 reg = <0x00 0x3000000 0x00 0x1
79 power-domains = <&k3_pds 160 T
80 clocks = <&ehrpwm_tbclk 0>, <&
81 clock-names = "tbclk", "fck";
82 status = "disabled";
83 };
84
85 main_ehrpwm1: pwm@3010000 {
86 compatible = "ti,am654-ehrpwm"
87 #pwm-cells = <3>;
88 reg = <0x00 0x3010000 0x00 0x1
89 power-domains = <&k3_pds 161 T
90 clocks = <&ehrpwm_tbclk 1>, <&
91 clock-names = "tbclk", "fck";
92 status = "disabled";
93 };
94
95 main_ehrpwm2: pwm@3020000 {
96 compatible = "ti,am654-ehrpwm"
97 #pwm-cells = <3>;
98 reg = <0x00 0x3020000 0x00 0x1
99 power-domains = <&k3_pds 162 T
100 clocks = <&ehrpwm_tbclk 2>, <&
101 clock-names = "tbclk", "fck";
102 status = "disabled";
103 };
104
105 main_ehrpwm3: pwm@3030000 {
106 compatible = "ti,am654-ehrpwm"
107 #pwm-cells = <3>;
108 reg = <0x00 0x3030000 0x00 0x1
109 power-domains = <&k3_pds 163 T
110 clocks = <&ehrpwm_tbclk 3>, <&
111 clock-names = "tbclk", "fck";
112 status = "disabled";
113 };
114
115 main_ehrpwm4: pwm@3040000 {
116 compatible = "ti,am654-ehrpwm"
117 #pwm-cells = <3>;
118 reg = <0x00 0x3040000 0x00 0x1
119 power-domains = <&k3_pds 164 T
120 clocks = <&ehrpwm_tbclk 4>, <&
121 clock-names = "tbclk", "fck";
122 status = "disabled";
123 };
124
125 main_ehrpwm5: pwm@3050000 {
126 compatible = "ti,am654-ehrpwm"
127 #pwm-cells = <3>;
128 reg = <0x00 0x3050000 0x00 0x1
129 power-domains = <&k3_pds 165 T
130 clocks = <&ehrpwm_tbclk 5>, <&
131 clock-names = "tbclk", "fck";
132 status = "disabled";
133 };
134
135 gic500: interrupt-controller@1800000 {
136 compatible = "arm,gic-v3";
137 #address-cells = <2>;
138 #size-cells = <2>;
139 ranges;
140 #interrupt-cells = <3>;
141 interrupt-controller;
142 reg = <0x00 0x01800000 0x00 0x
143 <0x00 0x01900000 0x00 0x
144 <0x00 0x6f000000 0x00 0x
145 <0x00 0x6f010000 0x00 0x
146 <0x00 0x6f020000 0x00 0x
147
148 /* vcpumntirq: virtual CPU int
149 interrupts = <GIC_PPI 9 IRQ_TY
150
151 gic_its: msi-controller@182000
152 compatible = "arm,gic-
153 reg = <0x00 0x01820000
154 socionext,synquacer-pr
155 msi-controller;
156 #msi-cells = <1>;
157 };
158 };
159
160 main_gpio_intr: interrupt-controller@a
161 compatible = "ti,sci-intr";
162 reg = <0x00 0x00a00000 0x00 0x
163 ti,intr-trigger-type = <1>;
164 interrupt-controller;
165 interrupt-parent = <&gic500>;
166 #interrupt-cells = <1>;
167 ti,sci = <&sms>;
168 ti,sci-dev-id = <148>;
169 ti,interrupt-ranges = <8 392 5
170 };
171
172 main_pmx0: pinctrl@11c000 {
173 compatible = "pinctrl-single";
174 /* Proxy 0 addressing */
175 reg = <0x0 0x11c000 0x0 0x120>
176 #pinctrl-cells = <1>;
177 pinctrl-single,register-width
178 pinctrl-single,function-mask =
179 };
180
181 /* TIMERIO pad input CTRLMMR_TIMER*_CT
182 main_timerio_input: pinctrl@104200 {
183 compatible = "pinctrl-single";
184 reg = <0x00 0x104200 0x00 0x50
185 #pinctrl-cells = <1>;
186 pinctrl-single,register-width
187 pinctrl-single,function-mask =
188 };
189
190 /* TIMERIO pad output CTCTRLMMR_TIMERI
191 main_timerio_output: pinctrl@104280 {
192 compatible = "pinctrl-single";
193 reg = <0x00 0x104280 0x00 0x20
194 #pinctrl-cells = <1>;
195 pinctrl-single,register-width
196 pinctrl-single,function-mask =
197 };
198
199 main_crypto: crypto@4e00000 {
200 compatible = "ti,j721e-sa2ul";
201 reg = <0x00 0x04e00000 0x00 0x
202 power-domains = <&k3_pds 297 T
203 #address-cells = <2>;
204 #size-cells = <2>;
205 ranges = <0x00 0x04e00000 0x00
206
207 dmas = <&main_udmap 0xca40>, <
208 <&main_udmap 0x4a41>;
209 dma-names = "tx", "rx1", "rx2"
210
211 rng: rng@4e10000 {
212 compatible = "inside-s
213 reg = <0x00 0x04e10000
214 interrupts = <GIC_SPI
215 };
216 };
217
218 main_timer0: timer@2400000 {
219 compatible = "ti,am654-timer";
220 reg = <0x00 0x2400000 0x00 0x4
221 interrupts = <GIC_SPI 224 IRQ_
222 clocks = <&k3_clks 63 1>;
223 clock-names = "fck";
224 assigned-clocks = <&k3_clks 63
225 assigned-clock-parents = <&k3_
226 power-domains = <&k3_pds 63 TI
227 ti,timer-pwm;
228 };
229
230 main_timer1: timer@2410000 {
231 compatible = "ti,am654-timer";
232 reg = <0x00 0x2410000 0x00 0x4
233 interrupts = <GIC_SPI 225 IRQ_
234 clocks = <&k3_clks 64 1>;
235 clock-names = "fck";
236 assigned-clocks = <&k3_clks 64
237 assigned-clock-parents = <&k3_
238 power-domains = <&k3_pds 64 TI
239 ti,timer-pwm;
240 };
241
242 main_timer2: timer@2420000 {
243 compatible = "ti,am654-timer";
244 reg = <0x00 0x2420000 0x00 0x4
245 interrupts = <GIC_SPI 226 IRQ_
246 clocks = <&k3_clks 65 1>;
247 clock-names = "fck";
248 assigned-clocks = <&k3_clks 65
249 assigned-clock-parents = <&k3_
250 power-domains = <&k3_pds 65 TI
251 ti,timer-pwm;
252 };
253
254 main_timer3: timer@2430000 {
255 compatible = "ti,am654-timer";
256 reg = <0x00 0x2430000 0x00 0x4
257 interrupts = <GIC_SPI 227 IRQ_
258 clocks = <&k3_clks 66 1>;
259 clock-names = "fck";
260 assigned-clocks = <&k3_clks 66
261 assigned-clock-parents = <&k3_
262 power-domains = <&k3_pds 66 TI
263 ti,timer-pwm;
264 };
265
266 main_timer4: timer@2440000 {
267 compatible = "ti,am654-timer";
268 reg = <0x00 0x2440000 0x00 0x4
269 interrupts = <GIC_SPI 228 IRQ_
270 clocks = <&k3_clks 67 1>;
271 clock-names = "fck";
272 assigned-clocks = <&k3_clks 67
273 assigned-clock-parents = <&k3_
274 power-domains = <&k3_pds 67 TI
275 ti,timer-pwm;
276 };
277
278 main_timer5: timer@2450000 {
279 compatible = "ti,am654-timer";
280 reg = <0x00 0x2450000 0x00 0x4
281 interrupts = <GIC_SPI 229 IRQ_
282 clocks = <&k3_clks 68 1>;
283 clock-names = "fck";
284 assigned-clocks = <&k3_clks 68
285 assigned-clock-parents = <&k3_
286 power-domains = <&k3_pds 68 TI
287 ti,timer-pwm;
288 };
289
290 main_timer6: timer@2460000 {
291 compatible = "ti,am654-timer";
292 reg = <0x00 0x2460000 0x00 0x4
293 interrupts = <GIC_SPI 230 IRQ_
294 clocks = <&k3_clks 69 1>;
295 clock-names = "fck";
296 assigned-clocks = <&k3_clks 69
297 assigned-clock-parents = <&k3_
298 power-domains = <&k3_pds 69 TI
299 ti,timer-pwm;
300 };
301
302 main_timer7: timer@2470000 {
303 compatible = "ti,am654-timer";
304 reg = <0x00 0x2470000 0x00 0x4
305 interrupts = <GIC_SPI 231 IRQ_
306 clocks = <&k3_clks 70 1>;
307 clock-names = "fck";
308 assigned-clocks = <&k3_clks 70
309 assigned-clock-parents = <&k3_
310 power-domains = <&k3_pds 70 TI
311 ti,timer-pwm;
312 };
313
314 main_timer8: timer@2480000 {
315 compatible = "ti,am654-timer";
316 reg = <0x00 0x2480000 0x00 0x4
317 interrupts = <GIC_SPI 232 IRQ_
318 clocks = <&k3_clks 71 1>;
319 clock-names = "fck";
320 assigned-clocks = <&k3_clks 71
321 assigned-clock-parents = <&k3_
322 power-domains = <&k3_pds 71 TI
323 ti,timer-pwm;
324 };
325
326 main_timer9: timer@2490000 {
327 compatible = "ti,am654-timer";
328 reg = <0x00 0x2490000 0x00 0x4
329 interrupts = <GIC_SPI 233 IRQ_
330 clocks = <&k3_clks 72 1>;
331 clock-names = "fck";
332 assigned-clocks = <&k3_clks 72
333 assigned-clock-parents = <&k3_
334 power-domains = <&k3_pds 72 TI
335 ti,timer-pwm;
336 };
337
338 main_timer10: timer@24a0000 {
339 compatible = "ti,am654-timer";
340 reg = <0x00 0x24a0000 0x00 0x4
341 interrupts = <GIC_SPI 234 IRQ_
342 clocks = <&k3_clks 73 1>;
343 clock-names = "fck";
344 assigned-clocks = <&k3_clks 73
345 assigned-clock-parents = <&k3_
346 power-domains = <&k3_pds 73 TI
347 ti,timer-pwm;
348 };
349
350 main_timer11: timer@24b0000 {
351 compatible = "ti,am654-timer";
352 reg = <0x00 0x24b0000 0x00 0x4
353 interrupts = <GIC_SPI 235 IRQ_
354 clocks = <&k3_clks 74 1>;
355 clock-names = "fck";
356 assigned-clocks = <&k3_clks 74
357 assigned-clock-parents = <&k3_
358 power-domains = <&k3_pds 74 TI
359 ti,timer-pwm;
360 };
361
362 main_timer12: timer@24c0000 {
363 compatible = "ti,am654-timer";
364 reg = <0x00 0x24c0000 0x00 0x4
365 interrupts = <GIC_SPI 236 IRQ_
366 clocks = <&k3_clks 75 1>;
367 clock-names = "fck";
368 assigned-clocks = <&k3_clks 75
369 assigned-clock-parents = <&k3_
370 power-domains = <&k3_pds 75 TI
371 ti,timer-pwm;
372 };
373
374 main_timer13: timer@24d0000 {
375 compatible = "ti,am654-timer";
376 reg = <0x00 0x24d0000 0x00 0x4
377 interrupts = <GIC_SPI 237 IRQ_
378 clocks = <&k3_clks 76 1>;
379 clock-names = "fck";
380 assigned-clocks = <&k3_clks 76
381 assigned-clock-parents = <&k3_
382 power-domains = <&k3_pds 76 TI
383 ti,timer-pwm;
384 };
385
386 main_timer14: timer@24e0000 {
387 compatible = "ti,am654-timer";
388 reg = <0x00 0x24e0000 0x00 0x4
389 interrupts = <GIC_SPI 238 IRQ_
390 clocks = <&k3_clks 77 1>;
391 clock-names = "fck";
392 assigned-clocks = <&k3_clks 77
393 assigned-clock-parents = <&k3_
394 power-domains = <&k3_pds 77 TI
395 ti,timer-pwm;
396 };
397
398 main_timer15: timer@24f0000 {
399 compatible = "ti,am654-timer";
400 reg = <0x00 0x24f0000 0x00 0x4
401 interrupts = <GIC_SPI 239 IRQ_
402 clocks = <&k3_clks 78 1>;
403 clock-names = "fck";
404 assigned-clocks = <&k3_clks 78
405 assigned-clock-parents = <&k3_
406 power-domains = <&k3_pds 78 TI
407 ti,timer-pwm;
408 };
409
410 main_timer16: timer@2500000 {
411 compatible = "ti,am654-timer";
412 reg = <0x00 0x2500000 0x00 0x4
413 interrupts = <GIC_SPI 240 IRQ_
414 clocks = <&k3_clks 79 1>;
415 clock-names = "fck";
416 assigned-clocks = <&k3_clks 79
417 assigned-clock-parents = <&k3_
418 power-domains = <&k3_pds 79 TI
419 ti,timer-pwm;
420 };
421
422 main_timer17: timer@2510000 {
423 compatible = "ti,am654-timer";
424 reg = <0x00 0x2510000 0x00 0x4
425 interrupts = <GIC_SPI 241 IRQ_
426 clocks = <&k3_clks 80 1>;
427 clock-names = "fck";
428 assigned-clocks = <&k3_clks 80
429 assigned-clock-parents = <&k3_
430 power-domains = <&k3_pds 80 TI
431 ti,timer-pwm;
432 };
433
434 main_timer18: timer@2520000 {
435 compatible = "ti,am654-timer";
436 reg = <0x00 0x2520000 0x00 0x4
437 interrupts = <GIC_SPI 242 IRQ_
438 clocks = <&k3_clks 81 1>;
439 clock-names = "fck";
440 assigned-clocks = <&k3_clks 81
441 assigned-clock-parents = <&k3_
442 power-domains = <&k3_pds 81 TI
443 ti,timer-pwm;
444 };
445
446 main_timer19: timer@2530000 {
447 compatible = "ti,am654-timer";
448 reg = <0x00 0x2530000 0x00 0x4
449 interrupts = <GIC_SPI 243 IRQ_
450 clocks = <&k3_clks 82 1>;
451 clock-names = "fck";
452 assigned-clocks = <&k3_clks 82
453 assigned-clock-parents = <&k3_
454 power-domains = <&k3_pds 82 TI
455 ti,timer-pwm;
456 };
457
458 main_uart0: serial@2800000 {
459 compatible = "ti,j721e-uart",
460 reg = <0x00 0x02800000 0x00 0x
461 interrupts = <GIC_SPI 192 IRQ_
462 clocks = <&k3_clks 146 3>;
463 clock-names = "fclk";
464 power-domains = <&k3_pds 146 T
465 status = "disabled";
466 };
467
468 main_uart1: serial@2810000 {
469 compatible = "ti,j721e-uart",
470 reg = <0x00 0x02810000 0x00 0x
471 interrupts = <GIC_SPI 193 IRQ_
472 clocks = <&k3_clks 350 3>;
473 clock-names = "fclk";
474 power-domains = <&k3_pds 350 T
475 status = "disabled";
476 };
477
478 main_uart2: serial@2820000 {
479 compatible = "ti,j721e-uart",
480 reg = <0x00 0x02820000 0x00 0x
481 interrupts = <GIC_SPI 194 IRQ_
482 clocks = <&k3_clks 351 3>;
483 clock-names = "fclk";
484 power-domains = <&k3_pds 351 T
485 status = "disabled";
486 };
487
488 main_uart3: serial@2830000 {
489 compatible = "ti,j721e-uart",
490 reg = <0x00 0x02830000 0x00 0x
491 interrupts = <GIC_SPI 195 IRQ_
492 clocks = <&k3_clks 352 3>;
493 clock-names = "fclk";
494 power-domains = <&k3_pds 352 T
495 status = "disabled";
496 };
497
498 main_uart4: serial@2840000 {
499 compatible = "ti,j721e-uart",
500 reg = <0x00 0x02840000 0x00 0x
501 interrupts = <GIC_SPI 196 IRQ_
502 clocks = <&k3_clks 353 3>;
503 clock-names = "fclk";
504 power-domains = <&k3_pds 353 T
505 status = "disabled";
506 };
507
508 main_uart5: serial@2850000 {
509 compatible = "ti,j721e-uart",
510 reg = <0x00 0x02850000 0x00 0x
511 interrupts = <GIC_SPI 197 IRQ_
512 clocks = <&k3_clks 354 3>;
513 clock-names = "fclk";
514 power-domains = <&k3_pds 354 T
515 status = "disabled";
516 };
517
518 main_uart6: serial@2860000 {
519 compatible = "ti,j721e-uart",
520 reg = <0x00 0x02860000 0x00 0x
521 interrupts = <GIC_SPI 198 IRQ_
522 clocks = <&k3_clks 355 3>;
523 clock-names = "fclk";
524 power-domains = <&k3_pds 355 T
525 status = "disabled";
526 };
527
528 main_uart7: serial@2870000 {
529 compatible = "ti,j721e-uart",
530 reg = <0x00 0x02870000 0x00 0x
531 interrupts = <GIC_SPI 199 IRQ_
532 clocks = <&k3_clks 356 3>;
533 clock-names = "fclk";
534 power-domains = <&k3_pds 356 T
535 status = "disabled";
536 };
537
538 main_uart8: serial@2880000 {
539 compatible = "ti,j721e-uart",
540 reg = <0x00 0x02880000 0x00 0x
541 interrupts = <GIC_SPI 248 IRQ_
542 clocks = <&k3_clks 357 3>;
543 clock-names = "fclk";
544 power-domains = <&k3_pds 357 T
545 status = "disabled";
546 };
547
548 main_uart9: serial@2890000 {
549 compatible = "ti,j721e-uart",
550 reg = <0x00 0x02890000 0x00 0x
551 interrupts = <GIC_SPI 249 IRQ_
552 clocks = <&k3_clks 358 3>;
553 clock-names = "fclk";
554 power-domains = <&k3_pds 358 T
555 status = "disabled";
556 };
557
558 main_gpio0: gpio@600000 {
559 compatible = "ti,j721e-gpio",
560 reg = <0x00 0x00600000 0x00 0x
561 gpio-controller;
562 #gpio-cells = <2>;
563 interrupt-parent = <&main_gpio
564 interrupts = <145>, <146>, <14
565 interrupt-controller;
566 #interrupt-cells = <2>;
567 ti,ngpio = <66>;
568 ti,davinci-gpio-unbanked = <0>
569 power-domains = <&k3_pds 111 T
570 clocks = <&k3_clks 111 0>;
571 clock-names = "gpio";
572 status = "disabled";
573 };
574
575 main_gpio2: gpio@610000 {
576 compatible = "ti,j721e-gpio",
577 reg = <0x00 0x00610000 0x00 0x
578 gpio-controller;
579 #gpio-cells = <2>;
580 interrupt-parent = <&main_gpio
581 interrupts = <154>, <155>, <15
582 interrupt-controller;
583 #interrupt-cells = <2>;
584 ti,ngpio = <66>;
585 ti,davinci-gpio-unbanked = <0>
586 power-domains = <&k3_pds 112 T
587 clocks = <&k3_clks 112 0>;
588 clock-names = "gpio";
589 status = "disabled";
590 };
591
592 main_gpio4: gpio@620000 {
593 compatible = "ti,j721e-gpio",
594 reg = <0x00 0x00620000 0x00 0x
595 gpio-controller;
596 #gpio-cells = <2>;
597 interrupt-parent = <&main_gpio
598 interrupts = <163>, <164>, <16
599 interrupt-controller;
600 #interrupt-cells = <2>;
601 ti,ngpio = <66>;
602 ti,davinci-gpio-unbanked = <0>
603 power-domains = <&k3_pds 113 T
604 clocks = <&k3_clks 113 0>;
605 clock-names = "gpio";
606 status = "disabled";
607 };
608
609 main_gpio6: gpio@630000 {
610 compatible = "ti,j721e-gpio",
611 reg = <0x00 0x00630000 0x00 0x
612 gpio-controller;
613 #gpio-cells = <2>;
614 interrupt-parent = <&main_gpio
615 interrupts = <172>, <173>, <17
616 interrupt-controller;
617 #interrupt-cells = <2>;
618 ti,ngpio = <66>;
619 ti,davinci-gpio-unbanked = <0>
620 power-domains = <&k3_pds 114 T
621 clocks = <&k3_clks 114 0>;
622 clock-names = "gpio";
623 status = "disabled";
624 };
625
626 main_i2c0: i2c@2000000 {
627 compatible = "ti,j721e-i2c", "
628 reg = <0x00 0x02000000 0x00 0x
629 interrupts = <GIC_SPI 200 IRQ_
630 #address-cells = <1>;
631 #size-cells = <0>;
632 clocks = <&k3_clks 214 1>;
633 clock-names = "fck";
634 power-domains = <&k3_pds 214 T
635 };
636
637 main_i2c1: i2c@2010000 {
638 compatible = "ti,j721e-i2c", "
639 reg = <0x00 0x02010000 0x00 0x
640 interrupts = <GIC_SPI 201 IRQ_
641 #address-cells = <1>;
642 #size-cells = <0>;
643 clocks = <&k3_clks 215 1>;
644 clock-names = "fck";
645 power-domains = <&k3_pds 215 T
646 status = "disabled";
647 };
648
649 main_i2c2: i2c@2020000 {
650 compatible = "ti,j721e-i2c", "
651 reg = <0x00 0x02020000 0x00 0x
652 interrupts = <GIC_SPI 202 IRQ_
653 #address-cells = <1>;
654 #size-cells = <0>;
655 clocks = <&k3_clks 216 1>;
656 clock-names = "fck";
657 power-domains = <&k3_pds 216 T
658 status = "disabled";
659 };
660
661 main_i2c3: i2c@2030000 {
662 compatible = "ti,j721e-i2c", "
663 reg = <0x00 0x02030000 0x00 0x
664 interrupts = <GIC_SPI 203 IRQ_
665 #address-cells = <1>;
666 #size-cells = <0>;
667 clocks = <&k3_clks 217 1>;
668 clock-names = "fck";
669 power-domains = <&k3_pds 217 T
670 status = "disabled";
671 };
672
673 main_i2c4: i2c@2040000 {
674 compatible = "ti,j721e-i2c", "
675 reg = <0x00 0x02040000 0x00 0x
676 interrupts = <GIC_SPI 204 IRQ_
677 #address-cells = <1>;
678 #size-cells = <0>;
679 clocks = <&k3_clks 218 1>;
680 clock-names = "fck";
681 power-domains = <&k3_pds 218 T
682 status = "disabled";
683 };
684
685 main_i2c5: i2c@2050000 {
686 compatible = "ti,j721e-i2c", "
687 reg = <0x00 0x02050000 0x00 0x
688 interrupts = <GIC_SPI 205 IRQ_
689 #address-cells = <1>;
690 #size-cells = <0>;
691 clocks = <&k3_clks 219 1>;
692 clock-names = "fck";
693 power-domains = <&k3_pds 219 T
694 status = "disabled";
695 };
696
697 main_i2c6: i2c@2060000 {
698 compatible = "ti,j721e-i2c", "
699 reg = <0x00 0x02060000 0x00 0x
700 interrupts = <GIC_SPI 206 IRQ_
701 #address-cells = <1>;
702 #size-cells = <0>;
703 clocks = <&k3_clks 220 1>;
704 clock-names = "fck";
705 power-domains = <&k3_pds 220 T
706 status = "disabled";
707 };
708
709 vpu: video-codec@4210000 {
710 compatible = "ti,j721s2-wave52
711 reg = <0x00 0x4210000 0x00 0x1
712 interrupts = <GIC_SPI 182 IRQ_
713 clocks = <&k3_clks 179 2>;
714 power-domains = <&k3_pds 179 T
715 };
716
717 main_sdhci0: mmc@4f80000 {
718 compatible = "ti,j721e-sdhci-8
719 reg = <0x00 0x04f80000 0x00 0x
720 <0x00 0x04f88000 0x00 0x
721 interrupts = <GIC_SPI 3 IRQ_TY
722 power-domains = <&k3_pds 98 TI
723 clocks = <&k3_clks 98 7>, <&k3
724 clock-names = "clk_ahb", "clk_
725 assigned-clocks = <&k3_clks 98
726 assigned-clock-parents = <&k3_
727 bus-width = <8>;
728 ti,otap-del-sel-legacy = <0x0>
729 ti,otap-del-sel-mmc-hs = <0x0>
730 ti,otap-del-sel-ddr52 = <0x6>;
731 ti,otap-del-sel-hs200 = <0x8>;
732 ti,otap-del-sel-hs400 = <0x5>;
733 ti,itap-del-sel-legacy = <0x10
734 ti,itap-del-sel-mmc-hs = <0xa>
735 ti,strobe-sel = <0x77>;
736 ti,clkbuf-sel = <0x7>;
737 ti,trm-icp = <0x8>;
738 mmc-ddr-1_8v;
739 mmc-hs200-1_8v;
740 mmc-hs400-1_8v;
741 dma-coherent;
742 status = "disabled";
743 };
744
745 main_sdhci1: mmc@4fb0000 {
746 compatible = "ti,j721e-sdhci-4
747 reg = <0x00 0x04fb0000 0x00 0x
748 <0x00 0x04fb8000 0x00 0x
749 interrupts = <GIC_SPI 4 IRQ_TY
750 power-domains = <&k3_pds 99 TI
751 clocks = <&k3_clks 99 8>, <&k3
752 clock-names = "clk_ahb", "clk_
753 assigned-clocks = <&k3_clks 99
754 assigned-clock-parents = <&k3_
755 bus-width = <4>;
756 ti,otap-del-sel-legacy = <0x0>
757 ti,otap-del-sel-sd-hs = <0x0>;
758 ti,otap-del-sel-sdr12 = <0xf>;
759 ti,otap-del-sel-sdr25 = <0xf>;
760 ti,otap-del-sel-sdr50 = <0xc>;
761 ti,otap-del-sel-sdr104 = <0x5>
762 ti,otap-del-sel-ddr50 = <0xc>;
763 ti,itap-del-sel-legacy = <0x0>
764 ti,itap-del-sel-sd-hs = <0x0>;
765 ti,itap-del-sel-sdr12 = <0x0>;
766 ti,itap-del-sel-sdr25 = <0x0>;
767 ti,itap-del-sel-ddr50 = <0x2>;
768 ti,clkbuf-sel = <0x7>;
769 ti,trm-icp = <0x8>;
770 dma-coherent;
771 status = "disabled";
772 };
773
774 main_navss: bus@30000000 {
775 compatible = "simple-bus";
776 #address-cells = <2>;
777 #size-cells = <2>;
778 ranges = <0x00 0x30000000 0x00
779 ti,sci-dev-id = <224>;
780 dma-coherent;
781 dma-ranges;
782
783 main_navss_intr: interrupt-con
784 compatible = "ti,sci-i
785 reg = <0x00 0x310e0000
786 ti,intr-trigger-type =
787 interrupt-controller;
788 interrupt-parent = <&g
789 #interrupt-cells = <1>
790 ti,sci = <&sms>;
791 ti,sci-dev-id = <227>;
792 ti,interrupt-ranges =
793
794
795 };
796
797 main_udmass_inta: msi-controll
798 compatible = "ti,sci-i
799 reg = <0x00 0x33d00000
800 interrupt-controller;
801 #interrupt-cells = <0>
802 interrupt-parent = <&m
803 msi-controller;
804 ti,sci = <&sms>;
805 ti,sci-dev-id = <265>;
806 ti,interrupt-ranges =
807 ti,unmapped-event-sour
808 };
809
810 secure_proxy_main: mailbox@32c
811 compatible = "ti,am654
812 #mbox-cells = <1>;
813 reg-names = "target_da
814 reg = <0x00 0x32c00000
815 <0x00 0x32400000
816 <0x00 0x32800000
817 interrupt-names = "rx_
818 interrupts = <GIC_SPI
819 };
820
821 hwspinlock: spinlock@30e00000
822 compatible = "ti,am654
823 reg = <0x00 0x30e00000
824 #hwlock-cells = <1>;
825 };
826
827 mailbox0_cluster0: mailbox@31f
828 compatible = "ti,am654
829 reg = <0x00 0x31f80000
830 #mbox-cells = <1>;
831 ti,mbox-num-users = <4
832 ti,mbox-num-fifos = <1
833 interrupt-parent = <&m
834 status = "disabled";
835 };
836
837 mailbox0_cluster1: mailbox@31f
838 compatible = "ti,am654
839 reg = <0x00 0x31f81000
840 #mbox-cells = <1>;
841 ti,mbox-num-users = <4
842 ti,mbox-num-fifos = <1
843 interrupt-parent = <&m
844 status = "disabled";
845 };
846
847 mailbox0_cluster2: mailbox@31f
848 compatible = "ti,am654
849 reg = <0x00 0x31f82000
850 #mbox-cells = <1>;
851 ti,mbox-num-users = <4
852 ti,mbox-num-fifos = <1
853 interrupt-parent = <&m
854 status = "disabled";
855 };
856
857 mailbox0_cluster3: mailbox@31f
858 compatible = "ti,am654
859 reg = <0x00 0x31f83000
860 #mbox-cells = <1>;
861 ti,mbox-num-users = <4
862 ti,mbox-num-fifos = <1
863 interrupt-parent = <&m
864 status = "disabled";
865 };
866
867 mailbox0_cluster4: mailbox@31f
868 compatible = "ti,am654
869 reg = <0x00 0x31f84000
870 #mbox-cells = <1>;
871 ti,mbox-num-users = <4
872 ti,mbox-num-fifos = <1
873 interrupt-parent = <&m
874 status = "disabled";
875 };
876
877 mailbox0_cluster5: mailbox@31f
878 compatible = "ti,am654
879 reg = <0x00 0x31f85000
880 #mbox-cells = <1>;
881 ti,mbox-num-users = <4
882 ti,mbox-num-fifos = <1
883 interrupt-parent = <&m
884 status = "disabled";
885 };
886
887 mailbox0_cluster6: mailbox@31f
888 compatible = "ti,am654
889 reg = <0x00 0x31f86000
890 #mbox-cells = <1>;
891 ti,mbox-num-users = <4
892 ti,mbox-num-fifos = <1
893 interrupt-parent = <&m
894 status = "disabled";
895 };
896
897 mailbox0_cluster7: mailbox@31f
898 compatible = "ti,am654
899 reg = <0x00 0x31f87000
900 #mbox-cells = <1>;
901 ti,mbox-num-users = <4
902 ti,mbox-num-fifos = <1
903 interrupt-parent = <&m
904 status = "disabled";
905 };
906
907 mailbox0_cluster8: mailbox@31f
908 compatible = "ti,am654
909 reg = <0x00 0x31f88000
910 #mbox-cells = <1>;
911 ti,mbox-num-users = <4
912 ti,mbox-num-fifos = <1
913 interrupt-parent = <&m
914 status = "disabled";
915 };
916
917 mailbox0_cluster9: mailbox@31f
918 compatible = "ti,am654
919 reg = <0x00 0x31f89000
920 #mbox-cells = <1>;
921 ti,mbox-num-users = <4
922 ti,mbox-num-fifos = <1
923 interrupt-parent = <&m
924 status = "disabled";
925 };
926
927 mailbox0_cluster10: mailbox@31
928 compatible = "ti,am654
929 reg = <0x00 0x31f8a000
930 #mbox-cells = <1>;
931 ti,mbox-num-users = <4
932 ti,mbox-num-fifos = <1
933 interrupt-parent = <&m
934 status = "disabled";
935 };
936
937 mailbox0_cluster11: mailbox@31
938 compatible = "ti,am654
939 reg = <0x00 0x31f8b000
940 #mbox-cells = <1>;
941 ti,mbox-num-users = <4
942 ti,mbox-num-fifos = <1
943 interrupt-parent = <&m
944 status = "disabled";
945 };
946
947 mailbox1_cluster0: mailbox@31f
948 compatible = "ti,am654
949 reg = <0x00 0x31f90000
950 #mbox-cells = <1>;
951 ti,mbox-num-users = <4
952 ti,mbox-num-fifos = <1
953 interrupt-parent = <&m
954 status = "disabled";
955 };
956
957 mailbox1_cluster1: mailbox@31f
958 compatible = "ti,am654
959 reg = <0x00 0x31f91000
960 #mbox-cells = <1>;
961 ti,mbox-num-users = <4
962 ti,mbox-num-fifos = <1
963 interrupt-parent = <&m
964 status = "disabled";
965 };
966
967 mailbox1_cluster2: mailbox@31f
968 compatible = "ti,am654
969 reg = <0x00 0x31f92000
970 #mbox-cells = <1>;
971 ti,mbox-num-users = <4
972 ti,mbox-num-fifos = <1
973 interrupt-parent = <&m
974 status = "disabled";
975 };
976
977 mailbox1_cluster3: mailbox@31f
978 compatible = "ti,am654
979 reg = <0x00 0x31f93000
980 #mbox-cells = <1>;
981 ti,mbox-num-users = <4
982 ti,mbox-num-fifos = <1
983 interrupt-parent = <&m
984 status = "disabled";
985 };
986
987 mailbox1_cluster4: mailbox@31f
988 compatible = "ti,am654
989 reg = <0x00 0x31f94000
990 #mbox-cells = <1>;
991 ti,mbox-num-users = <4
992 ti,mbox-num-fifos = <1
993 interrupt-parent = <&m
994 status = "disabled";
995 };
996
997 mailbox1_cluster5: mailbox@31f
998 compatible = "ti,am654
999 reg = <0x00 0x31f95000
1000 #mbox-cells = <1>;
1001 ti,mbox-num-users = <
1002 ti,mbox-num-fifos = <
1003 interrupt-parent = <&
1004 status = "disabled";
1005 };
1006
1007 mailbox1_cluster6: mailbox@31
1008 compatible = "ti,am65
1009 reg = <0x00 0x31f9600
1010 #mbox-cells = <1>;
1011 ti,mbox-num-users = <
1012 ti,mbox-num-fifos = <
1013 interrupt-parent = <&
1014 status = "disabled";
1015 };
1016
1017 mailbox1_cluster7: mailbox@31
1018 compatible = "ti,am65
1019 reg = <0x00 0x31f9700
1020 #mbox-cells = <1>;
1021 ti,mbox-num-users = <
1022 ti,mbox-num-fifos = <
1023 interrupt-parent = <&
1024 status = "disabled";
1025 };
1026
1027 mailbox1_cluster8: mailbox@31
1028 compatible = "ti,am65
1029 reg = <0x00 0x31f9800
1030 #mbox-cells = <1>;
1031 ti,mbox-num-users = <
1032 ti,mbox-num-fifos = <
1033 interrupt-parent = <&
1034 status = "disabled";
1035 };
1036
1037 mailbox1_cluster9: mailbox@31
1038 compatible = "ti,am65
1039 reg = <0x00 0x31f9900
1040 #mbox-cells = <1>;
1041 ti,mbox-num-users = <
1042 ti,mbox-num-fifos = <
1043 interrupt-parent = <&
1044 status = "disabled";
1045 };
1046
1047 mailbox1_cluster10: mailbox@3
1048 compatible = "ti,am65
1049 reg = <0x00 0x31f9a00
1050 #mbox-cells = <1>;
1051 ti,mbox-num-users = <
1052 ti,mbox-num-fifos = <
1053 interrupt-parent = <&
1054 status = "disabled";
1055 };
1056
1057 mailbox1_cluster11: mailbox@3
1058 compatible = "ti,am65
1059 reg = <0x00 0x31f9b00
1060 #mbox-cells = <1>;
1061 ti,mbox-num-users = <
1062 ti,mbox-num-fifos = <
1063 interrupt-parent = <&
1064 status = "disabled";
1065 };
1066
1067 main_ringacc: ringacc@3c00000
1068 compatible = "ti,am65
1069 reg = <0x0 0x3c000000
1070 <0x0 0x38000000
1071 <0x0 0x31120000
1072 <0x0 0x33000000
1073 <0x0 0x31080000
1074 reg-names = "rt", "fi
1075 ti,num-rings = <1024>
1076 ti,sci-rm-range-gp-ri
1077 ti,sci = <&sms>;
1078 ti,sci-dev-id = <259>
1079 msi-parent = <&main_u
1080 };
1081
1082 main_udmap: dma-controller@31
1083 compatible = "ti,j721
1084 reg = <0x0 0x31150000
1085 <0x0 0x34000000
1086 <0x0 0x35000000
1087 <0x0 0x30b00000
1088 <0x0 0x30c00000
1089 <0x0 0x30d00000
1090 reg-names = "gcfg", "
1091 "tchan",
1092 msi-parent = <&main_u
1093 #dma-cells = <1>;
1094
1095 ti,sci = <&sms>;
1096 ti,sci-dev-id = <263>
1097 ti,ringacc = <&main_r
1098
1099 ti,sci-rm-range-tchan
1100
1101
1102 ti,sci-rm-range-rchan
1103
1104
1105 ti,sci-rm-range-rflow
1106 };
1107
1108 main_bcdma_csi: dma-controlle
1109 compatible = "ti,j721
1110 reg = <0x00 0x311a000
1111 <0x00 0x35d0000
1112 <0x00 0x35c0000
1113 <0x00 0x35e0000
1114 reg-names = "gcfg", "
1115 msi-parent = <&main_u
1116 #dma-cells = <3>;
1117 ti,sci = <&sms>;
1118 ti,sci-dev-id = <225>
1119 ti,sci-rm-range-rchan
1120 ti,sci-rm-range-tchan
1121 };
1122
1123 cpts@310d0000 {
1124 compatible = "ti,j721
1125 reg = <0x0 0x310d0000
1126 reg-names = "cpts";
1127 clocks = <&k3_clks 22
1128 clock-names = "cpts";
1129 assigned-clocks = <&k
1130 assigned-clock-parent
1131 interrupts-extended =
1132 interrupt-names = "cp
1133 ti,cpts-periodic-outp
1134 ti,cpts-ext-ts-inputs
1135 };
1136 };
1137
1138 main_cpsw: ethernet@c200000 {
1139 compatible = "ti,j721e-cpsw-n
1140 reg = <0x00 0xc200000 0x00 0x
1141 reg-names = "cpsw_nuss";
1142 ranges = <0x0 0x0 0x0 0xc2000
1143 #address-cells = <2>;
1144 #size-cells = <2>;
1145 dma-coherent;
1146 clocks = <&k3_clks 28 28>;
1147 clock-names = "fck";
1148 power-domains = <&k3_pds 28 T
1149
1150 dmas = <&main_udmap 0xc640>,
1151 <&main_udmap 0xc641>,
1152 <&main_udmap 0xc642>,
1153 <&main_udmap 0xc643>,
1154 <&main_udmap 0xc644>,
1155 <&main_udmap 0xc645>,
1156 <&main_udmap 0xc646>,
1157 <&main_udmap 0xc647>,
1158 <&main_udmap 0x4640>;
1159 dma-names = "tx0", "tx1", "tx
1160 "tx4", "tx5", "tx
1161 "rx";
1162
1163 status = "disabled";
1164
1165 ethernet-ports {
1166 #address-cells = <1>;
1167 #size-cells = <0>;
1168
1169 main_cpsw_port1: port
1170 reg = <1>;
1171 ti,mac-only;
1172 label = "port
1173 phys = <&phy_
1174 status = "dis
1175 };
1176 };
1177
1178 main_cpsw_mdio: mdio@f00 {
1179 compatible = "ti,cpsw
1180 reg = <0x00 0xf00 0x0
1181 #address-cells = <1>;
1182 #size-cells = <0>;
1183 clocks = <&k3_clks 28
1184 clock-names = "fck";
1185 bus_freq = <1000000>;
1186 status = "disabled";
1187 };
1188
1189 cpts@3d000 {
1190 compatible = "ti,am65
1191 reg = <0x00 0x3d000 0
1192 clocks = <&k3_clks 28
1193 clock-names = "cpts";
1194 interrupts-extended =
1195 interrupt-names = "cp
1196 ti,cpts-ext-ts-inputs
1197 ti,cpts-periodic-outp
1198 };
1199 };
1200
1201 usbss0: cdns-usb@4104000 {
1202 compatible = "ti,j721e-usb";
1203 reg = <0x00 0x04104000 0x00 0
1204 clocks = <&k3_clks 360 16>, <
1205 clock-names = "ref", "lpm";
1206 assigned-clocks = <&k3_clks 3
1207 assigned-clock-parents = <&k3
1208 power-domains = <&k3_pds 360
1209 #address-cells = <2>;
1210 #size-cells = <2>;
1211 ranges;
1212 dma-coherent;
1213
1214 status = "disabled"; /* Needs
1215
1216 usb0: usb@6000000 {
1217 compatible = "cdns,us
1218 reg = <0x00 0x0600000
1219 <0x00 0x0601000
1220 <0x00 0x0602000
1221 reg-names = "otg", "x
1222 interrupts = <GIC_SPI
1223 <GIC_SPI
1224 <GIC_SPI
1225 interrupt-names = "ho
1226 maximum-speed = "supe
1227 dr_mode = "otg";
1228 };
1229 };
1230
1231 ti_csi2rx0: ticsi2rx@4500000 {
1232 compatible = "ti,j721e-csi2rx
1233 reg = <0x00 0x04500000 0x00 0
1234 ranges;
1235 #address-cells = <2>;
1236 #size-cells = <2>;
1237 dmas = <&main_bcdma_csi 0 0x4
1238 dma-names = "rx0";
1239 power-domains = <&k3_pds 38 T
1240 status = "disabled";
1241
1242 cdns_csi2rx0: csi-bridge@4504
1243 compatible = "ti,j721
1244 reg = <0x00 0x0450400
1245 clocks = <&k3_clks 38
1246 <&k3_clks 38
1247 clock-names = "sys_cl
1248 "pixel_if1_cl
1249 phys = <&dphy0>;
1250 phy-names = "dphy";
1251
1252 ports {
1253 #address-cell
1254 #size-cells =
1255
1256 csi0_port0: p
1257 reg =
1258 statu
1259 };
1260
1261 csi0_port1: p
1262 reg =
1263 statu
1264 };
1265
1266 csi0_port2: p
1267 reg =
1268 statu
1269 };
1270
1271 csi0_port3: p
1272 reg =
1273 statu
1274 };
1275
1276 csi0_port4: p
1277 reg =
1278 statu
1279 };
1280 };
1281 };
1282 };
1283
1284 ti_csi2rx1: ticsi2rx@4510000 {
1285 compatible = "ti,j721e-csi2rx
1286 reg = <0x00 0x04510000 0x00 0
1287 ranges;
1288 #address-cells = <2>;
1289 #size-cells = <2>;
1290 dmas = <&main_bcdma_csi 0 0x4
1291 dma-names = "rx0";
1292 power-domains = <&k3_pds 39 T
1293 status = "disabled";
1294
1295 cdns_csi2rx1: csi-bridge@4514
1296 compatible = "ti,j721
1297 reg = <0x00 0x0451400
1298 clocks = <&k3_clks 39
1299 <&k3_clks 39
1300 clock-names = "sys_cl
1301 "pixel_if1_cl
1302 phys = <&dphy1>;
1303 phy-names = "dphy";
1304
1305 ports {
1306 #address-cell
1307 #size-cells =
1308
1309 csi1_port0: p
1310 reg =
1311 statu
1312 };
1313
1314 csi1_port1: p
1315 reg =
1316 statu
1317 };
1318
1319 csi1_port2: p
1320 reg =
1321 statu
1322 };
1323
1324 csi1_port3: p
1325 reg =
1326 statu
1327 };
1328
1329 csi1_port4: p
1330 reg =
1331 statu
1332 };
1333 };
1334 };
1335 };
1336
1337 dphy0: phy@4580000 {
1338 compatible = "cdns,dphy-rx";
1339 reg = <0x00 0x04580000 0x00 0
1340 #phy-cells = <0>;
1341 power-domains = <&k3_pds 152
1342 status = "disabled";
1343 };
1344
1345 dphy1: phy@4590000 {
1346 compatible = "cdns,dphy-rx";
1347 reg = <0x00 0x04590000 0x00 0
1348 #phy-cells = <0>;
1349 power-domains = <&k3_pds 153
1350 status = "disabled";
1351 };
1352
1353 serdes_wiz0: wiz@5060000 {
1354 compatible = "ti,j721s2-wiz-1
1355 #address-cells = <1>;
1356 #size-cells = <1>;
1357 power-domains = <&k3_pds 365
1358 clocks = <&k3_clks 365 0>, <&
1359 clock-names = "fck", "core_re
1360 num-lanes = <4>;
1361 #reset-cells = <1>;
1362 #clock-cells = <1>;
1363 ranges = <0x5060000 0x0 0x506
1364
1365 assigned-clocks = <&k3_clks 3
1366 assigned-clock-parents = <&k3
1367
1368 serdes0: serdes@5060000 {
1369 compatible = "ti,j721
1370 reg = <0x05060000 0x0
1371 reg-names = "torrent_
1372 resets = <&serdes_wiz
1373 reset-names = "torren
1374 clocks = <&serdes_wiz
1375 <&serdes_wiz
1376 clock-names = "refclk
1377 assigned-clocks = <&s
1378 <&s
1379 <&s
1380 assigned-clock-parent
1381
1382
1383 #address-cells = <1>;
1384 #size-cells = <0>;
1385 #clock-cells = <1>;
1386
1387 status = "disabled";
1388 };
1389 };
1390
1391 pcie1_rc: pcie@2910000 {
1392 compatible = "ti,j7200-pcie-h
1393 reg = <0x00 0x02910000 0x00 0
1394 <0x00 0x02917000 0x00 0
1395 <0x00 0x0d800000 0x00 0
1396 <0x00 0x18000000 0x00 0
1397 reg-names = "intd_cfg", "user
1398 interrupt-names = "link_state
1399 interrupts = <GIC_SPI 330 IRQ
1400 device_type = "pci";
1401 ti,syscon-pcie-ctrl = <&scm_c
1402 max-link-speed = <3>;
1403 num-lanes = <4>;
1404 power-domains = <&k3_pds 276
1405 clocks = <&k3_clks 276 41>;
1406 clock-names = "fck";
1407 #address-cells = <3>;
1408 #size-cells = <2>;
1409 bus-range = <0x0 0xff>;
1410 vendor-id = <0x104c>;
1411 device-id = <0xb013>;
1412 msi-map = <0x0 &gic_its 0x0 0
1413 dma-coherent;
1414 ranges = <0x01000000 0x0 0x18
1415 <0x02000000 0x0 0x18
1416 dma-ranges = <0x02000000 0x0
1417 #interrupt-cells = <1>;
1418 interrupt-map-mask = <0 0 0 7
1419 interrupt-map = <0 0 0 1 &pci
1420 <0 0 0 2 &pci
1421 <0 0 0 3 &pci
1422 <0 0 0 4 &pci
1423
1424 status = "disabled"; /* Needs
1425
1426 pcie1_intc: interrupt-control
1427 interrupt-controller;
1428 #interrupt-cells = <1
1429 interrupt-parent = <&
1430 interrupts = <GIC_SPI
1431 };
1432 };
1433
1434 main_mcan0: can@2701000 {
1435 compatible = "bosch,m_can";
1436 reg = <0x00 0x02701000 0x00 0
1437 <0x00 0x02708000 0x00 0
1438 reg-names = "m_can", "message
1439 power-domains = <&k3_pds 182
1440 clocks = <&k3_clks 182 0>, <&
1441 clock-names = "hclk", "cclk";
1442 interrupts = <GIC_SPI 124 IRQ
1443 <GIC_SPI 125 IRQ
1444 interrupt-names = "int0", "in
1445 bosch,mram-cfg = <0x0 128 64
1446 status = "disabled";
1447 };
1448
1449 main_mcan1: can@2711000 {
1450 compatible = "bosch,m_can";
1451 reg = <0x00 0x02711000 0x00 0
1452 <0x00 0x02718000 0x00 0
1453 reg-names = "m_can", "message
1454 power-domains = <&k3_pds 183
1455 clocks = <&k3_clks 183 0>, <&
1456 clock-names = "hclk", "cclk";
1457 interrupts = <GIC_SPI 127 IRQ
1458 <GIC_SPI 128 IRQ
1459 interrupt-names = "int0", "in
1460 bosch,mram-cfg = <0x0 128 64
1461 status = "disabled";
1462 };
1463
1464 main_mcan2: can@2721000 {
1465 compatible = "bosch,m_can";
1466 reg = <0x00 0x02721000 0x00 0
1467 <0x00 0x02728000 0x00 0
1468 reg-names = "m_can", "message
1469 power-domains = <&k3_pds 184
1470 clocks = <&k3_clks 184 0>, <&
1471 clock-names = "hclk", "cclk";
1472 interrupts = <GIC_SPI 130 IRQ
1473 <GIC_SPI 131 IRQ
1474 interrupt-names = "int0", "in
1475 bosch,mram-cfg = <0x0 128 64
1476 status = "disabled";
1477 };
1478
1479 main_mcan3: can@2731000 {
1480 compatible = "bosch,m_can";
1481 reg = <0x00 0x02731000 0x00 0
1482 <0x00 0x02738000 0x00 0
1483 reg-names = "m_can", "message
1484 power-domains = <&k3_pds 185
1485 clocks = <&k3_clks 185 0>, <&
1486 clock-names = "hclk", "cclk";
1487 interrupts = <GIC_SPI 133 IRQ
1488 <GIC_SPI 134 IRQ
1489 interrupt-names = "int0", "in
1490 bosch,mram-cfg = <0x0 128 64
1491 status = "disabled";
1492 };
1493
1494 main_mcan4: can@2741000 {
1495 compatible = "bosch,m_can";
1496 reg = <0x00 0x02741000 0x00 0
1497 <0x00 0x02748000 0x00 0
1498 reg-names = "m_can", "message
1499 power-domains = <&k3_pds 186
1500 clocks = <&k3_clks 186 0>, <&
1501 clock-names = "hclk", "cclk";
1502 interrupts = <GIC_SPI 136 IRQ
1503 <GIC_SPI 137 IRQ
1504 interrupt-names = "int0", "in
1505 bosch,mram-cfg = <0x0 128 64
1506 status = "disabled";
1507 };
1508
1509 main_mcan5: can@2751000 {
1510 compatible = "bosch,m_can";
1511 reg = <0x00 0x02751000 0x00 0
1512 <0x00 0x02758000 0x00 0
1513 reg-names = "m_can", "message
1514 power-domains = <&k3_pds 187
1515 clocks = <&k3_clks 187 0>, <&
1516 clock-names = "hclk", "cclk";
1517 interrupts = <GIC_SPI 139 IRQ
1518 <GIC_SPI 140 IRQ
1519 interrupt-names = "int0", "in
1520 bosch,mram-cfg = <0x0 128 64
1521 status = "disabled";
1522 };
1523
1524 main_mcan6: can@2761000 {
1525 compatible = "bosch,m_can";
1526 reg = <0x00 0x02761000 0x00 0
1527 <0x00 0x02768000 0x00 0
1528 reg-names = "m_can", "message
1529 power-domains = <&k3_pds 188
1530 clocks = <&k3_clks 188 0>, <&
1531 clock-names = "hclk", "cclk";
1532 interrupts = <GIC_SPI 142 IRQ
1533 <GIC_SPI 143 IRQ
1534 interrupt-names = "int0", "in
1535 bosch,mram-cfg = <0x0 128 64
1536 status = "disabled";
1537 };
1538
1539 main_mcan7: can@2771000 {
1540 compatible = "bosch,m_can";
1541 reg = <0x00 0x02771000 0x00 0
1542 <0x00 0x02778000 0x00 0
1543 reg-names = "m_can", "message
1544 power-domains = <&k3_pds 189
1545 clocks = <&k3_clks 189 0>, <&
1546 clock-names = "hclk", "cclk";
1547 interrupts = <GIC_SPI 145 IRQ
1548 <GIC_SPI 146 IRQ
1549 interrupt-names = "int0", "in
1550 bosch,mram-cfg = <0x0 128 64
1551 status = "disabled";
1552 };
1553
1554 main_mcan8: can@2781000 {
1555 compatible = "bosch,m_can";
1556 reg = <0x00 0x02781000 0x00 0
1557 <0x00 0x02788000 0x00 0
1558 reg-names = "m_can", "message
1559 power-domains = <&k3_pds 190
1560 clocks = <&k3_clks 190 0>, <&
1561 clock-names = "hclk", "cclk";
1562 interrupts = <GIC_SPI 576 IRQ
1563 <GIC_SPI 577 IRQ
1564 interrupt-names = "int0", "in
1565 bosch,mram-cfg = <0x0 128 64
1566 status = "disabled";
1567 };
1568
1569 main_mcan9: can@2791000 {
1570 compatible = "bosch,m_can";
1571 reg = <0x00 0x02791000 0x00 0
1572 <0x00 0x02798000 0x00 0
1573 reg-names = "m_can", "message
1574 power-domains = <&k3_pds 191
1575 clocks = <&k3_clks 191 0>, <&
1576 clock-names = "hclk", "cclk";
1577 interrupts = <GIC_SPI 579 IRQ
1578 <GIC_SPI 580 IRQ
1579 interrupt-names = "int0", "in
1580 bosch,mram-cfg = <0x0 128 64
1581 status = "disabled";
1582 };
1583
1584 main_mcan10: can@27a1000 {
1585 compatible = "bosch,m_can";
1586 reg = <0x00 0x027a1000 0x00 0
1587 <0x00 0x027a8000 0x00 0
1588 reg-names = "m_can", "message
1589 power-domains = <&k3_pds 192
1590 clocks = <&k3_clks 192 0>, <&
1591 clock-names = "hclk", "cclk";
1592 interrupts = <GIC_SPI 582 IRQ
1593 <GIC_SPI 583 IRQ
1594 interrupt-names = "int0", "in
1595 bosch,mram-cfg = <0x0 128 64
1596 status = "disabled";
1597 };
1598
1599 main_mcan11: can@27b1000 {
1600 compatible = "bosch,m_can";
1601 reg = <0x00 0x027b1000 0x00 0
1602 <0x00 0x027b8000 0x00 0
1603 reg-names = "m_can", "message
1604 power-domains = <&k3_pds 193
1605 clocks = <&k3_clks 193 0>, <&
1606 clock-names = "hclk", "cclk";
1607 interrupts = <GIC_SPI 585 IRQ
1608 <GIC_SPI 586 IRQ
1609 interrupt-names = "int0", "in
1610 bosch,mram-cfg = <0x0 128 64
1611 status = "disabled";
1612 };
1613
1614 main_mcan12: can@27c1000 {
1615 compatible = "bosch,m_can";
1616 reg = <0x00 0x027c1000 0x00 0
1617 <0x00 0x027c8000 0x00 0
1618 reg-names = "m_can", "message
1619 power-domains = <&k3_pds 194
1620 clocks = <&k3_clks 194 0>, <&
1621 clock-names = "hclk", "cclk";
1622 interrupts = <GIC_SPI 588 IRQ
1623 <GIC_SPI 589 IRQ
1624 interrupt-names = "int0", "in
1625 bosch,mram-cfg = <0x0 128 64
1626 status = "disabled";
1627 };
1628
1629 main_mcan13: can@27d1000 {
1630 compatible = "bosch,m_can";
1631 reg = <0x00 0x027d1000 0x00 0
1632 <0x00 0x027d8000 0x00 0
1633 reg-names = "m_can", "message
1634 power-domains = <&k3_pds 195
1635 clocks = <&k3_clks 195 0>, <&
1636 clock-names = "hclk", "cclk";
1637 interrupts = <GIC_SPI 591 IRQ
1638 <GIC_SPI 592 IRQ
1639 interrupt-names = "int0", "in
1640 bosch,mram-cfg = <0x0 128 64
1641 status = "disabled";
1642 };
1643
1644 main_mcan14: can@2681000 {
1645 compatible = "bosch,m_can";
1646 reg = <0x00 0x02681000 0x00 0
1647 <0x00 0x02688000 0x00 0
1648 reg-names = "m_can", "message
1649 power-domains = <&k3_pds 197
1650 clocks = <&k3_clks 197 0>, <&
1651 clock-names = "hclk", "cclk";
1652 interrupts = <GIC_SPI 594 IRQ
1653 <GIC_SPI 595 IRQ
1654 interrupt-names = "int0", "in
1655 bosch,mram-cfg = <0x0 128 64
1656 status = "disabled";
1657 };
1658
1659 main_mcan15: can@2691000 {
1660 compatible = "bosch,m_can";
1661 reg = <0x00 0x02691000 0x00 0
1662 <0x00 0x02698000 0x00 0
1663 reg-names = "m_can", "message
1664 power-domains = <&k3_pds 199
1665 clocks = <&k3_clks 199 0>, <&
1666 clock-names = "hclk", "cclk";
1667 interrupts = <GIC_SPI 597 IRQ
1668 <GIC_SPI 598 IRQ
1669 interrupt-names = "int0", "in
1670 bosch,mram-cfg = <0x0 128 64
1671 status = "disabled";
1672 };
1673
1674 main_mcan16: can@26a1000 {
1675 compatible = "bosch,m_can";
1676 reg = <0x00 0x026a1000 0x00 0
1677 <0x00 0x026a8000 0x00 0
1678 reg-names = "m_can", "message
1679 power-domains = <&k3_pds 201
1680 clocks = <&k3_clks 201 0>, <&
1681 clock-names = "hclk", "cclk";
1682 interrupts = <GIC_SPI 784 IRQ
1683 <GIC_SPI 785 IRQ
1684 interrupt-names = "int0", "in
1685 bosch,mram-cfg = <0x0 128 64
1686 status = "disabled";
1687 };
1688
1689 main_mcan17: can@26b1000 {
1690 compatible = "bosch,m_can";
1691 reg = <0x00 0x026b1000 0x00 0
1692 <0x00 0x026b8000 0x00 0
1693 reg-names = "m_can", "message
1694 power-domains = <&k3_pds 206
1695 clocks = <&k3_clks 206 0>, <&
1696 clock-names = "hclk", "cclk";
1697 interrupts = <GIC_SPI 787 IRQ
1698 <GIC_SPI 788 IRQ
1699 interrupt-names = "int0", "in
1700 bosch,mram-cfg = <0x0 128 64
1701 status = "disabled";
1702 };
1703
1704 main_spi0: spi@2100000 {
1705 compatible = "ti,am654-mcspi"
1706 reg = <0x00 0x02100000 0x00 0
1707 interrupts = <GIC_SPI 184 IRQ
1708 #address-cells = <1>;
1709 #size-cells = <0>;
1710 power-domains = <&k3_pds 339
1711 clocks = <&k3_clks 339 1>;
1712 status = "disabled";
1713 };
1714
1715 main_spi1: spi@2110000 {
1716 compatible = "ti,am654-mcspi"
1717 reg = <0x00 0x02110000 0x00 0
1718 interrupts = <GIC_SPI 185 IRQ
1719 #address-cells = <1>;
1720 #size-cells = <0>;
1721 power-domains = <&k3_pds 340
1722 clocks = <&k3_clks 340 1>;
1723 status = "disabled";
1724 };
1725
1726 main_spi2: spi@2120000 {
1727 compatible = "ti,am654-mcspi"
1728 reg = <0x00 0x02120000 0x00 0
1729 interrupts = <GIC_SPI 186 IRQ
1730 #address-cells = <1>;
1731 #size-cells = <0>;
1732 power-domains = <&k3_pds 341
1733 clocks = <&k3_clks 341 1>;
1734 status = "disabled";
1735 };
1736
1737 main_spi3: spi@2130000 {
1738 compatible = "ti,am654-mcspi"
1739 reg = <0x00 0x02130000 0x00 0
1740 interrupts = <GIC_SPI 187 IRQ
1741 #address-cells = <1>;
1742 #size-cells = <0>;
1743 power-domains = <&k3_pds 342
1744 clocks = <&k3_clks 342 1>;
1745 status = "disabled";
1746 };
1747
1748 main_spi4: spi@2140000 {
1749 compatible = "ti,am654-mcspi"
1750 reg = <0x00 0x02140000 0x00 0
1751 interrupts = <GIC_SPI 188 IRQ
1752 #address-cells = <1>;
1753 #size-cells = <0>;
1754 power-domains = <&k3_pds 343
1755 clocks = <&k3_clks 343 1>;
1756 status = "disabled";
1757 };
1758
1759 main_spi5: spi@2150000 {
1760 compatible = "ti,am654-mcspi"
1761 reg = <0x00 0x02150000 0x00 0
1762 interrupts = <GIC_SPI 189 IRQ
1763 #address-cells = <1>;
1764 #size-cells = <0>;
1765 power-domains = <&k3_pds 344
1766 clocks = <&k3_clks 344 1>;
1767 status = "disabled";
1768 };
1769
1770 main_spi6: spi@2160000 {
1771 compatible = "ti,am654-mcspi"
1772 reg = <0x00 0x02160000 0x00 0
1773 interrupts = <GIC_SPI 190 IRQ
1774 #address-cells = <1>;
1775 #size-cells = <0>;
1776 power-domains = <&k3_pds 345
1777 clocks = <&k3_clks 345 1>;
1778 status = "disabled";
1779 };
1780
1781 main_spi7: spi@2170000 {
1782 compatible = "ti,am654-mcspi"
1783 reg = <0x00 0x02170000 0x00 0
1784 interrupts = <GIC_SPI 191 IRQ
1785 #address-cells = <1>;
1786 #size-cells = <0>;
1787 power-domains = <&k3_pds 346
1788 clocks = <&k3_clks 346 1>;
1789 status = "disabled";
1790 };
1791
1792 dss: dss@4a00000 {
1793 compatible = "ti,j721e-dss";
1794 reg = <0x00 0x04a00000 0x00 0
1795 <0x00 0x04a10000 0x00 0
1796 <0x00 0x04b00000 0x00 0
1797 <0x00 0x04b10000 0x00 0
1798 <0x00 0x04a20000 0x00 0
1799 <0x00 0x04a30000 0x00 0
1800 <0x00 0x04a50000 0x00 0
1801 <0x00 0x04a60000 0x00 0
1802 <0x00 0x04a70000 0x00 0
1803 <0x00 0x04a90000 0x00 0
1804 <0x00 0x04ab0000 0x00 0
1805 <0x00 0x04ad0000 0x00 0
1806 <0x00 0x04a80000 0x00 0
1807 <0x00 0x04aa0000 0x00 0
1808 <0x00 0x04ac0000 0x00 0
1809 <0x00 0x04ae0000 0x00 0
1810 <0x00 0x04af0000 0x00 0
1811 reg-names = "common_m", "comm
1812 "common_s1", "com
1813 "vidl1", "vidl2",
1814 "ovr1", "ovr2", "
1815 "vp1", "vp2", "vp
1816 "wb";
1817 clocks = <&k3_clks 158 0>,
1818 <&k3_clks 158 2>,
1819 <&k3_clks 158 5>,
1820 <&k3_clks 158 14>,
1821 <&k3_clks 158 18>;
1822 clock-names = "fck", "vp1", "
1823 power-domains = <&k3_pds 158
1824 interrupts = <GIC_SPI 602 IRQ
1825 <GIC_SPI 603 IRQ
1826 <GIC_SPI 604 IRQ
1827 <GIC_SPI 605 IRQ
1828 interrupt-names = "common_m",
1829 "common_s0"
1830 "common_s1"
1831 "common_s2"
1832 status = "disabled";
1833
1834 dss_ports: ports {
1835 };
1836 };
1837
1838 main_r5fss0: r5fss@5c00000 {
1839 compatible = "ti,j721s2-r5fss
1840 ti,cluster-mode = <1>;
1841 #address-cells = <1>;
1842 #size-cells = <1>;
1843 ranges = <0x5c00000 0x00 0x5c
1844 <0x5d00000 0x00 0x5d
1845 power-domains = <&k3_pds 277
1846
1847 main_r5fss0_core0: r5f@5c0000
1848 compatible = "ti,j721
1849 reg = <0x5c00000 0x00
1850 <0x5c10000 0x00
1851 reg-names = "atcm", "
1852 ti,sci = <&sms>;
1853 ti,sci-dev-id = <279>
1854 ti,sci-proc-ids = <0x
1855 resets = <&k3_reset 2
1856 firmware-name = "j721
1857 ti,atcm-enable = <1>;
1858 ti,btcm-enable = <1>;
1859 ti,loczrama = <1>;
1860 };
1861
1862 main_r5fss0_core1: r5f@5d0000
1863 compatible = "ti,j721
1864 reg = <0x5d00000 0x00
1865 <0x5d10000 0x00
1866 reg-names = "atcm", "
1867 ti,sci = <&sms>;
1868 ti,sci-dev-id = <280>
1869 ti,sci-proc-ids = <0x
1870 resets = <&k3_reset 2
1871 firmware-name = "j721
1872 ti,atcm-enable = <1>;
1873 ti,btcm-enable = <1>;
1874 ti,loczrama = <1>;
1875 };
1876 };
1877
1878 main_r5fss1: r5fss@5e00000 {
1879 compatible = "ti,j721s2-r5fss
1880 ti,cluster-mode = <1>;
1881 #address-cells = <1>;
1882 #size-cells = <1>;
1883 ranges = <0x5e00000 0x00 0x5e
1884 <0x5f00000 0x00 0x5f
1885 power-domains = <&k3_pds 278
1886
1887 main_r5fss1_core0: r5f@5e0000
1888 compatible = "ti,j721
1889 reg = <0x5e00000 0x00
1890 <0x5e10000 0x00
1891 reg-names = "atcm", "
1892 ti,sci = <&sms>;
1893 ti,sci-dev-id = <281>
1894 ti,sci-proc-ids = <0x
1895 resets = <&k3_reset 2
1896 firmware-name = "j721
1897 ti,atcm-enable = <1>;
1898 ti,btcm-enable = <1>;
1899 ti,loczrama = <1>;
1900 };
1901
1902 main_r5fss1_core1: r5f@5f0000
1903 compatible = "ti,j721
1904 reg = <0x5f00000 0x00
1905 <0x5f10000 0x00
1906 reg-names = "atcm", "
1907 ti,sci = <&sms>;
1908 ti,sci-dev-id = <282>
1909 ti,sci-proc-ids = <0x
1910 resets = <&k3_reset 2
1911 firmware-name = "j721
1912 ti,atcm-enable = <1>;
1913 ti,btcm-enable = <1>;
1914 ti,loczrama = <1>;
1915 };
1916 };
1917
1918 c71_0: dsp@64800000 {
1919 compatible = "ti,j721s2-c71-d
1920 reg = <0x00 0x64800000 0x00 0
1921 <0x00 0x64e00000 0x00 0
1922 reg-names = "l2sram", "l1dram
1923 ti,sci = <&sms>;
1924 ti,sci-dev-id = <8>;
1925 ti,sci-proc-ids = <0x30 0xff>
1926 resets = <&k3_reset 8 1>;
1927 firmware-name = "j721s2-c71_0
1928 status = "disabled";
1929 };
1930
1931 c71_1: dsp@65800000 {
1932 compatible = "ti,j721s2-c71-d
1933 reg = <0x00 0x65800000 0x00 0
1934 <0x00 0x65e00000 0x00 0
1935 reg-names = "l2sram", "l1dram
1936 ti,sci = <&sms>;
1937 ti,sci-dev-id = <11>;
1938 ti,sci-proc-ids = <0x31 0xff>
1939 resets = <&k3_reset 11 1>;
1940 firmware-name = "j721s2-c71_1
1941 status = "disabled";
1942 };
1943
1944 main_esm: esm@700000 {
1945 compatible = "ti,j721e-esm";
1946 reg = <0x00 0x700000 0x00 0x1
1947 ti,esm-pins = <688>, <689>;
1948 bootph-pre-ram;
1949 };
1950
1951 watchdog0: watchdog@2200000 {
1952 compatible = "ti,j7-rti-wdt";
1953 reg = <0x00 0x2200000 0x00 0x
1954 clocks = <&k3_clks 286 1>;
1955 power-domains = <&k3_pds 286
1956 assigned-clocks = <&k3_clks 2
1957 assigned-clock-parents = <&k3
1958 };
1959
1960 watchdog1: watchdog@2210000 {
1961 compatible = "ti,j7-rti-wdt";
1962 reg = <0x00 0x2210000 0x00 0x
1963 clocks = <&k3_clks 287 1>;
1964 power-domains = <&k3_pds 287
1965 assigned-clocks = <&k3_clks 2
1966 assigned-clock-parents = <&k3
1967 };
1968
1969 /*
1970 * The following RTI instances are co
1971 * GPU so keeping them reserved as th
1972 * respective firmware
1973 */
1974 watchdog2: watchdog@22f0000 {
1975 compatible = "ti,j7-rti-wdt";
1976 reg = <0x00 0x22f0000 0x00 0x
1977 clocks = <&k3_clks 290 1>;
1978 power-domains = <&k3_pds 290
1979 assigned-clocks = <&k3_clks 2
1980 assigned-clock-parents = <&k3
1981 /* reserved for GPU */
1982 status = "reserved";
1983 };
1984
1985 watchdog3: watchdog@2300000 {
1986 compatible = "ti,j7-rti-wdt";
1987 reg = <0x00 0x2300000 0x00 0x
1988 clocks = <&k3_clks 288 1>;
1989 power-domains = <&k3_pds 288
1990 assigned-clocks = <&k3_clks 2
1991 assigned-clock-parents = <&k3
1992 /* reserved for C7X_0 */
1993 status = "reserved";
1994 };
1995
1996 watchdog4: watchdog@2310000 {
1997 compatible = "ti,j7-rti-wdt";
1998 reg = <0x00 0x2310000 0x00 0x
1999 clocks = <&k3_clks 289 1>;
2000 power-domains = <&k3_pds 289
2001 assigned-clocks = <&k3_clks 2
2002 assigned-clock-parents = <&k3
2003 /* reserved for C7X_1 */
2004 status = "reserved";
2005 };
2006
2007 watchdog5: watchdog@23c0000 {
2008 compatible = "ti,j7-rti-wdt";
2009 reg = <0x00 0x23c0000 0x00 0x
2010 clocks = <&k3_clks 291 1>;
2011 power-domains = <&k3_pds 291
2012 assigned-clocks = <&k3_clks 2
2013 assigned-clock-parents = <&k3
2014 /* reserved for MAIN_R5F0_0 *
2015 status = "reserved";
2016 };
2017
2018 watchdog6: watchdog@23d0000 {
2019 compatible = "ti,j7-rti-wdt";
2020 reg = <0x00 0x23d0000 0x00 0x
2021 clocks = <&k3_clks 292 1>;
2022 power-domains = <&k3_pds 292
2023 assigned-clocks = <&k3_clks 2
2024 assigned-clock-parents = <&k3
2025 /* reserved for MAIN_R5F0_1 *
2026 status = "reserved";
2027 };
2028
2029 watchdog7: watchdog@23e0000 {
2030 compatible = "ti,j7-rti-wdt";
2031 reg = <0x00 0x23e0000 0x00 0x
2032 clocks = <&k3_clks 293 1>;
2033 power-domains = <&k3_pds 293
2034 assigned-clocks = <&k3_clks 2
2035 assigned-clock-parents = <&k3
2036 /* reserved for MAIN_R5F1_0 *
2037 status = "reserved";
2038 };
2039
2040 watchdog8: watchdog@23f0000 {
2041 compatible = "ti,j7-rti-wdt";
2042 reg = <0x00 0x23f0000 0x00 0x
2043 clocks = <&k3_clks 294 1>;
2044 power-domains = <&k3_pds 294
2045 assigned-clocks = <&k3_clks 2
2046 assigned-clock-parents = <&k3
2047 /* reserved for MAIN_R5F1_1 *
2048 status = "reserved";
2049 };
2050 };
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