1 // SPDX-License-Identifier: GPL-2.0-only OR MI
2 /*
3 * Device Tree file for the J722S EVM
4 * Copyright (C) 2024 Texas Instruments Incorp
5 *
6 * Schematics: https://www.ti.com/lit/zip/sprr
7 */
8
9 /dts-v1/;
10
11 #include <dt-bindings/net/ti-dp83867.h>
12 #include <dt-bindings/phy/phy.h>
13 #include "k3-j722s.dtsi"
14 #include "k3-serdes.h"
15
16 / {
17 compatible = "ti,j722s-evm", "ti,j722s
18 model = "Texas Instruments J722S EVM";
19
20 aliases {
21 serial0 = &wkup_uart0;
22 serial2 = &main_uart0;
23 serial3 = &main_uart5;
24 mmc0 = &sdhci0;
25 mmc1 = &sdhci1;
26 };
27
28 chosen {
29 stdout-path = &main_uart0;
30 };
31
32 memory@80000000 {
33 /* 8G RAM */
34 reg = <0x00000000 0x80000000 0
35 <0x00000008 0x80000000 0
36 device_type = "memory";
37 bootph-pre-ram;
38 };
39
40 reserved_memory: reserved-memory {
41 #address-cells = <2>;
42 #size-cells = <2>;
43 ranges;
44
45 secure_tfa_ddr: tfa@9e780000 {
46 reg = <0x00 0x9e780000
47 no-map;
48 };
49
50 secure_ddr: optee@9e800000 {
51 reg = <0x00 0x9e800000
52 no-map;
53 };
54
55 wkup_r5fss0_core0_dma_memory_r
56 compatible = "shared-d
57 reg = <0x00 0xa0000000
58 no-map;
59 };
60
61 wkup_r5fss0_core0_memory_regio
62 compatible = "shared-d
63 reg = <0x00 0xa0100000
64 no-map;
65 };
66
67 mcu_r5fss0_core0_dma_memory_re
68 compatible = "shared-d
69 reg = <0x00 0xa1000000
70 no-map;
71 };
72
73 mcu_r5fss0_core0_memory_region
74 compatible = "shared-d
75 reg = <0x00 0xa1100000
76 no-map;
77 };
78
79 main_r5fss0_core0_dma_memory_r
80 compatible = "shared-d
81 reg = <0x00 0xa2000000
82 no-map;
83 };
84
85 main_r5fss0_core0_memory_regio
86 compatible = "shared-d
87 reg = <0x00 0xa2100000
88 no-map;
89 };
90
91 c7x_0_dma_memory_region: c7x-d
92 compatible = "shared-d
93 reg = <0x00 0xa3000000
94 no-map;
95 };
96
97 c7x_0_memory_region: c7x-memor
98 compatible = "shared-d
99 reg = <0x00 0xa3100000
100 no-map;
101 };
102
103 c7x_1_dma_memory_region: c7x-d
104 compatible = "shared-d
105 reg = <0x00 0xa4000000
106 no-map;
107 };
108
109 c7x_1_memory_region: c7x-memor
110 compatible = "shared-d
111 reg = <0x00 0xa4100000
112 no-map;
113 };
114
115 rtos_ipc_memory_region: ipc-me
116 reg = <0x00 0xa5000000
117 alignment = <0x1000>;
118 no-map;
119 };
120 };
121
122 vmain_pd: regulator-0 {
123 /* TPS65988 PD CONTROLLER OUTP
124 compatible = "regulator-fixed"
125 regulator-name = "vmain_pd";
126 regulator-min-microvolt = <500
127 regulator-max-microvolt = <500
128 regulator-always-on;
129 regulator-boot-on;
130 bootph-all;
131 };
132
133 vsys_5v0: regulator-vsys5v0 {
134 /* Output of LM5140 */
135 compatible = "regulator-fixed"
136 regulator-name = "vsys_5v0";
137 regulator-min-microvolt = <500
138 regulator-max-microvolt = <500
139 vin-supply = <&vmain_pd>;
140 regulator-always-on;
141 regulator-boot-on;
142 };
143
144 vdd_mmc1: regulator-mmc1 {
145 /* TPS22918DBVR */
146 compatible = "regulator-fixed"
147 regulator-name = "vdd_mmc1";
148 regulator-min-microvolt = <330
149 regulator-max-microvolt = <330
150 regulator-boot-on;
151 enable-active-high;
152 gpio = <&exp1 15 GPIO_ACTIVE_H
153 bootph-all;
154 };
155
156 vdd_sd_dv: regulator-TLV71033 {
157 compatible = "regulator-gpio";
158 regulator-name = "tlv71033";
159 pinctrl-names = "default";
160 pinctrl-0 = <&vdd_sd_dv_pins_d
161 regulator-min-microvolt = <180
162 regulator-max-microvolt = <330
163 regulator-boot-on;
164 vin-supply = <&vsys_5v0>;
165 gpios = <&main_gpio0 70 GPIO_A
166 states = <1800000 0x0>,
167 <3300000 0x1>;
168 };
169
170 vsys_io_3v3: regulator-vsys-io-3v3 {
171 compatible = "regulator-fixed"
172 regulator-name = "vsys_io_3v3"
173 regulator-min-microvolt = <330
174 regulator-max-microvolt = <330
175 regulator-always-on;
176 regulator-boot-on;
177 };
178
179 vsys_io_1v8: regulator-vsys-io-1v8 {
180 compatible = "regulator-fixed"
181 regulator-name = "vsys_io_1v8"
182 regulator-min-microvolt = <180
183 regulator-max-microvolt = <180
184 regulator-always-on;
185 regulator-boot-on;
186 };
187
188 vsys_io_1v2: regulator-vsys-io-1v2 {
189 compatible = "regulator-fixed"
190 regulator-name = "vsys_io_1v2"
191 regulator-min-microvolt = <120
192 regulator-max-microvolt = <120
193 regulator-always-on;
194 regulator-boot-on;
195 };
196
197 codec_audio: sound {
198 compatible = "simple-audio-car
199 simple-audio-card,name = "J722
200 simple-audio-card,widgets =
201 "Headphone", "Headp
202 "Line", "Line
203 "Microphone", "Micro
204 simple-audio-card,routing =
205 "Headphone Jack",
206 "Headphone Jack",
207 "LINE1L",
208 "LINE1R",
209 "MIC3R",
210 "Microphone Jack",
211 simple-audio-card,format = "ds
212 simple-audio-card,bitclock-mas
213 simple-audio-card,frame-master
214 simple-audio-card,bitclock-inv
215
216 simple-audio-card,cpu {
217 sound-dai = <&mcasp1>;
218 };
219
220 sound_master: simple-audio-car
221 sound-dai = <&tlv320ai
222 clocks = <&audio_refcl
223 };
224 };
225
226 transceiver0: can-phy0 {
227 compatible = "ti,tcan1042";
228 #phy-cells = <0>;
229 max-bitrate = <5000000>;
230 pinctrl-names = "default";
231 pinctrl-0 = <&mcu_mcan0_gpio_p
232 standby-gpios = <&mcu_gpio0 12
233 };
234
235 transceiver1: can-phy1 {
236 compatible = "ti,tcan1042";
237 #phy-cells = <0>;
238 max-bitrate = <5000000>;
239 };
240
241 transceiver2: can-phy2 {
242 compatible = "ti,tcan1042";
243 #phy-cells = <0>;
244 max-bitrate = <5000000>;
245 standby-gpios = <&exp1 17 GPIO
246 };
247 };
248
249 &main_pmx0 {
250
251 main_mcan0_pins_default: main-mcan0-de
252 pinctrl-single,pins = <
253 J722S_IOPAD(0x1dc, PIN
254 J722S_IOPAD(0x1d8, PIN
255 >;
256 };
257
258 main_i2c0_pins_default: main-i2c0-defa
259 pinctrl-single,pins = <
260 J722S_IOPAD(0x01e0, PI
261 J722S_IOPAD(0x01e4, PI
262 >;
263 bootph-all;
264 };
265
266 main_uart0_pins_default: main-uart0-de
267 pinctrl-single,pins = <
268 J722S_IOPAD(0x01c8, PI
269 J722S_IOPAD(0x01cc, PI
270 >;
271 bootph-all;
272 };
273
274 main_uart5_pins_default: main-uart5-de
275 pinctrl-single,pins = <
276 J722S_IOPAD(0x0108, PI
277 J722S_IOPAD(0x010c, PI
278 >;
279 };
280
281 vdd_sd_dv_pins_default: vdd-sd-dv-defa
282 pinctrl-single,pins = <
283 J722S_IOPAD(0x0120, PI
284 >;
285 bootph-all;
286 };
287
288 main_mmc1_pins_default: main-mmc1-defa
289 pinctrl-single,pins = <
290 J722S_IOPAD(0x023c, PI
291 J722S_IOPAD(0x0234, PI
292 J722S_IOPAD(0x0230, PI
293 J722S_IOPAD(0x022c, PI
294 J722S_IOPAD(0x0228, PI
295 J722S_IOPAD(0x0224, PI
296 J722S_IOPAD(0x0240, PI
297 >;
298 bootph-all;
299 };
300
301 mdio_pins_default: mdio-default-pins {
302 pinctrl-single,pins = <
303 J722S_IOPAD(0x0160, PI
304 J722S_IOPAD(0x015c, PI
305 >;
306 };
307
308 ospi0_pins_default: ospi0-default-pins
309 pinctrl-single,pins = <
310 J722S_IOPAD(0x0000, PI
311 J722S_IOPAD(0x002c, PI
312 J722S_IOPAD(0x000c, PI
313 J722S_IOPAD(0x0010, PI
314 J722S_IOPAD(0x0014, PI
315 J722S_IOPAD(0x0018, PI
316 J722S_IOPAD(0x001c, PI
317 J722S_IOPAD(0x0020, PI
318 J722S_IOPAD(0x0024, PI
319 J722S_IOPAD(0x0028, PI
320 J722S_IOPAD(0x0008, PI
321 >;
322 bootph-all;
323 };
324
325 rgmii1_pins_default: rgmii1-default-pi
326 pinctrl-single,pins = <
327 J722S_IOPAD(0x014c, PI
328 J722S_IOPAD(0x0150, PI
329 J722S_IOPAD(0x0154, PI
330 J722S_IOPAD(0x0158, PI
331 J722S_IOPAD(0x0148, PI
332 J722S_IOPAD(0x0144, PI
333 J722S_IOPAD(0x0134, PI
334 J722S_IOPAD(0x0138, PI
335 J722S_IOPAD(0x013c, PI
336 J722S_IOPAD(0x0140, PI
337 J722S_IOPAD(0x0130, PI
338 J722S_IOPAD(0x012c, PI
339 >;
340 };
341
342 main_usb1_pins_default: main-usb1-defa
343 pinctrl-single,pins = <
344 J722S_IOPAD(0x0258, PI
345 >;
346 };
347
348 main_mcasp1_pins_default: main-mcasp1-
349 pinctrl-single,pins = <
350 J722S_IOPAD(0x0090, PI
351 J722S_IOPAD(0x0098, PI
352 J722S_IOPAD(0x008c, PI
353 J722S_IOPAD(0x0084, PI
354 >;
355 };
356
357 audio_ext_refclk1_pins_default: audio-
358 pinctrl-single,pins = <
359 J722S_IOPAD(0x00a0, PI
360 >;
361 };
362 };
363
364 &cpsw3g {
365 status = "okay";
366 pinctrl-names = "default";
367 pinctrl-0 = <&rgmii1_pins_default>;
368 };
369
370 &cpsw3g_mdio {
371 status = "okay";
372 pinctrl-names = "default";
373 pinctrl-0 = <&mdio_pins_default>;
374
375 cpsw3g_phy0: ethernet-phy@0 {
376 reg = <0>;
377 ti,rx-internal-delay = <DP8386
378 ti,fifo-depth = <DP83867_PHYCR
379 ti,min-output-impedance;
380 };
381 };
382
383 &cpsw_port1 {
384 phy-mode = "rgmii-rxid";
385 phy-handle = <&cpsw3g_phy0>;
386 status = "okay";
387 };
388
389 &main_gpio1 {
390 status = "okay";
391 };
392
393 &main_uart0 {
394 pinctrl-names = "default";
395 pinctrl-0 = <&main_uart0_pins_default>
396 status = "okay";
397 bootph-all;
398 };
399
400 &main_uart5 {
401 /* MAIN UART 5 is used by System firmw
402 pinctrl-names = "default";
403 pinctrl-0 = <&main_uart5_pins_default>
404 status = "reserved";
405 };
406
407 &mcu_pmx0 {
408
409 mcu_mcan0_pins_default: mcu-mcan0-defa
410 pinctrl-single,pins = <
411 J722S_MCU_IOPAD(0x038,
412 J722S_MCU_IOPAD(0x034,
413 >;
414 };
415
416 mcu_mcan1_pins_default: mcu-mcan1-defa
417 pinctrl-single,pins = <
418 J722S_MCU_IOPAD(0x040,
419 J722S_MCU_IOPAD(0x03C,
420 >;
421 };
422
423 mcu_mcan0_gpio_pins_default: mcu-mcan0
424 pinctrl-single,pins = <
425 J722S_MCU_IOPAD(0x0030
426 >;
427 };
428
429 wkup_uart0_pins_default: wkup-uart0-de
430 pinctrl-single,pins = <
431 J722S_MCU_IOPAD(0x02c,
432 J722S_MCU_IOPAD(0x030,
433 J722S_MCU_IOPAD(0x024,
434 J722S_MCU_IOPAD(0x028,
435 >;
436 bootph-all;
437 };
438
439 wkup_i2c0_pins_default: wkup-i2c0-defa
440 pinctrl-single,pins = <
441 J722S_MCU_IOPAD(0x04c,
442 J722S_MCU_IOPAD(0x050,
443 >;
444 bootph-all;
445 };
446 };
447
448 &wkup_uart0 {
449 /* WKUP UART0 is used by Device Manage
450 pinctrl-names = "default";
451 pinctrl-0 = <&wkup_uart0_pins_default>
452 status = "reserved";
453 bootph-all;
454 };
455
456 &wkup_i2c0 {
457 pinctrl-names = "default";
458 pinctrl-0 = <&wkup_i2c0_pins_default>;
459 clock-frequency = <400000>;
460 status = "okay";
461 bootph-all;
462 };
463
464 &k3_clks {
465 /* Configure AUDIO_EXT_REFCLK1 pin as
466 pinctrl-names = "default";
467 pinctrl-0 = <&audio_ext_refclk1_pins_d
468 };
469
470 &main_i2c0 {
471 pinctrl-names = "default";
472 pinctrl-0 = <&main_i2c0_pins_default>;
473 clock-frequency = <400000>;
474 status = "okay";
475 bootph-all;
476
477 exp1: gpio@23 {
478 compatible = "ti,tca6424";
479 reg = <0x23>;
480 gpio-controller;
481 #gpio-cells = <2>;
482 gpio-line-names = "TRC_MUX_SEL
483 "MCASP1_FET_
484 "CSI_VIO_SEL
485 "CSI01_MUX_S
486 "LMK1_OE1",
487 "LMK2_OE0",
488 "GPIO_RGMII1
489 "GPIO_eMMC_R
490 "USER_LED2",
491 "PCIe0_1L_RC
492 "ENET1_EXP_S
493 "PD_I2ENET1_
494
495 p05-hog {
496 /* P05 - USB2.0_MUX_SE
497 gpio-hog;
498 gpios = <5 GPIO_ACTIVE
499 output-high;
500 };
501
502 p01_hog: p01-hog {
503 /* P01 - TRC_MUX_SEL *
504 gpio-hog;
505 gpios = <0 GPIO_ACTIVE
506 output-low;
507 line-name = "TRC_MUX_S
508 };
509
510 p02_hog: p02-hog {
511 /* P02 - MCASP1_FET_SE
512 gpio-hog;
513 gpios = <2 GPIO_ACTIVE
514 output-high;
515 line-name = "MCASP1_FE
516 };
517
518 p13_hog: p13-hog {
519 /* P13 - GPIO_AUD_RSTn
520 gpio-hog;
521 gpios = <13 GPIO_ACTIV
522 output-high;
523 line-name = "GPIO_AUD_
524 };
525 };
526
527 tlv320aic3106: audio-codec@1b {
528 #sound-dai-cells = <0>;
529 compatible = "ti,tlv320aic3106
530 reg = <0x1b>;
531 ai3x-micbias-vg = <1>; /* 2.0
532 AVDD-supply = <&vsys_io_3v3>;
533 IOVDD-supply = <&vsys_io_3v3>;
534 DRVDD-supply = <&vsys_io_3v3>;
535 DVDD-supply = <&vsys_io_1v8>;
536 };
537 };
538
539 &ospi0 {
540 pinctrl-names = "default";
541 pinctrl-0 = <&ospi0_pins_default>;
542 status = "okay";
543
544 flash@0 {
545 compatible = "jedec,spi-nor";
546 reg = <0x0>;
547 spi-tx-bus-width = <8>;
548 spi-rx-bus-width = <8>;
549 spi-max-frequency = <25000000>
550 cdns,tshsl-ns = <60>;
551 cdns,tsd2d-ns = <60>;
552 cdns,tchsh-ns = <60>;
553 cdns,tslch-ns = <60>;
554 cdns,read-delay = <4>;
555 bootph-all;
556
557 partitions {
558 compatible = "fixed-pa
559 #address-cells = <1>;
560 #size-cells = <1>;
561
562 partition@0 {
563 label = "ospi.
564 reg = <0x00 0x
565 };
566
567 partition@80000 {
568 label = "ospi.
569 reg = <0x80000
570 };
571
572 partition@280000 {
573 label = "ospi.
574 reg = <0x28000
575 };
576
577 partition@680000 {
578 label = "ospi.
579 reg = <0x68000
580 };
581
582 partition@6c0000 {
583 label = "ospi.
584 reg = <0x6c000
585 };
586
587 partition@800000 {
588 label = "ospi.
589 reg = <0x80000
590 };
591
592 partition@3fc0000 {
593 label = "ospi.
594 reg = <0x3fc00
595 };
596 };
597 };
598
599 };
600
601 &sdhci0 {
602 disable-wp;
603 bootph-all;
604 ti,driver-strength-ohm = <50>;
605 status = "okay";
606 };
607
608 &sdhci1 {
609 /* SD/MMC */
610 vmmc-supply = <&vdd_mmc1>;
611 vqmmc-supply = <&vdd_sd_dv>;
612 pinctrl-names = "default";
613 pinctrl-0 = <&main_mmc1_pins_default>;
614 ti,driver-strength-ohm = <50>;
615 disable-wp;
616 status = "okay";
617 bootph-all;
618 };
619
620 &mailbox0_cluster0 {
621 status = "okay";
622
623 mbox_wkup_r5_0: mbox-wkup-r5-0 {
624 ti,mbox-rx = <0 0 0>;
625 ti,mbox-tx = <1 0 0>;
626 };
627 };
628
629 &mailbox0_cluster1 {
630 status = "okay";
631
632 mbox_mcu_r5_0: mbox-mcu-r5-0 {
633 ti,mbox-rx = <0 0 0>;
634 ti,mbox-tx = <1 0 0>;
635 };
636 };
637
638 &mailbox0_cluster2 {
639 status = "okay";
640
641 mbox_c7x_0: mbox-c7x-0 {
642 ti,mbox-rx = <0 0 0>;
643 ti,mbox-tx = <1 0 0>;
644 };
645 };
646
647 &mailbox0_cluster3 {
648 status = "okay";
649
650 mbox_main_r5_0: mbox-main-r5-0 {
651 ti,mbox-rx = <0 0 0>;
652 ti,mbox-tx = <1 0 0>;
653 };
654
655 mbox_c7x_1: mbox-c7x-1 {
656 ti,mbox-rx = <2 0 0>;
657 ti,mbox-tx = <3 0 0>;
658 };
659 };
660
661 /* Timers are used by Remoteproc firmware */
662 &main_timer0 {
663 status = "reserved";
664 };
665
666 &main_timer1 {
667 status = "reserved";
668 };
669
670 &main_timer2 {
671 status = "reserved";
672 };
673
674 &wkup_r5fss0 {
675 status = "okay";
676 };
677
678 &wkup_r5fss0_core0 {
679 mboxes = <&mailbox0_cluster0 &mbox_wku
680 memory-region = <&wkup_r5fss0_core0_dm
681 <&wkup_r5fss0_core0_me
682 };
683
684 &mcu_r5fss0 {
685 status = "okay";
686 };
687
688 &mcu_r5fss0_core0 {
689 mboxes = <&mailbox0_cluster1 &mbox_mcu
690 memory-region = <&mcu_r5fss0_core0_dma
691 <&mcu_r5fss0_core0_mem
692 };
693
694 &main_r5fss0 {
695 status = "okay";
696 };
697
698 &main_r5fss0_core0 {
699 mboxes = <&mailbox0_cluster3 &mbox_mai
700 memory-region = <&main_r5fss0_core0_dm
701 <&main_r5fss0_core0_me
702 };
703
704 &c7x_0 {
705 mboxes = <&mailbox0_cluster2 &mbox_c7x
706 memory-region = <&c7x_0_dma_memory_reg
707 <&c7x_0_memory_region>
708 status = "okay";
709 };
710
711 &c7x_1 {
712 mboxes = <&mailbox0_cluster3 &mbox_c7x
713 memory-region = <&c7x_1_dma_memory_reg
714 <&c7x_1_memory_region>
715 status = "okay";
716 };
717
718 &serdes_ln_ctrl {
719 idle-states = <J722S_SERDES0_LANE0_USB
720 <J722S_SERDES1_LANE0_PCI
721 };
722
723 &serdes0 {
724 status = "okay";
725 serdes0_usb_link: phy@0 {
726 reg = <0>;
727 cdns,num-lanes = <1>;
728 #phy-cells = <0>;
729 cdns,phy-type = <PHY_TYPE_USB3
730 resets = <&serdes_wiz0 1>;
731 };
732 };
733
734 &serdes1 {
735 status = "okay";
736 serdes1_pcie_link: phy@0 {
737 reg = <0>;
738 cdns,num-lanes = <1>;
739 #phy-cells = <0>;
740 cdns,phy-type = <PHY_TYPE_PCIE
741 resets = <&serdes_wiz1 1>;
742 };
743 };
744
745 &pcie0_rc {
746 reset-gpios = <&exp1 18 GPIO_ACTIVE_HI
747 phys = <&serdes1_pcie_link>;
748 phy-names = "pcie-phy";
749 status = "okay";
750 };
751
752 &usbss0 {
753 ti,vbus-divider;
754 status = "okay";
755 };
756
757 &usb0 {
758 dr_mode = "otg";
759 usb-role-switch;
760 };
761
762 &usbss1 {
763 pinctrl-names = "default";
764 pinctrl-0 = <&main_usb1_pins_default>;
765 ti,vbus-divider;
766 status = "okay";
767 };
768
769 &usb1 {
770 dr_mode = "host";
771 maximum-speed = "super-speed";
772 phys = <&serdes0_usb_link>;
773 phy-names = "cdns3,usb3-phy";
774 };
775
776 &mcasp1 {
777 status = "okay";
778 #sound-dai-cells = <0>;
779 pinctrl-names = "default";
780 pinctrl-0 = <&main_mcasp1_pins_default
781 op-mode = <0>; /* MCASP_IIS_MODE */
782 tdm-slots = <2>;
783 serial-dir = < /* 0: INACTIVE, 1: TX,
784 1 0 2 0
785 0 0 0 0
786 0 0 0 0
787 0 0 0 0
788 >;
789 };
790
791 &mcu_mcan0 {
792 pinctrl-names = "default";
793 pinctrl-0 = <&mcu_mcan0_pins_default>;
794 phys = <&transceiver0>;
795 status = "okay";
796 };
797
798 &mcu_mcan1 {
799 pinctrl-names = "default";
800 pinctrl-0 = <&mcu_mcan1_pins_default>;
801 phys = <&transceiver1>;
802 status = "okay";
803 };
804
805 &main_mcan0 {
806 pinctrl-names = "default";
807 pinctrl-0 = <&main_mcan0_pins_default>
808 phys = <&transceiver2>;
809 status = "okay";
810 };
811
812 &mcu_gpio0 {
813 status = "okay";
814 };
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