1 // SPDX-License-Identifier: GPL-2.0-only OR MI
2 /*
3 * Device Tree Source for J722S SoC Family
4 *
5 * Copyright (C) 2024 Texas Instruments Incorp
6 */
7
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/irq
10 #include <dt-bindings/interrupt-controller/arm
11 #include <dt-bindings/soc/ti,sci_pm_domain.h>
12
13 #include "k3-pinctrl.h"
14
15 / {
16 model = "Texas Instruments K3 J722S So
17 compatible = "ti,j722s";
18 interrupt-parent = <&gic500>;
19 #address-cells = <2>;
20 #size-cells = <2>;
21
22 cpus {
23 #address-cells = <1>;
24 #size-cells = <0>;
25
26 cpu-map {
27 cluster0: cluster0 {
28 core0 {
29 cpu =
30 };
31
32 core1 {
33 cpu =
34 };
35
36 core2 {
37 cpu =
38 };
39
40 core3 {
41 cpu =
42 };
43 };
44 };
45
46 cpu0: cpu@0 {
47 compatible = "arm,cort
48 reg = <0x000>;
49 device_type = "cpu";
50 enable-method = "psci"
51 i-cache-size = <0x8000
52 i-cache-line-size = <6
53 i-cache-sets = <256>;
54 d-cache-size = <0x8000
55 d-cache-line-size = <6
56 d-cache-sets = <128>;
57 next-level-cache = <&l
58 clocks = <&k3_clks 135
59 };
60
61 cpu1: cpu@1 {
62 compatible = "arm,cort
63 reg = <0x001>;
64 device_type = "cpu";
65 enable-method = "psci"
66 i-cache-size = <0x8000
67 i-cache-line-size = <6
68 i-cache-sets = <256>;
69 d-cache-size = <0x8000
70 d-cache-line-size = <6
71 d-cache-sets = <128>;
72 next-level-cache = <&l
73 clocks = <&k3_clks 136
74 };
75
76 cpu2: cpu@2 {
77 compatible = "arm,cort
78 reg = <0x002>;
79 device_type = "cpu";
80 enable-method = "psci"
81 i-cache-size = <0x8000
82 i-cache-line-size = <6
83 i-cache-sets = <256>;
84 d-cache-size = <0x8000
85 d-cache-line-size = <6
86 d-cache-sets = <128>;
87 next-level-cache = <&l
88 clocks = <&k3_clks 137
89 };
90
91 cpu3: cpu@3 {
92 compatible = "arm,cort
93 reg = <0x003>;
94 device_type = "cpu";
95 enable-method = "psci"
96 i-cache-size = <0x8000
97 i-cache-line-size = <6
98 i-cache-sets = <256>;
99 d-cache-size = <0x8000
100 d-cache-line-size = <6
101 d-cache-sets = <128>;
102 next-level-cache = <&l
103 clocks = <&k3_clks 138
104 };
105 };
106
107 l2_0: l2-cache0 {
108 compatible = "cache";
109 cache-unified;
110 cache-level = <2>;
111 cache-size = <0x80000>;
112 cache-line-size = <64>;
113 cache-sets = <512>;
114 };
115
116 firmware {
117 optee {
118 compatible = "linaro,o
119 method = "smc";
120 };
121
122 psci: psci {
123 compatible = "arm,psci
124 method = "smc";
125 };
126 };
127
128 a53_timer0: timer-cl0-cpu0 {
129 compatible = "arm,armv8-timer"
130 interrupts = <GIC_PPI 13 IRQ_T
131 <GIC_PPI 14 IRQ_T
132 <GIC_PPI 11 IRQ_T
133 <GIC_PPI 10 IRQ_T
134 };
135
136 pmu: pmu {
137 compatible = "arm,cortex-a53-p
138 interrupts = <GIC_PPI 7 IRQ_TY
139 };
140
141 cbass_main: bus@f0000 {
142 compatible = "simple-bus";
143 #address-cells = <2>;
144 #size-cells = <2>;
145
146 ranges = <0x00 0x000f0000 0x00
147 <0x00 0x00420000 0x00
148 <0x00 0x00600000 0x00
149 <0x00 0x00703000 0x00
150 <0x00 0x0070c000 0x00
151 <0x00 0x00a40000 0x00
152 <0x00 0x01000000 0x00
153 <0x00 0x08000000 0x00
154 <0x00 0x0d000000 0x00
155 <0x00 0x0e000000 0x00
156 <0x00 0x0fd80000 0x00
157 <0x00 0x0fd20000 0x00
158 <0x00 0x0fd20200 0x00
159 <0x00 0x20000000 0x00
160 <0x00 0x30040000 0x00
161 <0x00 0x301C0000 0x00
162 <0x00 0x30101000 0x00
163 <0x00 0x30200000 0x00
164 <0x00 0x30210000 0x00
165 <0x00 0x30220000 0x00
166 <0x00 0x30270000 0x00
167 <0x00 0x30500000 0x00
168 <0x00 0x31000000 0x00
169 <0x00 0x31200000 0x00
170 <0x00 0x40900000 0x00
171 <0x00 0x43600000 0x00
172 <0x00 0x44043000 0x00
173 <0x00 0x44860000 0x00
174 <0x00 0x48000000 0x00
175 <0x00 0x60000000 0x00
176 <0x00 0x68000000 0x00
177 <0x00 0x70000000 0x00
178 <0x00 0x78400000 0x00
179 <0x00 0x78500000 0x00
180 <0x00 0x7e000000 0x00
181 <0x00 0x7e200000 0x00
182 <0x01 0x00000000 0x01
183 <0x05 0x00000000 0x05
184 <0x06 0x00000000 0x06
185
186 /* MCU Domain Range *
187 <0x00 0x04000000 0x00
188 <0x00 0x79000000 0x00
189 <0x00 0x79020000 0x00
190 <0x00 0x79100000 0x00
191 <0x00 0x79140000 0x00
192
193 /* Wakeup Domain Rang
194 <0x00 0x00b00000 0x00
195 <0x00 0x2b000000 0x00
196 <0x00 0x43000000 0x00
197 <0x00 0x78000000 0x00
198 <0x00 0x78100000 0x00
199
200 cbass_mcu: bus@4000000 {
201 compatible = "simple-b
202 #address-cells = <2>;
203 #size-cells = <2>;
204 ranges = <0x00 0x04000
205 <0x00 0x79000
206 <0x00 0x79020
207 <0x00 0x79100
208 <0x00 0x79140
209 bootph-all;
210 };
211
212 cbass_wakeup: bus@b00000 {
213 compatible = "simple-b
214 #address-cells = <2>;
215 #size-cells = <2>;
216 ranges = <0x00 0x00b00
217 <0x00 0x2b000
218 <0x00 0x43000
219 <0x00 0x78000
220 <0x00 0x78100
221 bootph-all;
222 };
223 };
224
225 #include "k3-am62p-j722s-common-therma
226 };
227
228 /* Include peripherals shared with AM62P */
229 #include "k3-am62p-j722s-common-main.dtsi"
230 #include "k3-am62p-j722s-common-mcu.dtsi"
231 #include "k3-am62p-j722s-common-wakeup.dtsi"
232
233 /* Include J722S specific peripherals */
234 #include "k3-j722s-main.dtsi"
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