1 // SPDX-License-Identifier: GPL-2.0-only OR MI
2 /*
3 * Device Tree Source for J784S4 SoC Family
4 *
5 * TRM (SPRUJ43 JULY 2022): https://www.ti.com
6 *
7 * Copyright (C) 2022-2024 Texas Instruments I
8 *
9 */
10
11 #include <dt-bindings/interrupt-controller/irq
12 #include <dt-bindings/interrupt-controller/arm
13 #include <dt-bindings/soc/ti,sci_pm_domain.h>
14
15 #include "k3-pinctrl.h"
16
17 / {
18 model = "Texas Instruments K3 J784S4 S
19 compatible = "ti,j784s4";
20 interrupt-parent = <&gic500>;
21 #address-cells = <2>;
22 #size-cells = <2>;
23
24 cpus {
25 #address-cells = <1>;
26 #size-cells = <0>;
27 cpu-map {
28 cluster0: cluster0 {
29 core0 {
30 cpu =
31 };
32
33 core1 {
34 cpu =
35 };
36
37 core2 {
38 cpu =
39 };
40
41 core3 {
42 cpu =
43 };
44 };
45
46 cluster1: cluster1 {
47 core0 {
48 cpu =
49 };
50
51 core1 {
52 cpu =
53 };
54
55 core2 {
56 cpu =
57 };
58
59 core3 {
60 cpu =
61 };
62 };
63 };
64
65 cpu0: cpu@0 {
66 compatible = "arm,cort
67 reg = <0x000>;
68 device_type = "cpu";
69 enable-method = "psci"
70 i-cache-size = <0xc000
71 i-cache-line-size = <6
72 i-cache-sets = <256>;
73 d-cache-size = <0x8000
74 d-cache-line-size = <6
75 d-cache-sets = <256>;
76 next-level-cache = <&L
77 };
78
79 cpu1: cpu@1 {
80 compatible = "arm,cort
81 reg = <0x001>;
82 device_type = "cpu";
83 enable-method = "psci"
84 i-cache-size = <0xc000
85 i-cache-line-size = <6
86 i-cache-sets = <256>;
87 d-cache-size = <0x8000
88 d-cache-line-size = <6
89 d-cache-sets = <256>;
90 next-level-cache = <&L
91 };
92
93 cpu2: cpu@2 {
94 compatible = "arm,cort
95 reg = <0x002>;
96 device_type = "cpu";
97 enable-method = "psci"
98 i-cache-size = <0xc000
99 i-cache-line-size = <6
100 i-cache-sets = <256>;
101 d-cache-size = <0x8000
102 d-cache-line-size = <6
103 d-cache-sets = <256>;
104 next-level-cache = <&L
105 };
106
107 cpu3: cpu@3 {
108 compatible = "arm,cort
109 reg = <0x003>;
110 device_type = "cpu";
111 enable-method = "psci"
112 i-cache-size = <0xc000
113 i-cache-line-size = <6
114 i-cache-sets = <256>;
115 d-cache-size = <0x8000
116 d-cache-line-size = <6
117 d-cache-sets = <256>;
118 next-level-cache = <&L
119 };
120
121 cpu4: cpu@100 {
122 compatible = "arm,cort
123 reg = <0x100>;
124 device_type = "cpu";
125 enable-method = "psci"
126 i-cache-size = <0xc000
127 i-cache-line-size = <6
128 i-cache-sets = <256>;
129 d-cache-size = <0x8000
130 d-cache-line-size = <6
131 d-cache-sets = <256>;
132 next-level-cache = <&L
133 };
134
135 cpu5: cpu@101 {
136 compatible = "arm,cort
137 reg = <0x101>;
138 device_type = "cpu";
139 enable-method = "psci"
140 i-cache-size = <0xc000
141 i-cache-line-size = <6
142 i-cache-sets = <256>;
143 d-cache-size = <0x8000
144 d-cache-line-size = <6
145 d-cache-sets = <256>;
146 next-level-cache = <&L
147 };
148
149 cpu6: cpu@102 {
150 compatible = "arm,cort
151 reg = <0x102>;
152 device_type = "cpu";
153 enable-method = "psci"
154 i-cache-size = <0xc000
155 i-cache-line-size = <6
156 i-cache-sets = <256>;
157 d-cache-size = <0x8000
158 d-cache-line-size = <6
159 d-cache-sets = <256>;
160 next-level-cache = <&L
161 };
162
163 cpu7: cpu@103 {
164 compatible = "arm,cort
165 reg = <0x103>;
166 device_type = "cpu";
167 enable-method = "psci"
168 i-cache-size = <0xc000
169 i-cache-line-size = <6
170 i-cache-sets = <256>;
171 d-cache-size = <0x8000
172 d-cache-line-size = <6
173 d-cache-sets = <256>;
174 next-level-cache = <&L
175 };
176 };
177
178 L2_0: l2-cache0 {
179 compatible = "cache";
180 cache-level = <2>;
181 cache-unified;
182 cache-size = <0x200000>;
183 cache-line-size = <64>;
184 cache-sets = <1024>;
185 next-level-cache = <&msmc_l3>;
186 };
187
188 L2_1: l2-cache1 {
189 compatible = "cache";
190 cache-level = <2>;
191 cache-unified;
192 cache-size = <0x200000>;
193 cache-line-size = <64>;
194 cache-sets = <1024>;
195 next-level-cache = <&msmc_l3>;
196 };
197
198 msmc_l3: l3-cache0 {
199 compatible = "cache";
200 cache-level = <3>;
201 cache-unified;
202 };
203
204 firmware {
205 optee {
206 compatible = "linaro,o
207 method = "smc";
208 };
209
210 psci: psci {
211 compatible = "arm,psci
212 method = "smc";
213 };
214 };
215
216 a72_timer0: timer-cl0-cpu0 {
217 compatible = "arm,armv8-timer"
218 interrupts = <GIC_PPI 13 IRQ_T
219 <GIC_PPI 14 IRQ_T
220 <GIC_PPI 11 IRQ_T
221 <GIC_PPI 10 IRQ_T
222 };
223
224 pmu: pmu {
225 compatible = "arm,cortex-a72-p
226 /* Recommendation from GIC500
227 interrupts = <GIC_PPI 7 IRQ_TY
228 };
229
230 cbass_main: bus@100000 {
231 bootph-all;
232 compatible = "simple-bus";
233 #address-cells = <2>;
234 #size-cells = <2>;
235 ranges = <0x00 0x00100000 0x00
236 <0x00 0x00600000 0x00
237 <0x00 0x00700000 0x00
238 <0x00 0x01000000 0x00
239 <0x00 0x04210000 0x00
240 <0x00 0x04220000 0x00
241 <0x00 0x0d000000 0x00
242 <0x00 0x0d800000 0x00
243 <0x00 0x0e000000 0x00
244 <0x00 0x0e800000 0x00
245 <0x00 0x10000000 0x00
246 <0x00 0x18000000 0x00
247 <0x00 0x64800000 0x00
248 <0x00 0x65800000 0x00
249 <0x00 0x66800000 0x00
250 <0x00 0x67800000 0x00
251 <0x00 0x6f000000 0x00
252 <0x00 0x70000000 0x00
253 <0x00 0x30000000 0x00
254 <0x40 0x00000000 0x40
255 <0x41 0x00000000 0x41
256 <0x42 0x00000000 0x42
257 <0x43 0x00000000 0x43
258 <0x44 0x00000000 0x44
259 <0x44 0x10000000 0x44
260 <0x4e 0x20000000 0x4e
261
262 /* MCUSS_WKUP Range *
263 <0x00 0x28380000 0x00
264 <0x00 0x40200000 0x00
265 <0x00 0x40f00000 0x00
266 <0x00 0x41000000 0x00
267 <0x00 0x41400000 0x00
268 <0x00 0x41c00000 0x00
269 <0x00 0x42040000 0x00
270 <0x00 0x45100000 0x00
271 <0x00 0x46000000 0x00
272 <0x00 0x47000000 0x00
273 <0x00 0x50000000 0x00
274 <0x04 0x00000000 0x04
275
276 cbass_mcu_wakeup: bus@28380000
277 bootph-all;
278 compatible = "simple-b
279 #address-cells = <2>;
280 #size-cells = <2>;
281 ranges = <0x00 0x28380
282 <0x00 0x40200
283 <0x00 0x40f00
284 <0x00 0x41000
285 <0x00 0x41400
286 <0x00 0x41c00
287 <0x00 0x42040
288 <0x00 0x45100
289 <0x00 0x46000
290 <0x00 0x47000
291 <0x00 0x50000
292 <0x04 0x00000
293 };
294 };
295
296 thermal_zones: thermal-zones {
297 #include "k3-j784s4-thermal.dt
298 };
299 };
300
301 /* Now include peripherals from each bus segme
302 #include "k3-j784s4-main.dtsi"
303 #include "k3-j784s4-mcu-wakeup.dtsi"
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