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Linux/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi

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Diff markup

Differences between /arch/arm64/boot/dts/toshiba/tmpv7708.dtsi (Version linux-6.12-rc7) and /arch/i386/boot/dts/toshiba/tmpv7708.dtsi (Version linux-5.3.18)


  1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)     
  2 /*                                                
  3  * Device Tree Source for the TMPV7708            
  4  *                                                
  5  * (C) Copyright 2018 - 2020, Toshiba Corporat    
  6  * (C) Copyright 2020, Nobuhiro Iwamatsu <nobuh    
  7  *                                                
  8  */                                               
  9                                                   
 10 #include <dt-bindings/clock/toshiba,tmpv770x.h    
 11 #include <dt-bindings/interrupt-controller/irq    
 12 #include <dt-bindings/interrupt-controller/arm    
 13                                                   
 14 /memreserve/ 0x81000000 0x00300000;     /* cpu    
 15                                                   
 16 / {                                               
 17         compatible = "toshiba,tmpv7708";          
 18         #address-cells = <2>;                     
 19         #size-cells = <2>;                        
 20                                                   
 21         cpus {                                    
 22                 #address-cells = <1>;             
 23                 #size-cells = <0>;                
 24                                                   
 25                 cpu-map {                         
 26                         cluster0 {                
 27                                 core0 {           
 28                                         cpu =     
 29                                 };                
 30                                 core1 {           
 31                                         cpu =     
 32                                 };                
 33                                 core2 {           
 34                                         cpu =     
 35                                 };                
 36                                 core3 {           
 37                                         cpu =     
 38                                 };                
 39                         };                        
 40                                                   
 41                         cluster1 {                
 42                                 core0 {           
 43                                         cpu =     
 44                                 };                
 45                                 core1 {           
 46                                         cpu =     
 47                                 };                
 48                                 core2 {           
 49                                         cpu =     
 50                                 };                
 51                                 core3 {           
 52                                         cpu =     
 53                                 };                
 54                         };                        
 55                 };                                
 56                                                   
 57                 cpu0: cpu@0 {                     
 58                         compatible = "arm,cort    
 59                         device_type = "cpu";      
 60                         enable-method = "spin-    
 61                         cpu-release-addr = <0x    
 62                         reg = <0x00>;             
 63                 };                                
 64                                                   
 65                 cpu1: cpu@1 {                     
 66                         compatible = "arm,cort    
 67                         device_type = "cpu";      
 68                         enable-method = "spin-    
 69                         cpu-release-addr = <0x    
 70                         reg = <0x01>;             
 71                 };                                
 72                                                   
 73                 cpu2: cpu@2 {                     
 74                         compatible = "arm,cort    
 75                         device_type = "cpu";      
 76                         enable-method = "spin-    
 77                         cpu-release-addr = <0x    
 78                         reg = <0x02>;             
 79                 };                                
 80                                                   
 81                 cpu3: cpu@3 {                     
 82                         compatible = "arm,cort    
 83                         device_type = "cpu";      
 84                         enable-method = "spin-    
 85                         cpu-release-addr = <0x    
 86                         reg = <0x03>;             
 87                 };                                
 88                                                   
 89                 cpu4: cpu@100 {                   
 90                         compatible = "arm,cort    
 91                         device_type = "cpu";      
 92                         enable-method = "spin-    
 93                         cpu-release-addr = <0x    
 94                         reg = <0x100>;            
 95                 };                                
 96                                                   
 97                 cpu5: cpu@101 {                   
 98                         compatible = "arm,cort    
 99                         device_type = "cpu";      
100                         enable-method = "spin-    
101                         cpu-release-addr = <0x    
102                         reg = <0x101>;            
103                 };                                
104                                                   
105                 cpu6: cpu@102 {                   
106                         compatible = "arm,cort    
107                         device_type = "cpu";      
108                         enable-method = "spin-    
109                         cpu-release-addr = <0x    
110                         reg = <0x102>;            
111                 };                                
112                                                   
113                 cpu7: cpu@103 {                   
114                         compatible = "arm,cort    
115                         device_type = "cpu";      
116                         enable-method = "spin-    
117                         cpu-release-addr = <0x    
118                         reg = <0x103>;            
119                 };                                
120         };                                        
121                                                   
122         timer {                                   
123                 compatible = "arm,armv8-timer"    
124                 interrupt-parent = <&gic>;        
125                 interrupts =                      
126                         <GIC_PPI 13 (GIC_CPU_M    
127                         <GIC_PPI 14 (GIC_CPU_M    
128                         <GIC_PPI 11 (GIC_CPU_M    
129                         <GIC_PPI 10 (GIC_CPU_M    
130         };                                        
131                                                   
132         extclk100mhz: extclk100mhz {              
133                 compatible = "fixed-clock";       
134                 #clock-cells = <0>;               
135                 clock-frequency = <100000000>;    
136                 clock-output-names = "extclk10    
137         };                                        
138                                                   
139         osc2_clk: osc2-clk {                      
140                 compatible = "fixed-clock";       
141                 clock-frequency = <20000000>;     
142                 #clock-cells = <0>;               
143         };                                        
144                                                   
145         soc {                                     
146                 #address-cells = <2>;             
147                 #size-cells = <2>;                
148                 compatible = "simple-bus";        
149                 interrupt-parent = <&gic>;        
150                 ranges;                           
151                                                   
152                 gic: interrupt-controller@2400    
153                         compatible = "arm,gic-    
154                         interrupt-controller;     
155                         #interrupt-cells = <3>    
156                         interrupts = <GIC_PPI     
157                         reg = <0 0x24001000 0     
158                               <0 0x24002000 0     
159                               <0 0x24004000 0     
160                               <0 0x24006000 0     
161                 };                                
162                                                   
163                 pmux: pmux@24190000 {             
164                         compatible = "toshiba,    
165                         reg = <0 0x24190000 0     
166                 };                                
167                                                   
168                 gpio: gpio@28020000 {             
169                         compatible = "toshiba,    
170                         reg = <0 0x28020000 0     
171                         #gpio-cells = <0x2>;      
172                         gpio-ranges = <&pmux 0    
173                         gpio-controller;          
174                         interrupt-controller;     
175                         #interrupt-cells = <2>    
176                         interrupt-parent = <&g    
177                 };                                
178                                                   
179                 pipllct: clock-controller@2422    
180                         compatible = "toshiba,    
181                         reg = <0 0x24220000 0     
182                         #clock-cells = <1>;       
183                         clocks = <&osc2_clk>;     
184                 };                                
185                                                   
186                 pismu: syscon@24200000 {          
187                         compatible = "toshiba,    
188                         reg = <0 0x24200000 0     
189                         #clock-cells = <1>;       
190                         #reset-cells = <1>;       
191                 };                                
192                                                   
193                 uart0: serial@28200000 {          
194                         compatible = "arm,pl01    
195                         reg = <0 0x28200000 0     
196                         interrupts = <GIC_SPI     
197                         pinctrl-names = "defau    
198                         pinctrl-0 = <&uart0_pi    
199                         clocks = <&pismu TMPV7    
200                         clock-names = "uartclk    
201                         status = "disabled";      
202                 };                                
203                                                   
204                 uart1: serial@28201000 {          
205                         compatible = "arm,pl01    
206                         reg = <0 0x28201000 0     
207                         interrupts = <GIC_SPI     
208                         pinctrl-names = "defau    
209                         pinctrl-0 = <&uart1_pi    
210                         clocks = <&pismu TMPV7    
211                         clock-names = "uartclk    
212                         status = "disabled";      
213                 };                                
214                                                   
215                 uart2: serial@28202000 {          
216                         compatible = "arm,pl01    
217                         reg = <0 0x28202000 0     
218                         interrupts = <GIC_SPI     
219                         pinctrl-names = "defau    
220                         pinctrl-0 = <&uart2_pi    
221                         clocks = <&pismu TMPV7    
222                         clock-names = "uartclk    
223                         status = "disabled";      
224                 };                                
225                                                   
226                 uart3: serial@28203000 {          
227                         compatible = "arm,pl01    
228                         reg = <0 0x28203000 0     
229                         interrupts = <GIC_SPI     
230                         pinctrl-names = "defau    
231                         pinctrl-0 = <&uart3_pi    
232                         clocks = <&pismu TMPV7    
233                         clock-names = "uartclk    
234                         status = "disabled";      
235                 };                                
236                                                   
237                 i2c0: i2c@28030000 {              
238                         compatible = "snps,des    
239                         reg = <0 0x28030000 0     
240                         interrupts = <GIC_SPI     
241                         pinctrl-names = "defau    
242                         pinctrl-0 = <&i2c0_pin    
243                         clock-frequency = <400    
244                         #address-cells = <1>;     
245                         #size-cells = <0>;        
246                         clocks = <&pismu TMPV7    
247                         status = "disabled";      
248                 };                                
249                                                   
250                 i2c1: i2c@28031000 {              
251                         compatible = "snps,des    
252                         reg = <0 0x28031000 0     
253                         interrupts = <GIC_SPI     
254                         pinctrl-names = "defau    
255                         pinctrl-0 = <&i2c1_pin    
256                         clock-frequency = <400    
257                         #address-cells = <1>;     
258                         #size-cells = <0>;        
259                         clocks = <&pismu TMPV7    
260                         status = "disabled";      
261                 };                                
262                                                   
263                 i2c2: i2c@28032000 {              
264                         compatible = "snps,des    
265                         reg = <0 0x28032000 0     
266                         interrupts = <GIC_SPI     
267                         pinctrl-names = "defau    
268                         pinctrl-0 = <&i2c2_pin    
269                         clock-frequency = <400    
270                         #address-cells = <1>;     
271                         #size-cells = <0>;        
272                         clocks = <&pismu TMPV7    
273                         status = "disabled";      
274                 };                                
275                                                   
276                 i2c3: i2c@28033000 {              
277                         compatible = "snps,des    
278                         reg = <0 0x28033000 0     
279                         interrupts = <GIC_SPI     
280                         pinctrl-names = "defau    
281                         pinctrl-0 = <&i2c3_pin    
282                         clock-frequency = <400    
283                         #address-cells = <1>;     
284                         #size-cells = <0>;        
285                         clocks = <&pismu TMPV7    
286                         status = "disabled";      
287                 };                                
288                                                   
289                 i2c4: i2c@28034000 {              
290                         compatible = "snps,des    
291                         reg = <0 0x28034000 0     
292                         interrupts = <GIC_SPI     
293                         pinctrl-names = "defau    
294                         pinctrl-0 = <&i2c4_pin    
295                         clock-frequency = <400    
296                         #address-cells = <1>;     
297                         #size-cells = <0>;        
298                         clocks = <&pismu TMPV7    
299                         status = "disabled";      
300                 };                                
301                                                   
302                 i2c5: i2c@28035000 {              
303                         compatible = "snps,des    
304                         reg = <0 0x28035000 0     
305                         interrupts = <GIC_SPI     
306                         pinctrl-names = "defau    
307                         pinctrl-0 = <&i2c5_pin    
308                         clock-frequency = <400    
309                         #address-cells = <1>;     
310                         #size-cells = <0>;        
311                         clocks = <&pismu TMPV7    
312                         status = "disabled";      
313                 };                                
314                                                   
315                 i2c6: i2c@28036000 {              
316                         compatible = "snps,des    
317                         reg = <0 0x28036000 0     
318                         interrupts = <GIC_SPI     
319                         pinctrl-names = "defau    
320                         pinctrl-0 = <&i2c6_pin    
321                         clock-frequency = <400    
322                         #address-cells = <1>;     
323                         #size-cells = <0>;        
324                         clocks = <&pismu TMPV7    
325                         status = "disabled";      
326                 };                                
327                                                   
328                 i2c7: i2c@28037000 {              
329                         compatible = "snps,des    
330                         reg = <0 0x28037000 0     
331                         interrupts = <GIC_SPI     
332                         pinctrl-names = "defau    
333                         pinctrl-0 = <&i2c7_pin    
334                         clock-frequency = <400    
335                         #address-cells = <1>;     
336                         #size-cells = <0>;        
337                         clocks = <&pismu TMPV7    
338                         status = "disabled";      
339                 };                                
340                                                   
341                 i2c8: i2c@28038000 {              
342                         compatible = "snps,des    
343                         reg = <0 0x28038000 0     
344                         interrupts = <GIC_SPI     
345                         pinctrl-names = "defau    
346                         pinctrl-0 = <&i2c8_pin    
347                         clock-frequency = <400    
348                         #address-cells = <1>;     
349                         #size-cells = <0>;        
350                         clocks = <&pismu TMPV7    
351                         status = "disabled";      
352                 };                                
353                                                   
354                 spi0: spi@28140000 {              
355                         compatible = "arm,pl02    
356                         reg = <0 0x28140000 0     
357                         interrupts = <GIC_SPI     
358                         pinctrl-names = "defau    
359                         pinctrl-0 = <&spi0_pin    
360                         num-cs = <1>;             
361                         #address-cells = <1>;     
362                         #size-cells = <0>;        
363                         clocks = <&pismu TMPV7    
364                         clock-names = "sspclk"    
365                         status = "disabled";      
366                 };                                
367                                                   
368                 spi1: spi@28141000 {              
369                         compatible = "arm,pl02    
370                         reg = <0 0x28141000 0     
371                         interrupts = <GIC_SPI     
372                         pinctrl-names = "defau    
373                         pinctrl-0 = <&spi1_pin    
374                         num-cs = <1>;             
375                         #address-cells = <1>;     
376                         #size-cells = <0>;        
377                         clocks = <&pismu TMPV7    
378                         clock-names = "sspclk"    
379                         status = "disabled";      
380                 };                                
381                                                   
382                 spi2: spi@28142000 {              
383                         compatible = "arm,pl02    
384                         reg = <0 0x28142000 0     
385                         interrupts = <GIC_SPI     
386                         pinctrl-names = "defau    
387                         pinctrl-0 = <&spi2_pin    
388                         num-cs = <1>;             
389                         #address-cells = <1>;     
390                         #size-cells = <0>;        
391                         clocks = <&pismu TMPV7    
392                         clock-names = "sspclk"    
393                         status = "disabled";      
394                 };                                
395                                                   
396                 spi3: spi@28143000 {              
397                         compatible = "arm,pl02    
398                         reg = <0 0x28143000 0     
399                         interrupts = <GIC_SPI     
400                         pinctrl-names = "defau    
401                         pinctrl-0 = <&spi3_pin    
402                         num-cs = <1>;             
403                         #address-cells = <1>;     
404                         #size-cells = <0>;        
405                         clocks = <&pismu TMPV7    
406                         clock-names = "sspclk"    
407                         status = "disabled";      
408                 };                                
409                                                   
410                 spi4: spi@28144000 {              
411                         compatible = "arm,pl02    
412                         reg = <0 0x28144000 0     
413                         interrupts = <GIC_SPI     
414                         pinctrl-names = "defau    
415                         pinctrl-0 = <&spi4_pin    
416                         num-cs = <1>;             
417                         #address-cells = <1>;     
418                         #size-cells = <0>;        
419                         clocks = <&pismu TMPV7    
420                         clock-names = "sspclk"    
421                         status = "disabled";      
422                 };                                
423                                                   
424                 spi5: spi@28145000 {              
425                         compatible = "arm,pl02    
426                         reg = <0 0x28145000 0     
427                         interrupts = <GIC_SPI     
428                         pinctrl-names = "defau    
429                         pinctrl-0 = <&spi5_pin    
430                         num-cs = <1>;             
431                         #address-cells = <1>;     
432                         #size-cells = <0>;        
433                         clocks = <&pismu TMPV7    
434                         clock-names = "sspclk"    
435                         status = "disabled";      
436                 };                                
437                                                   
438                 spi6: spi@28146000 {              
439                         compatible = "arm,pl02    
440                         reg = <0 0x28146000 0     
441                         interrupts = <GIC_SPI     
442                         pinctrl-names = "defau    
443                         pinctrl-0 = <&spi6_pin    
444                         num-cs = <1>;             
445                         #address-cells = <1>;     
446                         #size-cells = <0>;        
447                         clocks = <&pismu TMPV7    
448                         clock-names = "sspclk"    
449                         status = "disabled";      
450                 };                                
451                                                   
452                 piether: ethernet@28000000 {      
453                         compatible = "toshiba,    
454                         reg = <0 0x28000000 0     
455                         interrupts = <GIC_SPI     
456                         interrupt-names = "mac    
457                         snps,txpbl = <4>;         
458                         snps,rxpbl = <4>;         
459                         snps,tso;                 
460                         clocks = <&pismu TMPV7    
461                         clock-names = "stmmace    
462                         status = "disabled";      
463                 };                                
464                                                   
465                 wdt: wdt@28330000 {               
466                         compatible = "toshiba,    
467                         reg = <0 0x28330000 0     
468                         clocks = <&pismu TMPV7    
469                         status = "disabled";      
470                 };                                
471                                                   
472                 pwm: pwm@241c0000 {               
473                         compatible = "toshiba,    
474                         reg = <0 0x241c0000 0     
475                         pinctrl-names = "defau    
476                         pinctrl-0 = <&pwm_mux>    
477                         #pwm-cells = <2>;         
478                         status = "disabled";      
479                 };                                
480                                                   
481                 pcie: pcie@28400000 {             
482                         compatible = "toshiba,    
483                         reg = <0x0 0x28400000     
484                               <0x0 0x70000000     
485                               <0x0 0x28050000     
486                               <0x0 0x24200000     
487                               <0x0 0x24162000     
488                         reg-names = "dbi", "co    
489                         device_type = "pci";      
490                         bus-range = <0x00 0xff    
491                         num-lanes = <2>;          
492                         num-viewport = <8>;       
493                                                   
494                         #address-cells = <3>;     
495                         #size-cells = <2>;        
496                         #interrupt-cells = <1>    
497                         ranges = <0x81000000 0    
498                                   0x82000000 0    
499                         interrupts = <GIC_SPI     
500                                      <GIC_SPI     
501                         interrupt-names = "msi    
502                         interrupt-map-mask = <    
503                         interrupt-map =           
504                                 <0 0 0 1 &gic     
505                                  0 0 0 2 &gic     
506                                  0 0 0 3 &gic     
507                                  0 0 0 4 &gic     
508                         max-link-speed = <2>;     
509                         clocks = <&extclk100mh    
510                         clock-names = "ref", "    
511                         status = "disabled";      
512                 };                                
513         };                                        
514 };                                                
515                                                   
516 #include "tmpv7708_pins.dtsi"                     
                                                      

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