1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * sha2-ce-core.S - core SHA-224/SHA-256 trans
4 *
5 * Copyright (C) 2014 Linaro Ltd <ard.biesheuve
6 */
7
8 #include <linux/linkage.h>
9 #include <asm/assembler.h>
10
11 .text
12 .arch armv8-a+crypto
13
14 dga .req q20
15 dgav .req v20
16 dgb .req q21
17 dgbv .req v21
18
19 t0 .req v22
20 t1 .req v23
21
22 dg0q .req q24
23 dg0v .req v24
24 dg1q .req q25
25 dg1v .req v25
26 dg2q .req q26
27 dg2v .req v26
28
29 .macro add_only, ev, rc, s0
30 mov dg2v.16b, dg0v.16b
31 .ifeq \ev
32 add t1.4s, v\s0\().4s, \rc
33 sha256h dg0q, dg1q, t0.4s
34 sha256h2 dg1q, dg2q, t0.4s
35 .else
36 .ifnb \s0
37 add t0.4s, v\s0\().4s, \rc
38 .endif
39 sha256h dg0q, dg1q, t1.4s
40 sha256h2 dg1q, dg2q, t1.4s
41 .endif
42 .endm
43
44 .macro add_update, ev, rc, s0
45 sha256su0 v\s0\().4s, v\s1\().4s
46 add_only \ev, \rc, \s1
47 sha256su1 v\s0\().4s, v\s2\().4s
48 .endm
49
50 /*
51 * The SHA-256 round constants
52 */
53 .section ".rodata", "a"
54 .align 4
55 .Lsha2_rcon:
56 .word 0x428a2f98, 0x71374491
57 .word 0x3956c25b, 0x59f111f1
58 .word 0xd807aa98, 0x12835b01
59 .word 0x72be5d74, 0x80deb1fe
60 .word 0xe49b69c1, 0xefbe4786
61 .word 0x2de92c6f, 0x4a7484aa
62 .word 0x983e5152, 0xa831c66d
63 .word 0xc6e00bf3, 0xd5a79147
64 .word 0x27b70a85, 0x2e1b2138
65 .word 0x650a7354, 0x766a0abb
66 .word 0xa2bfe8a1, 0xa81a664b
67 .word 0xd192e819, 0xd6990624
68 .word 0x19a4c116, 0x1e376c08
69 .word 0x391c0cb3, 0x4ed8aa4a
70 .word 0x748f82ee, 0x78a5636f
71 .word 0x90befffa, 0xa4506ceb
72
73 /*
74 * int __sha256_ce_transform(struct sh
75 * int block
76 */
77 .text
78 SYM_FUNC_START(__sha256_ce_transform)
79 /* load round constants */
80 adr_l x8, .Lsha2_rcon
81 ld1 { v0.4s- v3.4s}, [x8],
82 ld1 { v4.4s- v7.4s}, [x8],
83 ld1 { v8.4s-v11.4s}, [x8],
84 ld1 {v12.4s-v15.4s}, [x8]
85
86 /* load state */
87 ld1 {dgav.4s, dgbv.4s}, [x
88
89 /* load sha256_ce_state::finalize */
90 ldr_l w4, sha256_ce_offsetof
91 ldr w4, [x0, x4]
92
93 /* load input */
94 0: ld1 {v16.4s-v19.4s}, [x1],
95 sub w2, w2, #1
96
97 CPU_LE( rev32 v16.16b, v16.16b
98 CPU_LE( rev32 v17.16b, v17.16b
99 CPU_LE( rev32 v18.16b, v18.16b
100 CPU_LE( rev32 v19.16b, v19.16b
101
102 1: add t0.4s, v16.4s, v0.4s
103 mov dg0v.16b, dgav.16b
104 mov dg1v.16b, dgbv.16b
105
106 add_update 0, v1, 16, 17, 18, 19
107 add_update 1, v2, 17, 18, 19, 16
108 add_update 0, v3, 18, 19, 16, 17
109 add_update 1, v4, 19, 16, 17, 18
110
111 add_update 0, v5, 16, 17, 18, 19
112 add_update 1, v6, 17, 18, 19, 16
113 add_update 0, v7, 18, 19, 16, 17
114 add_update 1, v8, 19, 16, 17, 18
115
116 add_update 0, v9, 16, 17, 18, 19
117 add_update 1, v10, 17, 18, 19, 16
118 add_update 0, v11, 18, 19, 16, 17
119 add_update 1, v12, 19, 16, 17, 18
120
121 add_only 0, v13, 17
122 add_only 1, v14, 18
123 add_only 0, v15, 19
124 add_only 1
125
126 /* update state */
127 add dgav.4s, dgav.4s, dg0v
128 add dgbv.4s, dgbv.4s, dg1v
129
130 /* handled all input blocks? */
131 cbz w2, 2f
132 cond_yield 3f, x5, x6
133 b 0b
134
135 /*
136 * Final block: add padding and total
137 * Skip if the input size was not a ro
138 * the padding is handled by the C cod
139 */
140 2: cbz x4, 3f
141 ldr_l w4, sha256_ce_offsetof
142 ldr x4, [x0, x4]
143 movi v17.2d, #0
144 mov x8, #0x80000000
145 movi v18.2d, #0
146 ror x7, x4, #29
147 fmov d16, x8
148 mov x4, #0
149 mov v19.d[0], xzr
150 mov v19.d[1], x7
151 b 1b
152
153 /* store new state */
154 3: st1 {dgav.4s, dgbv.4s}, [x
155 mov w0, w2
156 ret
157 SYM_FUNC_END(__sha256_ce_transform)
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