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Linux/arch/arm64/include/asm/archrandom.h

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Diff markup

Differences between /arch/arm64/include/asm/archrandom.h (Architecture m68k) and /arch/mips/include/asm-mips/archrandom.h (Architecture mips)


  1 /* SPDX-License-Identifier: GPL-2.0 */              1 
  2 #ifndef _ASM_ARCHRANDOM_H                         
  3 #define _ASM_ARCHRANDOM_H                         
  4                                                   
  5 #include <linux/arm-smccc.h>                      
  6 #include <linux/bug.h>                            
  7 #include <linux/kernel.h>                         
  8 #include <linux/irqflags.h>                       
  9 #include <asm/cpufeature.h>                       
 10                                                   
 11 #define ARM_SMCCC_TRNG_MIN_VERSION      0x1000    
 12                                                   
 13 extern bool smccc_trng_available;                 
 14                                                   
 15 static inline bool __init smccc_probe_trng(voi    
 16 {                                                 
 17         struct arm_smccc_res res;                 
 18                                                   
 19         arm_smccc_1_1_invoke(ARM_SMCCC_TRNG_VE    
 20         if ((s32)res.a0 < 0)                      
 21                 return false;                     
 22                                                   
 23         return res.a0 >= ARM_SMCCC_TRNG_MIN_VE    
 24 }                                                 
 25                                                   
 26 static inline bool __arm64_rndr(unsigned long     
 27 {                                                 
 28         bool ok;                                  
 29                                                   
 30         /*                                        
 31          * Reads of RNDR set PSTATE.NZCV to 0b    
 32          * and set PSTATE.NZCV to 0b0100 other    
 33          */                                       
 34         asm volatile(                             
 35                 __mrs_s("%0", SYS_RNDR_EL0) "\    
 36         "       cset %w1, ne\n"                   
 37         : "=r" (*v), "=r" (ok)                    
 38         :                                         
 39         : "cc");                                  
 40                                                   
 41         return ok;                                
 42 }                                                 
 43                                                   
 44 static inline bool __arm64_rndrrs(unsigned lon    
 45 {                                                 
 46         bool ok;                                  
 47                                                   
 48         /*                                        
 49          * Reads of RNDRRS set PSTATE.NZCV to     
 50          * and set PSTATE.NZCV to 0b0100 other    
 51          */                                       
 52         asm volatile(                             
 53                 __mrs_s("%0", SYS_RNDRRS_EL0)     
 54         "       cset %w1, ne\n"                   
 55         : "=r" (*v), "=r" (ok)                    
 56         :                                         
 57         : "cc");                                  
 58                                                   
 59         return ok;                                
 60 }                                                 
 61                                                   
 62 static __always_inline bool __cpu_has_rng(void    
 63 {                                                 
 64         if (unlikely(!system_capabilities_fina    
 65                 return this_cpu_has_cap(ARM64_    
 66         return alternative_has_cap_unlikely(AR    
 67 }                                                 
 68                                                   
 69 static inline size_t __must_check arch_get_ran    
 70 {                                                 
 71         /*                                        
 72          * Only support the generic interface     
 73          * the system wide capability, avoidin    
 74          * cpufeature code and with potential     
 75          * with and without the feature.          
 76          */                                       
 77         if (max_longs && __cpu_has_rng() && __    
 78                 return 1;                         
 79         return 0;                                 
 80 }                                                 
 81                                                   
 82 static inline size_t __must_check arch_get_ran    
 83 {                                                 
 84         if (!max_longs)                           
 85                 return 0;                         
 86                                                   
 87         /*                                        
 88          * We prefer the SMCCC call, since its    
 89          * hardware backed entropy) is closer     
 90          * function here than what even the RN    
 91          * (the output of a pseudo RNG freshly    
 92          */                                       
 93         if (smccc_trng_available) {               
 94                 struct arm_smccc_res res;         
 95                                                   
 96                 max_longs = min_t(size_t, 3, m    
 97                 arm_smccc_1_1_invoke(ARM_SMCCC    
 98                 if ((int)res.a0 >= 0) {           
 99                         switch (max_longs) {      
100                         case 3:                   
101                                 *v++ = res.a1;    
102                                 fallthrough;      
103                         case 2:                   
104                                 *v++ = res.a2;    
105                                 fallthrough;      
106                         case 1:                   
107                                 *v++ = res.a3;    
108                                 break;            
109                         }                         
110                         return max_longs;         
111                 }                                 
112         }                                         
113                                                   
114         /*                                        
115          * RNDRRS is not backed by an entropy     
116          * reseeded after each invocation. Thi    
117          * enough to implement this API if no     
118          */                                       
119         if (__cpu_has_rng() && __arm64_rndrrs(    
120                 return 1;                         
121                                                   
122         return 0;                                 
123 }                                                 
124                                                   
125 static inline bool __init __early_cpu_has_rndr    
126 {                                                 
127         /* Open code as we run prior to the fi    
128         unsigned long ftr = read_sysreg_s(SYS_    
129         return (ftr >> ID_AA64ISAR0_EL1_RNDR_S    
130 }                                                 
131                                                   
132 #endif /* _ASM_ARCHRANDOM_H */                    
133                                                   

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