1 /* SPDX-License-Identifier: GPL-2.0-only */ 1
2 /*
3 * Copyright (C) 2016 ARM Ltd.
4 */
5 #ifndef __ASM_PGTABLE_PROT_H
6 #define __ASM_PGTABLE_PROT_H
7
8 #include <asm/memory.h>
9 #include <asm/pgtable-hwdef.h>
10
11 #include <linux/const.h>
12
13 /*
14 * Software defined PTE bits definition.
15 */
16 #define PTE_WRITE (PTE_DBM)
17 #define PTE_SWP_EXCLUSIVE (_AT(pteval_t,
18 #define PTE_DIRTY (_AT(pteval_t,
19 #define PTE_SPECIAL (_AT(pteval_t,
20 #define PTE_DEVMAP (_AT(pteval_t,
21
22 /*
23 * PTE_PRESENT_INVALID=1 & PTE_VALID=0 indicat
24 * interpreted according to the HW layout by S
25 * the address will result in a fault. pte_pre
26 */
27 #define PTE_PRESENT_INVALID (PTE_NG)
28
29 #ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP
30 #define PTE_UFFD_WP (_AT(pteval_t,
31 #define PTE_SWP_UFFD_WP (_AT(pteval_t,
32 #else
33 #define PTE_UFFD_WP (_AT(pteval_t,
34 #define PTE_SWP_UFFD_WP (_AT(pteval_t,
35 #endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */
36
37 #define _PROT_DEFAULT (PTE_TYPE_PAGE
38 #define _PROT_SECT_DEFAULT (PMD_TYPE_SECT
39
40 #define PROT_DEFAULT (PTE_TYPE_PAGE
41 #define PROT_SECT_DEFAULT (PMD_TYPE_SECT
42
43 #define PROT_DEVICE_nGnRnE (PROT_DEFAULT
44 #define PROT_DEVICE_nGnRE (PROT_DEFAULT
45 #define PROT_NORMAL_NC (PROT_DEFAULT
46 #define PROT_NORMAL (PROT_DEFAULT
47 #define PROT_NORMAL_TAGGED (PROT_DEFAULT
48
49 #define PROT_SECT_DEVICE_nGnRE (PROT_SECT_DEF
50 #define PROT_SECT_NORMAL (PROT_SECT_DEF
51 #define PROT_SECT_NORMAL_EXEC (PROT_SECT_DEF
52
53 #define _PAGE_DEFAULT (_PROT_DEFAULT
54
55 #define _PAGE_KERNEL (PROT_NORMAL)
56 #define _PAGE_KERNEL_RO ((PROT_NORMAL
57 #define _PAGE_KERNEL_ROX ((PROT_NORMAL
58 #define _PAGE_KERNEL_EXEC (PROT_NORMAL &
59 #define _PAGE_KERNEL_EXEC_CONT ((PROT_NORMAL
60
61 #define _PAGE_SHARED (_PAGE_DEFAULT
62 #define _PAGE_SHARED_EXEC (_PAGE_DEFAULT
63 #define _PAGE_READONLY (_PAGE_DEFAULT
64 #define _PAGE_READONLY_EXEC (_PAGE_DEFAULT
65 #define _PAGE_EXECONLY (_PAGE_DEFAULT
66
67 #ifndef __ASSEMBLY__
68
69 #include <asm/cpufeature.h>
70 #include <asm/pgtable-types.h>
71
72 extern bool arm64_use_ng_mappings;
73
74 #define PTE_MAYBE_NG (arm64_use_ng_
75 #define PMD_MAYBE_NG (arm64_use_ng_
76
77 #ifndef CONFIG_ARM64_LPA2
78 #define lpa2_is_enabled() false
79 #define PTE_MAYBE_SHARED PTE_SHARED
80 #define PMD_MAYBE_SHARED PMD_SECT_S
81 #else
82 static inline bool __pure lpa2_is_enabled(void
83 {
84 return read_tcr() & TCR_DS;
85 }
86
87 #define PTE_MAYBE_SHARED (lpa2_is_enabl
88 #define PMD_MAYBE_SHARED (lpa2_is_enabl
89 #endif
90
91 /*
92 * If we have userspace only BTI we don't want
93 * guarded even if the system does support BTI
94 */
95 #define PTE_MAYBE_GP (system_suppor
96
97 #define PAGE_KERNEL __pgprot(_PAGE
98 #define PAGE_KERNEL_RO __pgprot(_PAGE
99 #define PAGE_KERNEL_ROX __pgprot(_PAGE
100 #define PAGE_KERNEL_EXEC __pgprot(_PAGE
101 #define PAGE_KERNEL_EXEC_CONT __pgprot(_PAGE
102
103 #define PAGE_S2_MEMATTR(attr, has_fwb)
104 ({
105 u64 __val;
106 if (has_fwb)
107 __val = PTE_S2_MEMATTR
108 else
109 __val = PTE_S2_MEMATTR
110 __val;
111 })
112
113 #define PAGE_NONE __pgprot(((_PA
114 /* shared+writable pages are clean by default,
115 #define PAGE_SHARED __pgprot(_PAGE
116 #define PAGE_SHARED_EXEC __pgprot(_PAGE
117 #define PAGE_READONLY __pgprot(_PAGE
118 #define PAGE_READONLY_EXEC __pgprot(_PAGE
119 #define PAGE_EXECONLY __pgprot(_PAGE
120
121 #endif /* __ASSEMBLY__ */
122
123 #define pte_pi_index(pte) ( \
124 ((pte & BIT(PTE_PI_IDX_3)) >> (PTE_PI_
125 ((pte & BIT(PTE_PI_IDX_2)) >> (PTE_PI_
126 ((pte & BIT(PTE_PI_IDX_1)) >> (PTE_PI_
127 ((pte & BIT(PTE_PI_IDX_0)) >> (PTE_PI_
128
129 /*
130 * Page types used via Permission Indirection
131 * the USER, DBM, PXN and UXN bits to to gener
132 * to look up the actual permission in PIR_ELx
133 * combinations we use on non-PIE systems with
134 * convenience these are listed here as commen
135 * encodings.
136 */
137
138 /* 0: PAGE_DEFAULT
139 /* 1:
140 /* 2:
141 /* 3:
142 /* 4: PAGE_EXECONLY PTE_PXN
143 /* 5: PAGE_READONLY_EXEC PTE_PXN |
144 /* 6: PTE_PXN |
145 /* 7: PAGE_SHARED_EXEC PTE_PXN |
146 /* 8: PAGE_KERNEL_ROX PTE_UXN
147 /* 9: PTE_UXN |
148 /* a: PAGE_KERNEL_EXEC PTE_UXN |
149 /* b: PTE_UXN |
150 /* c: PAGE_KERNEL_RO PTE_UXN | PTE_PXN
151 /* d: PAGE_READONLY PTE_UXN | PTE_PXN |
152 /* e: PAGE_KERNEL PTE_UXN | PTE_PXN |
153 /* f: PAGE_SHARED PTE_UXN | PTE_PXN |
154
155 #define PIE_E0 ( \
156 PIRx_ELx_PERM(pte_pi_index(_PAGE_EXECO
157 PIRx_ELx_PERM(pte_pi_index(_PAGE_READO
158 PIRx_ELx_PERM(pte_pi_index(_PAGE_SHARE
159 PIRx_ELx_PERM(pte_pi_index(_PAGE_READO
160 PIRx_ELx_PERM(pte_pi_index(_PAGE_SHARE
161
162 #define PIE_E1 ( \
163 PIRx_ELx_PERM(pte_pi_index(_PAGE_EXECO
164 PIRx_ELx_PERM(pte_pi_index(_PAGE_READO
165 PIRx_ELx_PERM(pte_pi_index(_PAGE_SHARE
166 PIRx_ELx_PERM(pte_pi_index(_PAGE_READO
167 PIRx_ELx_PERM(pte_pi_index(_PAGE_SHARE
168 PIRx_ELx_PERM(pte_pi_index(_PAGE_KERNE
169 PIRx_ELx_PERM(pte_pi_index(_PAGE_KERNE
170 PIRx_ELx_PERM(pte_pi_index(_PAGE_KERNE
171 PIRx_ELx_PERM(pte_pi_index(_PAGE_KERNE
172
173 #endif /* __ASM_PGTABLE_PROT_H */
174
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