1 /* SPDX-License-Identifier: GPL-2.0-only */ <<
2 /* 1 /*
3 * Low-level exception handling code !! 2 * This file is subject to the terms and conditions of the GNU General Public
>> 3 * License. See the file "COPYING" in the main directory of this archive
>> 4 * for more details.
4 * 5 *
5 * Copyright (C) 2012 ARM Ltd. !! 6 * Copyright (C) 1994 - 2000, 2001 by Ralf Baechle
6 * Authors: Catalin Marinas <catalin.marina !! 7 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
7 * Will Deacon <will.deacon@arm.co !! 8 * Copyright (C) 2001 MIPS Technologies, Inc.
8 */ 9 */
9 !! 10 #include <linux/config.h>
10 #include <linux/arm-smccc.h> <<
11 #include <linux/init.h> 11 #include <linux/init.h>
12 #include <linux/linkage.h> !! 12 #include <linux/sys.h>
13 13
14 #include <asm/alternative.h> !! 14 #include <asm/addrspace.h>
15 #include <asm/assembler.h> !! 15 #include <asm/asm.h>
16 #include <asm/asm-offsets.h> !! 16 #include <asm/cacheops.h>
17 #include <asm/asm_pointer_auth.h> !! 17 #include <asm/current.h>
18 #include <asm/bug.h> <<
19 #include <asm/cpufeature.h> <<
20 #include <asm/errno.h> 18 #include <asm/errno.h>
21 #include <asm/esr.h> !! 19 #include <asm/mipsregs.h>
22 #include <asm/irq.h> !! 20 #include <asm/page.h>
23 #include <asm/memory.h> !! 21 #include <asm/pgtable-bits.h>
24 #include <asm/mmu.h> !! 22 #include <asm/stackframe.h>
25 #include <asm/processor.h> 23 #include <asm/processor.h>
26 #include <asm/ptrace.h> !! 24 #include <asm/regdef.h>
27 #include <asm/scs.h> !! 25 #include <asm/fpregdef.h>
28 #include <asm/thread_info.h> <<
29 #include <asm/asm-uaccess.h> <<
30 #include <asm/unistd.h> 26 #include <asm/unistd.h>
>> 27 #include <asm/isadep.h>
31 28
32 .macro clear_gp_regs <<
33 .irp n,0,1,2,3,4,5,6,7,8,9,10,11,12 <<
34 mov x\n, xzr <<
35 .endr <<
36 .endm <<
37 <<
38 .macro kernel_ventry, el:req, ht:req, <<
39 .align 7 <<
40 .Lventry_start\@: <<
41 .if \el == 0 <<
42 /* <<
43 * This must be the first instruction <<
44 * skipped by the trampoline vectors, <<
45 */ <<
46 b .Lskip_tramp_vectors_cleanup\@ <<
47 .if \regsize == 64 <<
48 mrs x30, tpidrro_el0 <<
49 msr tpidrro_el0, xzr <<
50 .else <<
51 mov x30, xzr <<
52 .endif <<
53 .Lskip_tramp_vectors_cleanup\@: <<
54 .endif <<
55 <<
56 sub sp, sp, #PT_REGS_SIZE <<
57 #ifdef CONFIG_VMAP_STACK <<
58 /* <<
59 * Test whether the SP has overflowed, <<
60 * Task and IRQ stacks are aligned so <<
61 * should always be zero. <<
62 */ <<
63 add sp, sp, x0 <<
64 sub x0, sp, x0 <<
65 tbnz x0, #THREAD_SHIFT, 0f <<
66 sub x0, sp, x0 <<
67 sub sp, sp, x0 <<
68 b el\el\ht\()_\regsize\()_\label <<
69 <<
70 0: <<
71 /* <<
72 * Either we've just detected an overf <<
73 * while on the overflow stack. Either <<
74 * userspace, and can clobber EL0 regi <<
75 */ <<
76 <<
77 /* Stash the original SP (minus PT_REG <<
78 msr tpidr_el0, x0 <<
79 <<
80 /* Recover the original x0 value and s <<
81 sub x0, sp, x0 <<
82 msr tpidrro_el0, x0 <<
83 <<
84 /* Switch to the overflow stack */ <<
85 adr_this_cpu sp, overflow_stack + OVER <<
86 <<
87 /* <<
88 * Check whether we were already on th <<
89 * after panic() re-enables interrupts <<
90 */ <<
91 mrs x0, tpidr_el0 <<
92 sub x0, sp, x0 <<
93 tst x0, #~(OVERFLOW_STACK_SIZE - 1 <<
94 b.ne __bad_stack <<
95 <<
96 /* We were already on the overflow sta <<
97 sub sp, sp, x0 <<
98 mrs x0, tpidrro_el0 <<
99 #endif <<
100 b el\el\ht\()_\regsize\()_\label <<
101 .org .Lventry_start\@ + 128 // Did we over <<
102 .endm <<
103 <<
104 .macro tramp_alias, dst, sym <<
105 .set .Lalias\@, TRAMP_VALIAS + \sym <<
106 movz \dst, :abs_g2_s:.Lalias\@ <<
107 movk \dst, :abs_g1_nc:.Lalias\@ <<
108 movk \dst, :abs_g0_nc:.Lalias\@ <<
109 .endm <<
110 <<
111 /* <<
112 * This macro corrupts x0-x3. It is th <<
113 * them if required. <<
114 */ <<
115 .macro apply_ssbd, state, tmp1, tmp2 <<
116 alternative_cb ARM64_ALWAYS_SYSTEM, spectre_v <<
117 b .L__asm_ssbd_skip\@ <<
118 alternative_cb_end <<
119 ldr_this_cpu \tmp2, arm64_ssbd_call <<
120 cbz \tmp2, .L__asm_ssbd_skip\@ <<
121 ldr \tmp2, [tsk, #TSK_TI_FLAGS] <<
122 tbnz \tmp2, #TIF_SSBD, .L__asm_ssbd <<
123 mov w0, #ARM_SMCCC_ARCH_WORKAROUND <<
124 mov w1, #\state <<
125 alternative_cb ARM64_ALWAYS_SYSTEM, smccc_pat <<
126 nop <<
127 alternative_cb_end <<
128 .L__asm_ssbd_skip\@: <<
129 .endm <<
130 <<
131 /* Check for MTE asynchronous tag chec <<
132 .macro check_mte_async_tcf, tmp, ti_fl <<
133 #ifdef CONFIG_ARM64_MTE <<
134 .arch_extension lse <<
135 alternative_if_not ARM64_MTE <<
136 b 1f <<
137 alternative_else_nop_endif <<
138 /* <<
139 * Asynchronous tag check faults are o <<
140 * ASYM (3) modes. In each of these mo <<
141 * set, so skip the check if it is uns <<
142 */ <<
143 tbz \thread_sctlr, #(SCTLR_EL1_TCF <<
144 mrs_s \tmp, SYS_TFSRE0_EL1 <<
145 tbz \tmp, #SYS_TFSR_EL1_TF0_SHIFT, <<
146 /* Asynchronous TCF occurred for TTBR0 <<
147 mov \tmp, #_TIF_MTE_ASYNC_FAULT <<
148 add \ti_flags, tsk, #TSK_TI_FLAGS <<
149 stset \tmp, [\ti_flags] <<
150 1: <<
151 #endif <<
152 .endm <<
153 <<
154 /* Clear the MTE asynchronous tag chec <<
155 .macro clear_mte_async_tcf thread_sctl <<
156 #ifdef CONFIG_ARM64_MTE <<
157 alternative_if ARM64_MTE <<
158 /* See comment in check_mte_async_tcf <<
159 tbz \thread_sctlr, #(SCTLR_EL1_TCF <<
160 dsb ish <<
161 msr_s SYS_TFSRE0_EL1, xzr <<
162 1: <<
163 alternative_else_nop_endif <<
164 #endif <<
165 .endm <<
166 29
167 .macro mte_set_gcr, mte_ctrl, tmp !! 30 .text
168 #ifdef CONFIG_ARM64_MTE !! 31 .align 5
169 ubfx \tmp, \mte_ctrl, #MTE_CTRL_GCR !! 32 .set push
170 orr \tmp, \tmp, #SYS_GCR_EL1_RRND !! 33 .set reorder
171 msr_s SYS_GCR_EL1, \tmp !! 34 FEXPORT(ret_from_irq)
172 #endif !! 35 FEXPORT(ret_from_exception)
173 .endm !! 36 lw t0, PT_STATUS(sp) # returning to kernel mode?
174 !! 37 andi t0, t0, KU_USER
175 .macro mte_set_kernel_gcr, tmp, tmp2 !! 38 beqz t0, restore_all
176 #ifdef CONFIG_KASAN_HW_TAGS !! 39
177 alternative_cb ARM64_ALWAYS_SYSTEM, kasan_hw_ !! 40 FEXPORT(ret_from_sys_call) # here to prevent code duplication
178 b 1f !! 41 ret_from_schedule:
179 alternative_cb_end !! 42 mfc0 t0, CP0_STATUS # need_resched and signals atomic test
180 mov \tmp, KERNEL_GCR_EL1 !! 43 ori t0, t0, 1
181 msr_s SYS_GCR_EL1, \tmp !! 44 xori t0, t0, 1
182 1: !! 45 mtc0 t0, CP0_STATUS
183 #endif !! 46 SSNOP; SSNOP; SSNOP
184 .endm !! 47
185 !! 48 lw v0, TASK_NEED_RESCHED($28)
186 .macro mte_set_user_gcr, tsk, tmp, tmp !! 49 lw v1, TASK_SIGPENDING($28)
187 #ifdef CONFIG_KASAN_HW_TAGS !! 50 bnez v0, reschedule
188 alternative_cb ARM64_ALWAYS_SYSTEM, kasan_hw_ !! 51 bnez v1, signal_return
189 b 1f !! 52 restore_all: .set noat
190 alternative_cb_end !! 53 RESTORE_ALL_AND_RET
191 ldr \tmp, [\tsk, #THREAD_MTE_CTRL] !! 54 .set at
192 !! 55
193 mte_set_gcr \tmp, \tmp2 !! 56 /* Put this behind restore_all for the sake of the branch prediction. */
194 1: !! 57 signal_return:
195 #endif !! 58 .type signal_return, @function
196 .endm !! 59
197 !! 60 mfc0 t0, CP0_STATUS
198 .macro kernel_entry, el, regsize = 64 !! 61 ori t0, t0, 1
199 .if \el == 0 !! 62 mtc0 t0, CP0_STATUS
200 alternative_insn nop, SET_PSTATE_DIT(1 !! 63
201 .endif !! 64 move a0, zero
202 .if \regsize == 32 !! 65 move a1, sp
203 mov w0, w0 !! 66 jal do_signal
204 .endif !! 67 b restore_all
205 stp x0, x1, [sp, #16 * 0] !! 68
206 stp x2, x3, [sp, #16 * 1] !! 69 reschedule:
207 stp x4, x5, [sp, #16 * 2] !! 70 jal schedule
208 stp x6, x7, [sp, #16 * 3] !! 71 b ret_from_schedule
209 stp x8, x9, [sp, #16 * 4] !! 72
210 stp x10, x11, [sp, #16 * 5] !! 73 /*
211 stp x12, x13, [sp, #16 * 6] !! 74 * Common spurious interrupt handler.
212 stp x14, x15, [sp, #16 * 7] !! 75 */
213 stp x16, x17, [sp, #16 * 8] !! 76 .text
214 stp x18, x19, [sp, #16 * 9] !! 77 .align 5
215 stp x20, x21, [sp, #16 * 10] !! 78 LEAF(spurious_interrupt)
216 stp x22, x23, [sp, #16 * 11] !! 79 /*
217 stp x24, x25, [sp, #16 * 12] !! 80 * Someone tried to fool us by sending an interrupt but we
218 stp x26, x27, [sp, #16 * 13] !! 81 * couldn't find a cause for it.
219 stp x28, x29, [sp, #16 * 14] !! 82 */
220 !! 83 lui t1,%hi(irq_err_count)
221 .if \el == 0 !! 84 lw t0,%lo(irq_err_count)(t1)
222 clear_gp_regs !! 85 addiu t0,1
223 mrs x21, sp_el0 !! 86 sw t0,%lo(irq_err_count)(t1)
224 ldr_this_cpu tsk, __entry_task, x20 !! 87 j ret_from_irq
225 msr sp_el0, tsk !! 88 END(spurious_interrupt)
226 !! 89
227 /* !! 90 __INIT
228 * Ensure MDSCR_EL1.SS is clear, since !! 91
229 * when scheduling. !! 92 .set reorder
230 */ !! 93
231 ldr x19, [tsk, #TSK_TI_FLAGS] !! 94 NESTED(except_vec1_generic, 0, sp)
232 disable_step_tsk x19, x20 !! 95 PANIC("Exception vector 1 called")
233 !! 96 END(except_vec1_generic)
234 /* Check for asynchronous tag check fa !! 97
235 ldr x0, [tsk, THREAD_SCTLR_USER] !! 98 /*
236 check_mte_async_tcf x22, x23, x0 !! 99 * General exception vector. Used for all CPUs except R4000
237 !! 100 * and R4400 SC and MC versions.
238 #ifdef CONFIG_ARM64_PTR_AUTH !! 101 */
239 alternative_if ARM64_HAS_ADDRESS_AUTH !! 102 NESTED(except_vec3_generic, 0, sp)
240 /* !! 103 #if R5432_CP0_INTERRUPT_WAR
241 * Enable IA for in-kernel PAC if the !! 104 mfc0 k0, CP0_INDEX
242 * this could be implemented with an u !! 105 #endif
243 * a load, this was measured to be slo !! 106 mfc0 k1, CP0_CAUSE
244 * !! 107 la k0, exception_handlers
245 * Install the kernel IA key only if I !! 108 andi k1, k1, 0x7c
246 * was disabled on kernel exit then we !! 109 addu k0, k0, k1
247 * installed so there is no need to in !! 110 lw k0, (k0)
248 */ !! 111 jr k0
249 tbz x0, SCTLR_ELx_ENIA_SHIFT, 1f !! 112 END(except_vec3_generic)
250 __ptrauth_keys_install_kernel_nosync t !! 113 .set at
251 b 2f !! 114
252 1: !! 115 /* General exception vector R4000 version. */
253 mrs x0, sctlr_el1 !! 116 NESTED(except_vec3_r4000, 0, sp)
254 orr x0, x0, SCTLR_ELx_ENIA !! 117 .set push
255 msr sctlr_el1, x0 !! 118 .set mips3
256 2: !! 119 .set noat
257 alternative_else_nop_endif !! 120 mfc0 k1, CP0_CAUSE
258 #endif !! 121 li k0, 31<<2
259 !! 122 andi k1, k1, 0x7c
260 apply_ssbd 1, x22, x23 !! 123 .set noreorder
261 !! 124 beq k1, k0, handle_vced
262 mte_set_kernel_gcr x22, x23 !! 125 li k0, 14<<2
263 !! 126 beq k1, k0, handle_vcei
264 /* !! 127 la k0, exception_handlers
265 * Any non-self-synchronizing system r !! 128 .set reorder
266 * kernel entry should be placed befor !! 129 addu k0, k0, k1
267 */ !! 130 lw k0, (k0)
268 alternative_if ARM64_MTE !! 131 jr k0
269 isb !! 132
270 b 1f !! 133 /*
271 alternative_else_nop_endif !! 134 * Big shit, we now may have two dirty primary cache lines for
272 alternative_if ARM64_HAS_ADDRESS_AUTH !! 135 * the same physical address. We can savely invalidate the
273 isb !! 136 * line pointed to by c0_badvaddr because after return from
274 alternative_else_nop_endif !! 137 * this exception handler the load / store will be re-executed.
275 1: !! 138 */
276 !! 139 handle_vced:
277 scs_load_current !! 140 mfc0 k0, CP0_BADVADDR
278 .else !! 141 li k1, -4
279 add x21, sp, #PT_REGS_SIZE !! 142 and k0, k1
280 get_current_task tsk !! 143 mtc0 zero, CP0_TAGLO
281 .endif /* \el == 0 */ !! 144 cache Index_Store_Tag_D,(k0)
282 mrs x22, elr_el1 !! 145 cache Hit_Writeback_Inv_SD,(k0)
283 mrs x23, spsr_el1 !! 146 #ifdef CONFIG_PROC_FS
284 stp lr, x21, [sp, #S_LR] !! 147 lui k0, %hi(vced_count)
285 !! 148 lw k1, %lo(vced_count)(k0)
286 /* !! 149 addiu k1, 1
287 * For exceptions from EL0, create a f !! 150 sw k1, %lo(vced_count)(k0)
288 * For exceptions from EL1, create a s !! 151 #endif
289 * interrupted code shows up in the ba !! 152 eret
290 */ !! 153
291 .if \el == 0 !! 154 handle_vcei:
292 stp xzr, xzr, [sp, #S_STACKFRAME] !! 155 mfc0 k0, CP0_BADVADDR
293 .else !! 156 cache Hit_Writeback_Inv_SD, (k0) # also cleans pi
294 stp x29, x22, [sp, #S_STACKFRAME] !! 157 #ifdef CONFIG_PROC_FS
295 .endif !! 158 lui k0, %hi(vcei_count)
296 add x29, sp, #S_STACKFRAME !! 159 lw k1, %lo(vcei_count)(k0)
297 !! 160 addiu k1, 1
298 #ifdef CONFIG_ARM64_SW_TTBR0_PAN !! 161 sw k1, %lo(vcei_count)(k0)
299 alternative_if_not ARM64_HAS_PAN !! 162 #endif
300 bl __swpan_entry_el\el !! 163 eret
301 alternative_else_nop_endif !! 164 .set pop
302 #endif !! 165 END(except_vec3_r4000)
303 !! 166
304 stp x22, x23, [sp, #S_PC] !! 167 __FINIT
305 !! 168
306 /* Not in a syscall by default (el0_sv !! 169 /*
307 .if \el == 0 !! 170 * Build a default exception handler for the exceptions that don't need
308 mov w21, #NO_SYSCALL !! 171 * special handlers. If you didn't know yet - I *like* playing games with
309 str w21, [sp, #S_SYSCALLNO] !! 172 * the C preprocessor ...
310 .endif !! 173 */
311 !! 174 #define __BUILD_clear_none(exception)
312 #ifdef CONFIG_ARM64_PSEUDO_NMI !! 175 #define __BUILD_clear_sti(exception) \
313 alternative_if_not ARM64_HAS_GIC_PRIO_MASKING !! 176 STI
314 b .Lskip_pmr_save\@ !! 177 #define __BUILD_clear_cli(exception) \
315 alternative_else_nop_endif !! 178 CLI
316 !! 179 #define __BUILD_clear_fpe(exception) \
317 mrs_s x20, SYS_ICC_PMR_EL1 !! 180 cfc1 a1,fcr31; \
318 str x20, [sp, #S_PMR_SAVE] !! 181 li a2,~(0x3f<<12); \
319 mov x20, #GIC_PRIO_IRQON | GIC_PRI !! 182 and a2,a1; \
320 msr_s SYS_ICC_PMR_EL1, x20 !! 183 ctc1 a2,fcr31; \
321 !! 184 STI
322 .Lskip_pmr_save\@: !! 185 #define __BUILD_clear_ade(exception) \
323 #endif !! 186 .set reorder; \
324 !! 187 MFC0 t0,CP0_BADVADDR; \
325 /* !! 188 .set noreorder; \
326 * Registers that may be useful after !! 189 REG_S t0,PT_BVADDR(sp); \
327 * !! 190 KMODE
328 * x20 - ICC_PMR_EL1 !! 191 #define __BUILD_silent(exception)
329 * x21 - aborted SP !! 192
330 * x22 - aborted PC !! 193 #define fmt "Got %s at %08lx.\n"
331 * x23 - aborted PSTATE !! 194
332 */ !! 195 #define __BUILD_verbose(exception) \
333 .endm !! 196 la a1,8f; \
334 !! 197 TEXT (#exception); \
335 .macro kernel_exit, el !! 198 REG_L a2,PT_EPC(sp); \
336 .if \el != 0 !! 199 PRINT(fmt)
337 disable_daif !! 200 #define __BUILD_count(exception) \
338 .endif !! 201 .set reorder; \
339 !! 202 lw t0,exception_count_##exception; \
340 #ifdef CONFIG_ARM64_PSEUDO_NMI !! 203 .set noreorder; \
341 alternative_if_not ARM64_HAS_GIC_PRIO_MASKING !! 204 addiu t0, 1; \
342 b .Lskip_pmr_restore\@ !! 205 sw t0,exception_count_##exception; \
343 alternative_else_nop_endif !! 206 .data; \
344 !! 207 EXPORT(exception_count_##exception); \
345 ldr x20, [sp, #S_PMR_SAVE] !! 208 .word 0; \
346 msr_s SYS_ICC_PMR_EL1, x20 !! 209 .previous;
347 !! 210 #define BUILD_HANDLER(exception,handler,clear,verbose) \
348 /* Ensure priority change is seen by r !! 211 .align 5; \
349 alternative_if_not ARM64_HAS_GIC_PRIO_RELAXED_ !! 212 NESTED(handle_##exception, PT_SIZE, sp); \
350 dsb sy !! 213 .set noat; \
351 alternative_else_nop_endif !! 214 SAVE_ALL; \
352 !! 215 FEXPORT(handle_##exception##_int); \
353 .Lskip_pmr_restore\@: !! 216 __BUILD_clear_##clear(exception); \
354 #endif !! 217 .set at; \
355 !! 218 __BUILD_##verbose(exception); \
356 ldp x21, x22, [sp, #S_PC] !! 219 jal do_##handler; \
357 !! 220 move a0, sp; \
358 #ifdef CONFIG_ARM64_SW_TTBR0_PAN !! 221 j ret_from_exception; \
359 alternative_if_not ARM64_HAS_PAN !! 222 nop; \
360 bl __swpan_exit_el\el !! 223 END(handle_##exception)
361 alternative_else_nop_endif !! 224
362 #endif !! 225 BUILD_HANDLER(adel,ade,ade,silent) /* #4 */
363 !! 226 BUILD_HANDLER(ades,ade,ade,silent) /* #5 */
364 .if \el == 0 !! 227 BUILD_HANDLER(ibe,be,cli,silent) /* #6 */
365 ldr x23, [sp, #S_SP] !! 228 BUILD_HANDLER(dbe,be,cli,silent) /* #7 */
366 msr sp_el0, x23 !! 229 BUILD_HANDLER(bp,bp,sti,silent) /* #9 */
367 tst x22, #PSR_MODE32_BIT !! 230 BUILD_HANDLER(ri,ri,sti,silent) /* #10 */
368 b.eq 3f !! 231 BUILD_HANDLER(cpu,cpu,sti,silent) /* #11 */
369 !! 232 BUILD_HANDLER(ov,ov,sti,silent) /* #12 */
370 #ifdef CONFIG_ARM64_ERRATUM_845719 !! 233 BUILD_HANDLER(tr,tr,sti,silent) /* #13 */
371 alternative_if ARM64_WORKAROUND_845719 !! 234 BUILD_HANDLER(fpe,fpe,fpe,silent) /* #15 */
372 #ifdef CONFIG_PID_IN_CONTEXTIDR !! 235 BUILD_HANDLER(mdmx,mdmx,sti,silent) /* #22 */
373 mrs x29, contextidr_el1 !! 236 BUILD_HANDLER(watch,watch,sti,silent) /* #23 */
374 msr contextidr_el1, x29 !! 237 BUILD_HANDLER(mcheck,mcheck,cli,silent) /* #24 */
>> 238 BUILD_HANDLER(reserved,reserved,sti,silent) /* others */
>> 239
>> 240 .set pop
>> 241
>> 242 /*
>> 243 * Table of syscalls
>> 244 */
>> 245 .data
>> 246 .align PTRLOG
>> 247 EXPORT(sys_call_table)
>> 248 #define SYS(call, narg) PTR call
>> 249
>> 250 /* Reserved space for all SVR4 syscalls. */
>> 251 .space (1000)*PTRSIZE
>> 252
>> 253 #ifdef CONFIG_BINFMT_IRIX
>> 254 /* 32bit IRIX5 system calls. */
>> 255 #include "irix5sys.h"
375 #else 256 #else
376 msr contextidr_el1, xzr !! 257 .space (1000)*PTRSIZE /* No IRIX syscalls */
377 #endif <<
378 alternative_else_nop_endif <<
379 #endif <<
380 3: <<
381 scs_save tsk <<
382 <<
383 /* Ignore asynchronous tag check fault <<
384 ldr x0, [tsk, THREAD_SCTLR_USER] <<
385 clear_mte_async_tcf x0 <<
386 <<
387 #ifdef CONFIG_ARM64_PTR_AUTH <<
388 alternative_if ARM64_HAS_ADDRESS_AUTH <<
389 /* <<
390 * IA was enabled for in-kernel PAC. D <<
391 * alternatively install the user's IA <<
392 * SCTLR bits were updated on task swi <<
393 * <<
394 * No kernel C function calls after th <<
395 */ <<
396 tbz x0, SCTLR_ELx_ENIA_SHIFT, 1f <<
397 __ptrauth_keys_install_user tsk, x0, x <<
398 b 2f <<
399 1: <<
400 mrs x0, sctlr_el1 <<
401 bic x0, x0, SCTLR_ELx_ENIA <<
402 msr sctlr_el1, x0 <<
403 2: <<
404 alternative_else_nop_endif <<
405 #endif 258 #endif
406 259
407 mte_set_user_gcr tsk, x0, x1 !! 260 /* Reserved space for all the BSD43 and POSIX syscalls. */
408 !! 261 .space (2000)*PTRSIZE
409 apply_ssbd 0, x0, x1 <<
410 .endif <<
411 <<
412 msr elr_el1, x21 <<
413 msr spsr_el1, x22 <<
414 ldp x0, x1, [sp, #16 * 0] <<
415 ldp x2, x3, [sp, #16 * 1] <<
416 ldp x4, x5, [sp, #16 * 2] <<
417 ldp x6, x7, [sp, #16 * 3] <<
418 ldp x8, x9, [sp, #16 * 4] <<
419 ldp x10, x11, [sp, #16 * 5] <<
420 ldp x12, x13, [sp, #16 * 6] <<
421 ldp x14, x15, [sp, #16 * 7] <<
422 ldp x16, x17, [sp, #16 * 8] <<
423 ldp x18, x19, [sp, #16 * 9] <<
424 ldp x20, x21, [sp, #16 * 10] <<
425 ldp x22, x23, [sp, #16 * 11] <<
426 ldp x24, x25, [sp, #16 * 12] <<
427 ldp x26, x27, [sp, #16 * 13] <<
428 ldp x28, x29, [sp, #16 * 14] <<
429 <<
430 .if \el == 0 <<
431 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 <<
432 alternative_insn "b .L_skip_tramp_exit <<
433 <<
434 msr far_el1, x29 <<
435 <<
436 ldr_this_cpu x30, this_cpu_vector, <<
437 tramp_alias x29, tramp_exit <<
438 msr vbar_el1, x30 <<
439 ldr lr, [sp, #S_LR] <<
440 add sp, sp, #PT_REGS_SIZE <<
441 br x29 <<
442 <<
443 .L_skip_tramp_exit_\@: <<
444 #endif <<
445 .endif <<
446 <<
447 ldr lr, [sp, #S_LR] <<
448 add sp, sp, #PT_REGS_SIZE <<
449 <<
450 .if \el == 0 <<
451 /* This must be after the last explici <<
452 alternative_if ARM64_WORKAROUND_SPECULATIVE_UN <<
453 tlbi vale1, xzr <<
454 dsb nsh <<
455 alternative_else_nop_endif <<
456 .else <<
457 /* Ensure any device/NC reads complete <<
458 alternative_insn nop, "dmb sy", ARM64_ <<
459 .endif <<
460 <<
461 eret <<
462 sb <<
463 .endm <<
464 <<
465 #ifdef CONFIG_ARM64_SW_TTBR0_PAN <<
466 /* <<
467 * Set the TTBR0 PAN bit in SPSR. When <<
468 * EL0, there is no need to check the <<
469 * accesses are always enabled. <<
470 * Note that the meaning of this bit d <<
471 * feature as all TTBR0_EL1 accesses a <<
472 * user mappings. <<
473 */ <<
474 SYM_CODE_START_LOCAL(__swpan_entry_el1) <<
475 mrs x21, ttbr0_el1 <<
476 tst x21, #TTBR_ASID_MASK <<
477 orr x23, x23, #PSR_PAN_BIT <<
478 b.eq 1f <<
479 and x23, x23, #~PSR_PAN_BIT <<
480 SYM_INNER_LABEL(__swpan_entry_el0, SYM_L_LOCAL <<
481 __uaccess_ttbr0_disable x21 <<
482 1: ret <<
483 SYM_CODE_END(__swpan_entry_el1) <<
484 <<
485 /* <<
486 * Restore access to TTBR0_EL1. If ret <<
487 * PAN bit checking. <<
488 */ <<
489 SYM_CODE_START_LOCAL(__swpan_exit_el1) <<
490 tbnz x22, #22, 1f <<
491 __uaccess_ttbr0_enable x0, x1 <<
492 1: and x22, x22, #~PSR_PAN_BIT <<
493 ret <<
494 SYM_CODE_END(__swpan_exit_el1) <<
495 <<
496 SYM_CODE_START_LOCAL(__swpan_exit_el0) <<
497 __uaccess_ttbr0_enable x0, x1 <<
498 /* <<
499 * Enable errata workarounds only if r <<
500 * workaround currently required for T <<
501 * Cavium erratum 27456 (broadcast TLB <<
502 * corruption). <<
503 */ <<
504 b post_ttbr_update_workaround <<
505 SYM_CODE_END(__swpan_exit_el0) <<
506 #endif <<
507 <<
508 /* GPRs used by entry code */ <<
509 tsk .req x28 // current thr <<
510 <<
511 .text <<
512 <<
513 /* <<
514 * Exception vectors. <<
515 */ <<
516 .pushsection ".entry.text", "ax" <<
517 262
518 .align 11 !! 263 /* Linux flavoured syscalls. */
519 SYM_CODE_START(vectors) !! 264 #include "syscalls.h"
520 kernel_ventry 1, t, 64, sync <<
521 kernel_ventry 1, t, 64, irq <<
522 kernel_ventry 1, t, 64, fiq <<
523 kernel_ventry 1, t, 64, error <<
524 <<
525 kernel_ventry 1, h, 64, sync <<
526 kernel_ventry 1, h, 64, irq <<
527 kernel_ventry 1, h, 64, fiq <<
528 kernel_ventry 1, h, 64, error <<
529 <<
530 kernel_ventry 0, t, 64, sync <<
531 kernel_ventry 0, t, 64, irq <<
532 kernel_ventry 0, t, 64, fiq <<
533 kernel_ventry 0, t, 64, error <<
534 <<
535 kernel_ventry 0, t, 32, sync <<
536 kernel_ventry 0, t, 32, irq <<
537 kernel_ventry 0, t, 32, fiq <<
538 kernel_ventry 0, t, 32, error <<
539 SYM_CODE_END(vectors) <<
540 <<
541 #ifdef CONFIG_VMAP_STACK <<
542 SYM_CODE_START_LOCAL(__bad_stack) <<
543 /* <<
544 * We detected an overflow in kernel_v <<
545 * overflow stack. Stash the exception <<
546 * handler. <<
547 */ <<
548 <<
549 /* Restore the original x0 value */ <<
550 mrs x0, tpidrro_el0 <<
551 <<
552 /* <<
553 * Store the original GPRs to the new <<
554 * PT_REGS_SIZE) was stashed in tpidr_ <<
555 */ <<
556 sub sp, sp, #PT_REGS_SIZE <<
557 kernel_entry 1 <<
558 mrs x0, tpidr_el0 <<
559 add x0, x0, #PT_REGS_SIZE <<
560 str x0, [sp, #S_SP] <<
561 <<
562 /* Stash the regs for handle_bad_stack <<
563 mov x0, sp <<
564 <<
565 /* Time to die */ <<
566 bl handle_bad_stack <<
567 ASM_BUG() <<
568 SYM_CODE_END(__bad_stack) <<
569 #endif /* CONFIG_VMAP_STACK */ <<
570 <<
571 <<
572 .macro entry_handler el:req, ht:req, r <<
573 SYM_CODE_START_LOCAL(el\el\ht\()_\regsize\()_\ <<
574 kernel_entry \el, \regsize <<
575 mov x0, sp <<
576 bl el\el\ht\()_\regsize\()_\label <<
577 .if \el == 0 <<
578 b ret_to_user <<
579 .else <<
580 b ret_to_kernel <<
581 .endif <<
582 SYM_CODE_END(el\el\ht\()_\regsize\()_\label) <<
583 .endm <<
584 265
585 /* 266 /*
586 * Early exception handlers !! 267 * Number of arguments of each syscall
587 */ 268 */
588 entry_handler 1, t, 64, sync !! 269 EXPORT(sys_narg_table)
589 entry_handler 1, t, 64, irq !! 270 #undef SYS
590 entry_handler 1, t, 64, fiq !! 271 #define SYS(call, narg) .byte narg
591 entry_handler 1, t, 64, error <<
592 <<
593 entry_handler 1, h, 64, sync <<
594 entry_handler 1, h, 64, irq <<
595 entry_handler 1, h, 64, fiq <<
596 entry_handler 1, h, 64, error <<
597 <<
598 entry_handler 0, t, 64, sync <<
599 entry_handler 0, t, 64, irq <<
600 entry_handler 0, t, 64, fiq <<
601 entry_handler 0, t, 64, error <<
602 <<
603 entry_handler 0, t, 32, sync <<
604 entry_handler 0, t, 32, irq <<
605 entry_handler 0, t, 32, fiq <<
606 entry_handler 0, t, 32, error <<
607 <<
608 SYM_CODE_START_LOCAL(ret_to_kernel) <<
609 kernel_exit 1 <<
610 SYM_CODE_END(ret_to_kernel) <<
611 <<
612 SYM_CODE_START_LOCAL(ret_to_user) <<
613 ldr x19, [tsk, #TSK_TI_FLAGS] <<
614 enable_step_tsk x19, x2 <<
615 #ifdef CONFIG_GCC_PLUGIN_STACKLEAK <<
616 bl stackleak_erase_on_task_stack <<
617 #endif <<
618 kernel_exit 0 <<
619 SYM_CODE_END(ret_to_user) <<
620 272
621 .popsection !! 273 /* Reserved space for all SVR4 flavoured syscalls. */
>> 274 .space (1000)
622 275
623 // Move from tramp_pg_dir to swapper_p !! 276 #ifdef CONFIG_BINFMT_IRIX
624 .macro tramp_map_kernel, tmp !! 277 /* 32bit IRIX5 system calls. */
625 mrs \tmp, ttbr1_el1 !! 278 #include "irix5sys.h"
626 add \tmp, \tmp, #TRAMP_SWAPPER_OFF <<
627 bic \tmp, \tmp, #USER_ASID_FLAG <<
628 msr ttbr1_el1, \tmp <<
629 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003 <<
630 alternative_if ARM64_WORKAROUND_QCOM_FALKOR_E1 <<
631 /* ASID already in \tmp[63:48] */ <<
632 movk \tmp, #:abs_g2_nc:(TRAMP_VALIA <<
633 movk \tmp, #:abs_g1_nc:(TRAMP_VALIA <<
634 /* 2MB boundary containing the vectors <<
635 movk \tmp, #:abs_g0_nc:((TRAMP_VALI <<
636 isb <<
637 tlbi vae1, \tmp <<
638 dsb nsh <<
639 alternative_else_nop_endif <<
640 #endif /* CONFIG_QCOM_FALKOR_ERRATUM_1003 */ <<
641 .endm <<
642 <<
643 // Move from swapper_pg_dir to tramp_p <<
644 .macro tramp_unmap_kernel, tmp <<
645 mrs \tmp, ttbr1_el1 <<
646 sub \tmp, \tmp, #TRAMP_SWAPPER_OFF <<
647 orr \tmp, \tmp, #USER_ASID_FLAG <<
648 msr ttbr1_el1, \tmp <<
649 /* <<
650 * We avoid running the post_ttbr_upda <<
651 * it's only needed by Cavium ThunderX <<
652 * disabled. <<
653 */ <<
654 .endm <<
655 <<
656 .macro tramp_data_read_var <<
657 #ifdef CONFIG_RELOCATABLE <<
658 ldr \dst, .L__tramp_data_\ <<
659 .ifndef .L__tramp_data_\var <<
660 .pushsection ".entry.tramp.rodata", <<
661 .align 3 <<
662 .L__tramp_data_\var: <<
663 .quad \var <<
664 .popsection <<
665 .endif <<
666 #else 279 #else
667 /* !! 280 .space (1000) /* No IRIX syscalls */
668 * As !RELOCATABLE implies !RANDOMIZE_ <<
669 * compile time constant (and hence no <<
670 * <<
671 * As statically allocated kernel code <<
672 * 47 bits of the address space we can <<
673 * instruction to load the upper 16 bi <<
674 */ <<
675 movz \dst, :abs_g2_s:\var <<
676 movk \dst, :abs_g1_nc:\var <<
677 movk \dst, :abs_g0_nc:\var <<
678 #endif 281 #endif
679 .endm <<
680 <<
681 #define BHB_MITIGATION_NONE 0 <<
682 #define BHB_MITIGATION_LOOP 1 <<
683 #define BHB_MITIGATION_FW 2 <<
684 #define BHB_MITIGATION_INSN 3 <<
685 <<
686 .macro tramp_ventry, vector_start, reg <<
687 .align 7 <<
688 1: <<
689 .if \regsize == 64 <<
690 msr tpidrro_el0, x30 // Res <<
691 .endif <<
692 <<
693 .if \bhb == BHB_MITIGATION_LOOP <<
694 /* <<
695 * This sequence must appear before th <<
696 * ret out of tramp_ventry. It appears <<
697 */ <<
698 __mitigate_spectre_bhb_loop x30 <<
699 .endif // \bhb == BHB_MITIGATION_LOOP <<
700 <<
701 .if \bhb == BHB_MITIGATION_INSN <<
702 clearbhb <<
703 isb <<
704 .endif // \bhb == BHB_MITIGATION_INSN <<
705 <<
706 .if \kpti == 1 <<
707 /* <<
708 * Defend against branch aliasing atta <<
709 * entry onto the return stack and usi <<
710 * enter the full-fat kernel vectors. <<
711 */ <<
712 bl 2f <<
713 b . <<
714 2: <<
715 tramp_map_kernel x30 <<
716 alternative_insn isb, nop, ARM64_WORKAROUND_QC <<
717 tramp_data_read_var x30, vectors <<
718 alternative_if_not ARM64_WORKAROUND_CAVIUM_TX2 <<
719 prfm plil1strm, [x30, #(1b - \vecto <<
720 alternative_else_nop_endif <<
721 <<
722 msr vbar_el1, x30 <<
723 isb <<
724 .else <<
725 adr_l x30, vectors <<
726 .endif // \kpti == 1 <<
727 <<
728 .if \bhb == BHB_MITIGATION_FW <<
729 /* <<
730 * The firmware sequence must appear b <<
731 * i.e. the ret out of tramp_ventry. B <<
732 * mapped to save/restore the register <<
733 */ <<
734 __mitigate_spectre_bhb_fw <<
735 .endif // \bhb == BHB_MITIGATION_FW <<
736 <<
737 add x30, x30, #(1b - \vector_start <<
738 ret <<
739 .org 1b + 128 // Did we overflow the ventry <<
740 .endm <<
741 <<
742 .macro generate_tramp_vector, kpti, <<
743 .Lvector_start\@: <<
744 .space 0x400 <<
745 <<
746 .rept 4 <<
747 tramp_ventry .Lvector_start\@, 64, <<
748 .endr <<
749 .rept 4 <<
750 tramp_ventry .Lvector_start\@, 32, <<
751 .endr <<
752 .endm <<
753 <<
754 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 <<
755 /* <<
756 * Exception vectors trampoline. <<
757 * The order must match __bp_harden_el1_vector <<
758 * arm64_bp_harden_el1_vectors enum. <<
759 */ <<
760 .pushsection ".entry.tramp.text", "ax" <<
761 .align 11 <<
762 SYM_CODE_START_LOCAL_NOALIGN(tramp_vectors) <<
763 #ifdef CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY <<
764 generate_tramp_vector kpti=1, bhb=BH <<
765 generate_tramp_vector kpti=1, bhb=BH <<
766 generate_tramp_vector kpti=1, bhb=BH <<
767 #endif /* CONFIG_MITIGATE_SPECTRE_BRANCH_HISTO <<
768 generate_tramp_vector kpti=1, bhb=BH <<
769 SYM_CODE_END(tramp_vectors) <<
770 <<
771 SYM_CODE_START_LOCAL(tramp_exit) <<
772 tramp_unmap_kernel x29 <<
773 mrs x29, far_el1 <<
774 eret <<
775 sb <<
776 SYM_CODE_END(tramp_exit) <<
777 .popsection <<
778 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ <<
779 <<
780 /* <<
781 * Exception vectors for spectre mitigations o <<
782 * kpti is not in use. <<
783 */ <<
784 .macro generate_el1_vector, bhb <<
785 .Lvector_start\@: <<
786 kernel_ventry 1, t, 64, sync <<
787 kernel_ventry 1, t, 64, irq <<
788 kernel_ventry 1, t, 64, fiq <<
789 kernel_ventry 1, t, 64, error <<
790 <<
791 kernel_ventry 1, h, 64, sync <<
792 kernel_ventry 1, h, 64, irq <<
793 kernel_ventry 1, h, 64, fiq <<
794 kernel_ventry 1, h, 64, error <<
795 <<
796 .rept 4 <<
797 tramp_ventry .Lvector_start\@, 64, <<
798 .endr <<
799 .rept 4 <<
800 tramp_ventry .Lvector_start\@, 32, <<
801 .endr <<
802 .endm <<
803 <<
804 /* The order must match tramp_vecs and the arm <<
805 .pushsection ".entry.text", "ax" <<
806 .align 11 <<
807 SYM_CODE_START(__bp_harden_el1_vectors) <<
808 #ifdef CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY <<
809 generate_el1_vector bhb=BHB_MITIGA <<
810 generate_el1_vector bhb=BHB_MITIGA <<
811 generate_el1_vector bhb=BHB_MITIGA <<
812 #endif /* CONFIG_MITIGATE_SPECTRE_BRANCH_HISTO <<
813 SYM_CODE_END(__bp_harden_el1_vectors) <<
814 .popsection <<
815 <<
816 282
817 /* !! 283 /* Reserved space for all the BSD43 and POSIX syscalls. */
818 * Register switch for AArch64. The callee-sav !! 284 .space (2000)
819 * and restored. On entry: <<
820 * x0 = previous task_struct (must be preser <<
821 * x1 = next task_struct <<
822 * Previous and next are guaranteed not to be <<
823 * <<
824 */ <<
825 SYM_FUNC_START(cpu_switch_to) <<
826 mov x10, #THREAD_CPU_CONTEXT <<
827 add x8, x0, x10 <<
828 mov x9, sp <<
829 stp x19, x20, [x8], #16 <<
830 stp x21, x22, [x8], #16 <<
831 stp x23, x24, [x8], #16 <<
832 stp x25, x26, [x8], #16 <<
833 stp x27, x28, [x8], #16 <<
834 stp x29, x9, [x8], #16 <<
835 str lr, [x8] <<
836 add x8, x1, x10 <<
837 ldp x19, x20, [x8], #16 <<
838 ldp x21, x22, [x8], #16 <<
839 ldp x23, x24, [x8], #16 <<
840 ldp x25, x26, [x8], #16 <<
841 ldp x27, x28, [x8], #16 <<
842 ldp x29, x9, [x8], #16 <<
843 ldr lr, [x8] <<
844 mov sp, x9 <<
845 msr sp_el0, x1 <<
846 ptrauth_keys_install_kernel x1, x8, x9 <<
847 scs_save x0 <<
848 scs_load_current <<
849 ret <<
850 SYM_FUNC_END(cpu_switch_to) <<
851 NOKPROBE(cpu_switch_to) <<
852 <<
853 /* <<
854 * This is how we return from a fork. <<
855 */ <<
856 SYM_CODE_START(ret_from_fork) <<
857 bl schedule_tail <<
858 cbz x19, 1f <<
859 mov x0, x20 <<
860 blr x19 <<
861 1: get_current_task tsk <<
862 mov x0, sp <<
863 bl asm_exit_to_user_mode <<
864 b ret_to_user <<
865 SYM_CODE_END(ret_from_fork) <<
866 NOKPROBE(ret_from_fork) <<
867 <<
868 /* <<
869 * void call_on_irq_stack(struct pt_regs *regs <<
870 * void (*func)(struct <<
871 * <<
872 * Calls func(regs) using this CPU's irq stack <<
873 */ <<
874 SYM_FUNC_START(call_on_irq_stack) <<
875 #ifdef CONFIG_SHADOW_CALL_STACK <<
876 get_current_task x16 <<
877 scs_save x16 <<
878 ldr_this_cpu scs_sp, irq_shadow_call_s <<
879 #endif <<
880 <<
881 /* Create a frame record to save our L <<
882 stp x29, x30, [sp, #-16]! <<
883 mov x29, sp <<
884 <<
885 ldr_this_cpu x16, irq_stack_ptr, x17 <<
886 <<
887 /* Move to the new stack and call the <<
888 add sp, x16, #IRQ_STACK_SIZE <<
889 blr x1 <<
890 <<
891 /* <<
892 * Restore the SP from the FP, and res <<
893 * record. <<
894 */ <<
895 mov sp, x29 <<
896 ldp x29, x30, [sp], #16 <<
897 scs_load_current <<
898 ret <<
899 SYM_FUNC_END(call_on_irq_stack) <<
900 NOKPROBE(call_on_irq_stack) <<
901 <<
902 #ifdef CONFIG_ARM_SDE_INTERFACE <<
903 <<
904 #include <asm/sdei.h> <<
905 #include <uapi/linux/arm_sdei.h> <<
906 <<
907 .macro sdei_handler_exit exit_mode <<
908 /* On success, this call never returns <<
909 cmp \exit_mode, #SDEI_EXIT_SMC <<
910 b.ne 99f <<
911 smc #0 <<
912 b . <<
913 99: hvc #0 <<
914 b . <<
915 .endm <<
916 <<
917 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 <<
918 /* <<
919 * The regular SDEI entry point may have been <<
920 * the kernel. This trampoline restores the ke <<
921 * argument accessible. <<
922 * <<
923 * This clobbers x4, __sdei_handler() will res <<
924 * copy. <<
925 */ <<
926 .pushsection ".entry.tramp.text", "ax" <<
927 SYM_CODE_START(__sdei_asm_entry_trampoline) <<
928 mrs x4, ttbr1_el1 <<
929 tbz x4, #USER_ASID_BIT, 1f <<
930 <<
931 tramp_map_kernel tmp=x4 <<
932 isb <<
933 mov x4, xzr <<
934 <<
935 /* <<
936 * Remember whether to unmap the kerne <<
937 */ <<
938 1: str x4, [x1, #(SDEI_EVENT_INTREGS <<
939 tramp_data_read_var x4, __sdei_asm <<
940 br x4 <<
941 SYM_CODE_END(__sdei_asm_entry_trampoline) <<
942 NOKPROBE(__sdei_asm_entry_trampoline) <<
943 <<
944 /* <<
945 * Make the exit call and restore the original <<
946 * <<
947 * x0 & x1: setup for the exit API call <<
948 * x2: exit_mode <<
949 * x4: struct sdei_registered_event argument f <<
950 */ <<
951 SYM_CODE_START(__sdei_asm_exit_trampoline) <<
952 ldr x4, [x4, #(SDEI_EVENT_INTREGS <<
953 cbnz x4, 1f <<
954 <<
955 tramp_unmap_kernel tmp=x4 <<
956 <<
957 1: sdei_handler_exit exit_mode=x2 <<
958 SYM_CODE_END(__sdei_asm_exit_trampoline) <<
959 NOKPROBE(__sdei_asm_exit_trampoline) <<
960 .popsection // .entry.tramp.text <<
961 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ <<
962 <<
963 /* <<
964 * Software Delegated Exception entry point. <<
965 * <<
966 * x0: Event number <<
967 * x1: struct sdei_registered_event argument f <<
968 * x2: interrupted PC <<
969 * x3: interrupted PSTATE <<
970 * x4: maybe clobbered by the trampoline <<
971 * <<
972 * Firmware has preserved x0->x17 for us, we m <<
973 * follow SMC-CC. We save (or retrieve) all th <<
974 * want them. <<
975 */ <<
976 SYM_CODE_START(__sdei_asm_handler) <<
977 stp x2, x3, [x1, #SDEI_EVENT_INTRE <<
978 stp x4, x5, [x1, #SDEI_EVENT_INTRE <<
979 stp x6, x7, [x1, #SDEI_EVENT_INTRE <<
980 stp x8, x9, [x1, #SDEI_EVENT_INTRE <<
981 stp x10, x11, [x1, #SDEI_EVENT_INT <<
982 stp x12, x13, [x1, #SDEI_EVENT_INT <<
983 stp x14, x15, [x1, #SDEI_EVENT_INT <<
984 stp x16, x17, [x1, #SDEI_EVENT_INT <<
985 stp x18, x19, [x1, #SDEI_EVENT_INT <<
986 stp x20, x21, [x1, #SDEI_EVENT_INT <<
987 stp x22, x23, [x1, #SDEI_EVENT_INT <<
988 stp x24, x25, [x1, #SDEI_EVENT_INT <<
989 stp x26, x27, [x1, #SDEI_EVENT_INT <<
990 stp x28, x29, [x1, #SDEI_EVENT_INT <<
991 mov x4, sp <<
992 stp lr, x4, [x1, #SDEI_EVENT_INTRE <<
993 <<
994 mov x19, x1 <<
995 <<
996 /* Store the registered-event for cras <<
997 ldrb w4, [x19, #SDEI_EVENT_PRIORITY <<
998 cbnz w4, 1f <<
999 adr_this_cpu dst=x5, sym=sdei_active_n <<
1000 b 2f <<
1001 1: adr_this_cpu dst=x5, sym=sdei_active_ <<
1002 2: str x19, [x5] <<
1003 <<
1004 #ifdef CONFIG_VMAP_STACK <<
1005 /* <<
1006 * entry.S may have been using sp as <<
1007 * this is a normal or critical event <<
1008 * stack for this CPU. <<
1009 */ <<
1010 cbnz w4, 1f <<
1011 ldr_this_cpu dst=x5, sym=sdei_stack_n <<
1012 b 2f <<
1013 1: ldr_this_cpu dst=x5, sym=sdei_stack_c <<
1014 2: mov x6, #SDEI_STACK_SIZE <<
1015 add x5, x5, x6 <<
1016 mov sp, x5 <<
1017 #endif <<
1018 <<
1019 #ifdef CONFIG_SHADOW_CALL_STACK <<
1020 /* Use a separate shadow call stack f <<
1021 cbnz w4, 3f <<
1022 ldr_this_cpu dst=scs_sp, sym=sdei_sha <<
1023 b 4f <<
1024 3: ldr_this_cpu dst=scs_sp, sym=sdei_sha <<
1025 4: <<
1026 #endif <<
1027 <<
1028 /* <<
1029 * We may have interrupted userspace, <<
1030 * return-to either of these. We can' <<
1031 */ <<
1032 mrs x28, sp_el0 <<
1033 ldr_this_cpu dst=x0, sym=__entry_t <<
1034 msr sp_el0, x0 <<
1035 <<
1036 /* If we interrupted the kernel point <<
1037 and x0, x3, #0xc <<
1038 mrs x1, CurrentEL <<
1039 cmp x0, x1 <<
1040 csel x29, x29, xzr, eq // fp <<
1041 csel x4, x2, xzr, eq // el <<
1042 <<
1043 stp x29, x4, [sp, #-16]! <<
1044 mov x29, sp <<
1045 <<
1046 add x0, x19, #SDEI_EVENT_INTREGS <<
1047 mov x1, x19 <<
1048 bl __sdei_handler <<
1049 <<
1050 msr sp_el0, x28 <<
1051 /* restore regs >x17 that we clobbere <<
1052 mov x4, x19 // keep x4 fo <<
1053 ldp x28, x29, [x4, #SDEI_EVENT_IN <<
1054 ldp x18, x19, [x4, #SDEI_EVENT_IN <<
1055 ldp lr, x1, [x4, #SDEI_EVENT_INTR <<
1056 mov sp, x1 <<
1057 <<
1058 mov x1, x0 // ad <<
1059 /* x0 = (x0 <= SDEI_EV_FAILED) ? <<
1060 * EVENT_COMPLETE:EVENT_COMPLETE_AND_ <<
1061 */ <<
1062 cmp x0, #SDEI_EV_FAILED <<
1063 mov_q x2, SDEI_1_0_FN_SDEI_EVENT_CO <<
1064 mov_q x3, SDEI_1_0_FN_SDEI_EVENT_CO <<
1065 csel x0, x2, x3, ls <<
1066 <<
1067 ldr_l x2, sdei_exit_mode <<
1068 <<
1069 /* Clear the registered-event seen by <<
1070 ldrb w3, [x4, #SDEI_EVENT_PRIORITY <<
1071 cbnz w3, 1f <<
1072 adr_this_cpu dst=x5, sym=sdei_active_ <<
1073 b 2f <<
1074 1: adr_this_cpu dst=x5, sym=sdei_active_ <<
1075 2: str xzr, [x5] <<
1076 <<
1077 alternative_if_not ARM64_UNMAP_KERNEL_AT_EL0 <<
1078 sdei_handler_exit exit_mode=x2 <<
1079 alternative_else_nop_endif <<
1080 <<
1081 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 <<
1082 tramp_alias dst=x5, sym=__sdei_as <<
1083 br x5 <<
1084 #endif <<
1085 SYM_CODE_END(__sdei_asm_handler) <<
1086 NOKPROBE(__sdei_asm_handler) <<
1087 285
1088 SYM_CODE_START(__sdei_handler_abort) !! 286 /* Linux flavoured syscalls. */
1089 mov_q x0, SDEI_1_0_FN_SDEI_EVENT_CO !! 287 #include "syscalls.h"
1090 adr x1, 1f <<
1091 ldr_l x2, sdei_exit_mode <<
1092 sdei_handler_exit exit_mode=x2 <<
1093 // exit the handler and jump to the n <<
1094 // Exit will stomp x0-x17, PSTATE, EL <<
1095 1: ret <<
1096 SYM_CODE_END(__sdei_handler_abort) <<
1097 NOKPROBE(__sdei_handler_abort) <<
1098 #endif /* CONFIG_ARM_SDE_INTERFACE */ <<
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