1 /* SPDX-License-Identifier: GPL-2.0-only */ !! 1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* !! 2 /* arch/sparc/kernel/entry.S: Sparc trap low-level entry points.
3 * Low-level exception handling code <<
4 * 3 *
5 * Copyright (C) 2012 ARM Ltd. !! 4 * Copyright (C) 1995, 2007 David S. Miller (davem@davemloft.net)
6 * Authors: Catalin Marinas <catalin.marina !! 5 * Copyright (C) 1996 Eddie C. Dost (ecd@skynet.be)
7 * Will Deacon <will.deacon@arm.co !! 6 * Copyright (C) 1996 Miguel de Icaza (miguel@nuclecu.unam.mx)
>> 7 * Copyright (C) 1996-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
>> 8 * Copyright (C) 1997 Anton Blanchard (anton@progsoc.uts.edu.au)
8 */ 9 */
9 10
10 #include <linux/arm-smccc.h> <<
11 #include <linux/init.h> <<
12 #include <linux/linkage.h> 11 #include <linux/linkage.h>
>> 12 #include <linux/errno.h>
13 13
14 #include <asm/alternative.h> !! 14 #include <asm/head.h>
15 #include <asm/assembler.h> !! 15 #include <asm/asi.h>
16 #include <asm/asm-offsets.h> !! 16 #include <asm/smp.h>
17 #include <asm/asm_pointer_auth.h> !! 17 #include <asm/contregs.h>
18 #include <asm/bug.h> <<
19 #include <asm/cpufeature.h> <<
20 #include <asm/errno.h> <<
21 #include <asm/esr.h> <<
22 #include <asm/irq.h> <<
23 #include <asm/memory.h> <<
24 #include <asm/mmu.h> <<
25 #include <asm/processor.h> <<
26 #include <asm/ptrace.h> 18 #include <asm/ptrace.h>
27 #include <asm/scs.h> !! 19 #include <asm/asm-offsets.h>
>> 20 #include <asm/psr.h>
>> 21 #include <asm/vaddrs.h>
>> 22 #include <asm/page.h>
>> 23 #include <asm/pgtable.h>
>> 24 #include <asm/winmacro.h>
>> 25 #include <asm/signal.h>
>> 26 #include <asm/obio.h>
>> 27 #include <asm/mxcc.h>
28 #include <asm/thread_info.h> 28 #include <asm/thread_info.h>
29 #include <asm/asm-uaccess.h> !! 29 #include <asm/param.h>
30 #include <asm/unistd.h> 30 #include <asm/unistd.h>
31 31
32 .macro clear_gp_regs !! 32 #include <asm/asmmacro.h>
33 .irp n,0,1,2,3,4,5,6,7,8,9,10,11,12 !! 33 #include <asm/export.h>
34 mov x\n, xzr <<
35 .endr <<
36 .endm <<
37 <<
38 .macro kernel_ventry, el:req, ht:req, <<
39 .align 7 <<
40 .Lventry_start\@: <<
41 .if \el == 0 <<
42 /* <<
43 * This must be the first instruction <<
44 * skipped by the trampoline vectors, <<
45 */ <<
46 b .Lskip_tramp_vectors_cleanup\@ <<
47 .if \regsize == 64 <<
48 mrs x30, tpidrro_el0 <<
49 msr tpidrro_el0, xzr <<
50 .else <<
51 mov x30, xzr <<
52 .endif <<
53 .Lskip_tramp_vectors_cleanup\@: <<
54 .endif <<
55 34
56 sub sp, sp, #PT_REGS_SIZE !! 35 #define curptr g6
57 #ifdef CONFIG_VMAP_STACK <<
58 /* <<
59 * Test whether the SP has overflowed, <<
60 * Task and IRQ stacks are aligned so <<
61 * should always be zero. <<
62 */ <<
63 add sp, sp, x0 <<
64 sub x0, sp, x0 <<
65 tbnz x0, #THREAD_SHIFT, 0f <<
66 sub x0, sp, x0 <<
67 sub sp, sp, x0 <<
68 b el\el\ht\()_\regsize\()_\label <<
69 36
70 0: !! 37 /* These are just handy. */
71 /* !! 38 #define _SV save %sp, -STACKFRAME_SZ, %sp
72 * Either we've just detected an overf !! 39 #define _RS restore
73 * while on the overflow stack. Either !! 40
74 * userspace, and can clobber EL0 regi !! 41 #define FLUSH_ALL_KERNEL_WINDOWS \
75 */ !! 42 _SV; _SV; _SV; _SV; _SV; _SV; _SV; \
76 !! 43 _RS; _RS; _RS; _RS; _RS; _RS; _RS;
77 /* Stash the original SP (minus PT_REG <<
78 msr tpidr_el0, x0 <<
79 44
80 /* Recover the original x0 value and s !! 45 .text
81 sub x0, sp, x0 <<
82 msr tpidrro_el0, x0 <<
83 46
84 /* Switch to the overflow stack */ !! 47 #ifdef CONFIG_KGDB
85 adr_this_cpu sp, overflow_stack + OVER !! 48 .align 4
>> 49 .globl arch_kgdb_breakpoint
>> 50 .type arch_kgdb_breakpoint,#function
>> 51 arch_kgdb_breakpoint:
>> 52 ta 0x7d
>> 53 retl
>> 54 nop
>> 55 .size arch_kgdb_breakpoint,.-arch_kgdb_breakpoint
>> 56 #endif
>> 57
>> 58 #if defined(CONFIG_BLK_DEV_FD) || defined(CONFIG_BLK_DEV_FD_MODULE)
>> 59 .align 4
>> 60 .globl floppy_hardint
>> 61 floppy_hardint:
>> 62 /*
>> 63 * This code cannot touch registers %l0 %l1 and %l2
>> 64 * because SAVE_ALL depends on their values. It depends
>> 65 * on %l3 also, but we regenerate it before a call.
>> 66 * Other registers are:
>> 67 * %l3 -- base address of fdc registers
>> 68 * %l4 -- pdma_vaddr
>> 69 * %l5 -- scratch for ld/st address
>> 70 * %l6 -- pdma_size
>> 71 * %l7 -- scratch [floppy byte, ld/st address, aux. data]
>> 72 */
>> 73
>> 74 /* Do we have work to do? */
>> 75 sethi %hi(doing_pdma), %l7
>> 76 ld [%l7 + %lo(doing_pdma)], %l7
>> 77 cmp %l7, 0
>> 78 be floppy_dosoftint
>> 79 nop
>> 80
>> 81 /* Load fdc register base */
>> 82 sethi %hi(fdc_status), %l3
>> 83 ld [%l3 + %lo(fdc_status)], %l3
>> 84
>> 85 /* Setup register addresses */
>> 86 sethi %hi(pdma_vaddr), %l5 ! transfer buffer
>> 87 ld [%l5 + %lo(pdma_vaddr)], %l4
>> 88 sethi %hi(pdma_size), %l5 ! bytes to go
>> 89 ld [%l5 + %lo(pdma_size)], %l6
>> 90 next_byte:
>> 91 ldub [%l3], %l7
>> 92
>> 93 andcc %l7, 0x80, %g0 ! Does fifo still have data
>> 94 bz floppy_fifo_emptied ! fifo has been emptied...
>> 95 andcc %l7, 0x20, %g0 ! in non-dma mode still?
>> 96 bz floppy_overrun ! nope, overrun
>> 97 andcc %l7, 0x40, %g0 ! 0=write 1=read
>> 98 bz floppy_write
>> 99 sub %l6, 0x1, %l6
>> 100
>> 101 /* Ok, actually read this byte */
>> 102 ldub [%l3 + 1], %l7
>> 103 orcc %g0, %l6, %g0
>> 104 stb %l7, [%l4]
>> 105 bne next_byte
>> 106 add %l4, 0x1, %l4
>> 107
>> 108 b floppy_tdone
>> 109 nop
>> 110
>> 111 floppy_write:
>> 112 /* Ok, actually write this byte */
>> 113 ldub [%l4], %l7
>> 114 orcc %g0, %l6, %g0
>> 115 stb %l7, [%l3 + 1]
>> 116 bne next_byte
>> 117 add %l4, 0x1, %l4
>> 118
>> 119 /* fall through... */
>> 120 floppy_tdone:
>> 121 sethi %hi(pdma_vaddr), %l5
>> 122 st %l4, [%l5 + %lo(pdma_vaddr)]
>> 123 sethi %hi(pdma_size), %l5
>> 124 st %l6, [%l5 + %lo(pdma_size)]
>> 125 /* Flip terminal count pin */
>> 126 set auxio_register, %l7
>> 127 ld [%l7], %l7
>> 128
>> 129 ldub [%l7], %l5
>> 130
>> 131 or %l5, 0xc2, %l5
>> 132 stb %l5, [%l7]
>> 133 andn %l5, 0x02, %l5
86 134
87 /* !! 135 2:
88 * Check whether we were already on th !! 136 /* Kill some time so the bits set */
89 * after panic() re-enables interrupts !! 137 WRITE_PAUSE
90 */ !! 138 WRITE_PAUSE
91 mrs x0, tpidr_el0 !! 139
92 sub x0, sp, x0 !! 140 stb %l5, [%l7]
93 tst x0, #~(OVERFLOW_STACK_SIZE - 1 !! 141
94 b.ne __bad_stack !! 142 /* Prevent recursion */
95 !! 143 sethi %hi(doing_pdma), %l7
96 /* We were already on the overflow sta !! 144 b floppy_dosoftint
97 sub sp, sp, x0 !! 145 st %g0, [%l7 + %lo(doing_pdma)]
98 mrs x0, tpidrro_el0 !! 146
99 #endif !! 147 /* We emptied the FIFO, but we haven't read everything
100 b el\el\ht\()_\regsize\()_\label !! 148 * as of yet. Store the current transfer address and
101 .org .Lventry_start\@ + 128 // Did we over !! 149 * bytes left to read so we can continue when the next
102 .endm !! 150 * fast IRQ comes in.
103 !! 151 */
104 .macro tramp_alias, dst, sym !! 152 floppy_fifo_emptied:
105 .set .Lalias\@, TRAMP_VALIAS + \sym !! 153 sethi %hi(pdma_vaddr), %l5
106 movz \dst, :abs_g2_s:.Lalias\@ !! 154 st %l4, [%l5 + %lo(pdma_vaddr)]
107 movk \dst, :abs_g1_nc:.Lalias\@ !! 155 sethi %hi(pdma_size), %l7
108 movk \dst, :abs_g0_nc:.Lalias\@ !! 156 st %l6, [%l7 + %lo(pdma_size)]
109 .endm !! 157
>> 158 /* Restore condition codes */
>> 159 wr %l0, 0x0, %psr
>> 160 WRITE_PAUSE
>> 161
>> 162 jmp %l1
>> 163 rett %l2
>> 164
>> 165 floppy_overrun:
>> 166 sethi %hi(pdma_vaddr), %l5
>> 167 st %l4, [%l5 + %lo(pdma_vaddr)]
>> 168 sethi %hi(pdma_size), %l5
>> 169 st %l6, [%l5 + %lo(pdma_size)]
>> 170 /* Prevent recursion */
>> 171 sethi %hi(doing_pdma), %l7
>> 172 st %g0, [%l7 + %lo(doing_pdma)]
>> 173
>> 174 /* fall through... */
>> 175 floppy_dosoftint:
>> 176 rd %wim, %l3
>> 177 SAVE_ALL
>> 178
>> 179 /* Set all IRQs off. */
>> 180 or %l0, PSR_PIL, %l4
>> 181 wr %l4, 0x0, %psr
>> 182 WRITE_PAUSE
>> 183 wr %l4, PSR_ET, %psr
>> 184 WRITE_PAUSE
>> 185
>> 186 mov 11, %o0 ! floppy irq level (unused anyway)
>> 187 mov %g0, %o1 ! devid is not used in fast interrupts
>> 188 call sparc_floppy_irq
>> 189 add %sp, STACKFRAME_SZ, %o2 ! struct pt_regs *regs
>> 190
>> 191 RESTORE_ALL
>> 192
>> 193 #endif /* (CONFIG_BLK_DEV_FD) */
>> 194
>> 195 /* Bad trap handler */
>> 196 .globl bad_trap_handler
>> 197 bad_trap_handler:
>> 198 SAVE_ALL
>> 199
>> 200 wr %l0, PSR_ET, %psr
>> 201 WRITE_PAUSE
>> 202
>> 203 add %sp, STACKFRAME_SZ, %o0 ! pt_regs
>> 204 call do_hw_interrupt
>> 205 mov %l7, %o1 ! trap number
>> 206
>> 207 RESTORE_ALL
>> 208
>> 209 /* For now all IRQ's not registered get sent here. handler_irq() will
>> 210 * see if a routine is registered to handle this interrupt and if not
>> 211 * it will say so on the console.
>> 212 */
110 213
111 /* !! 214 .align 4
112 * This macro corrupts x0-x3. It is th !! 215 .globl real_irq_entry, patch_handler_irq
113 * them if required. !! 216 real_irq_entry:
114 */ !! 217 SAVE_ALL
115 .macro apply_ssbd, state, tmp1, tmp2 !! 218
116 alternative_cb ARM64_ALWAYS_SYSTEM, spectre_v !! 219 #ifdef CONFIG_SMP
117 b .L__asm_ssbd_skip\@ !! 220 .globl patchme_maybe_smp_msg
118 alternative_cb_end !! 221
119 ldr_this_cpu \tmp2, arm64_ssbd_call !! 222 cmp %l7, 11
120 cbz \tmp2, .L__asm_ssbd_skip\@ !! 223 patchme_maybe_smp_msg:
121 ldr \tmp2, [tsk, #TSK_TI_FLAGS] !! 224 bgu maybe_smp4m_msg
122 tbnz \tmp2, #TIF_SSBD, .L__asm_ssbd !! 225 nop
123 mov w0, #ARM_SMCCC_ARCH_WORKAROUND !! 226 #endif
124 mov w1, #\state !! 227
125 alternative_cb ARM64_ALWAYS_SYSTEM, smccc_pat !! 228 real_irq_continue:
126 nop !! 229 or %l0, PSR_PIL, %g2
127 alternative_cb_end !! 230 wr %g2, 0x0, %psr
128 .L__asm_ssbd_skip\@: !! 231 WRITE_PAUSE
129 .endm !! 232 wr %g2, PSR_ET, %psr
130 !! 233 WRITE_PAUSE
131 /* Check for MTE asynchronous tag chec !! 234 mov %l7, %o0 ! irq level
132 .macro check_mte_async_tcf, tmp, ti_fl !! 235 patch_handler_irq:
133 #ifdef CONFIG_ARM64_MTE !! 236 call handler_irq
134 .arch_extension lse !! 237 add %sp, STACKFRAME_SZ, %o1 ! pt_regs ptr
135 alternative_if_not ARM64_MTE !! 238 or %l0, PSR_PIL, %g2 ! restore PIL after handler_irq
136 b 1f !! 239 wr %g2, PSR_ET, %psr ! keep ET up
137 alternative_else_nop_endif !! 240 WRITE_PAUSE
138 /* !! 241
139 * Asynchronous tag check faults are o !! 242 RESTORE_ALL
140 * ASYM (3) modes. In each of these mo !! 243
141 * set, so skip the check if it is uns !! 244 #ifdef CONFIG_SMP
>> 245 /* SMP per-cpu ticker interrupts are handled specially. */
>> 246 smp4m_ticker:
>> 247 bne real_irq_continue+4
>> 248 or %l0, PSR_PIL, %g2
>> 249 wr %g2, 0x0, %psr
>> 250 WRITE_PAUSE
>> 251 wr %g2, PSR_ET, %psr
>> 252 WRITE_PAUSE
>> 253 call smp4m_percpu_timer_interrupt
>> 254 add %sp, STACKFRAME_SZ, %o0
>> 255 wr %l0, PSR_ET, %psr
>> 256 WRITE_PAUSE
>> 257 RESTORE_ALL
>> 258
>> 259 #define GET_PROCESSOR4M_ID(reg) \
>> 260 rd %tbr, %reg; \
>> 261 srl %reg, 12, %reg; \
>> 262 and %reg, 3, %reg;
>> 263
>> 264 /* Here is where we check for possible SMP IPI passed to us
>> 265 * on some level other than 15 which is the NMI and only used
>> 266 * for cross calls. That has a separate entry point below.
>> 267 *
>> 268 * IPIs are sent on Level 12, 13 and 14. See IRQ_IPI_*.
142 */ 269 */
143 tbz \thread_sctlr, #(SCTLR_EL1_TCF !! 270 maybe_smp4m_msg:
144 mrs_s \tmp, SYS_TFSRE0_EL1 !! 271 GET_PROCESSOR4M_ID(o3)
145 tbz \tmp, #SYS_TFSR_EL1_TF0_SHIFT, !! 272 sethi %hi(sun4m_irq_percpu), %l5
146 /* Asynchronous TCF occurred for TTBR0 !! 273 sll %o3, 2, %o3
147 mov \tmp, #_TIF_MTE_ASYNC_FAULT !! 274 or %l5, %lo(sun4m_irq_percpu), %o5
148 add \ti_flags, tsk, #TSK_TI_FLAGS !! 275 sethi %hi(0x70000000), %o2 ! Check all soft-IRQs
149 stset \tmp, [\ti_flags] !! 276 ld [%o5 + %o3], %o1
150 1: !! 277 ld [%o1 + 0x00], %o3 ! sun4m_irq_percpu[cpu]->pending
151 #endif !! 278 andcc %o3, %o2, %g0
152 .endm !! 279 be,a smp4m_ticker
>> 280 cmp %l7, 14
>> 281 /* Soft-IRQ IPI */
>> 282 st %o2, [%o1 + 0x04] ! sun4m_irq_percpu[cpu]->clear=0x70000000
>> 283 WRITE_PAUSE
>> 284 ld [%o1 + 0x00], %g0 ! sun4m_irq_percpu[cpu]->pending
>> 285 WRITE_PAUSE
>> 286 or %l0, PSR_PIL, %l4
>> 287 wr %l4, 0x0, %psr
>> 288 WRITE_PAUSE
>> 289 wr %l4, PSR_ET, %psr
>> 290 WRITE_PAUSE
>> 291 srl %o3, 28, %o2 ! shift for simpler checks below
>> 292 maybe_smp4m_msg_check_single:
>> 293 andcc %o2, 0x1, %g0
>> 294 beq,a maybe_smp4m_msg_check_mask
>> 295 andcc %o2, 0x2, %g0
>> 296 call smp_call_function_single_interrupt
>> 297 nop
>> 298 andcc %o2, 0x2, %g0
>> 299 maybe_smp4m_msg_check_mask:
>> 300 beq,a maybe_smp4m_msg_check_resched
>> 301 andcc %o2, 0x4, %g0
>> 302 call smp_call_function_interrupt
>> 303 nop
>> 304 andcc %o2, 0x4, %g0
>> 305 maybe_smp4m_msg_check_resched:
>> 306 /* rescheduling is done in RESTORE_ALL regardless, but incr stats */
>> 307 beq,a maybe_smp4m_msg_out
>> 308 nop
>> 309 call smp_resched_interrupt
>> 310 nop
>> 311 maybe_smp4m_msg_out:
>> 312 RESTORE_ALL
>> 313
>> 314 .align 4
>> 315 .globl linux_trap_ipi15_sun4m
>> 316 linux_trap_ipi15_sun4m:
>> 317 SAVE_ALL
>> 318 sethi %hi(0x80000000), %o2
>> 319 GET_PROCESSOR4M_ID(o0)
>> 320 sethi %hi(sun4m_irq_percpu), %l5
>> 321 or %l5, %lo(sun4m_irq_percpu), %o5
>> 322 sll %o0, 2, %o0
>> 323 ld [%o5 + %o0], %o5
>> 324 ld [%o5 + 0x00], %o3 ! sun4m_irq_percpu[cpu]->pending
>> 325 andcc %o3, %o2, %g0
>> 326 be sun4m_nmi_error ! Must be an NMI async memory error
>> 327 st %o2, [%o5 + 0x04] ! sun4m_irq_percpu[cpu]->clear=0x80000000
>> 328 WRITE_PAUSE
>> 329 ld [%o5 + 0x00], %g0 ! sun4m_irq_percpu[cpu]->pending
>> 330 WRITE_PAUSE
>> 331 or %l0, PSR_PIL, %l4
>> 332 wr %l4, 0x0, %psr
>> 333 WRITE_PAUSE
>> 334 wr %l4, PSR_ET, %psr
>> 335 WRITE_PAUSE
>> 336 call smp4m_cross_call_irq
>> 337 nop
>> 338 b ret_trap_lockless_ipi
>> 339 clr %l6
>> 340
>> 341 .globl smp4d_ticker
>> 342 /* SMP per-cpu ticker interrupts are handled specially. */
>> 343 smp4d_ticker:
>> 344 SAVE_ALL
>> 345 or %l0, PSR_PIL, %g2
>> 346 sethi %hi(CC_ICLR), %o0
>> 347 sethi %hi(1 << 14), %o1
>> 348 or %o0, %lo(CC_ICLR), %o0
>> 349 stha %o1, [%o0] ASI_M_MXCC /* Clear PIL 14 in MXCC's ICLR */
>> 350 wr %g2, 0x0, %psr
>> 351 WRITE_PAUSE
>> 352 wr %g2, PSR_ET, %psr
>> 353 WRITE_PAUSE
>> 354 call smp4d_percpu_timer_interrupt
>> 355 add %sp, STACKFRAME_SZ, %o0
>> 356 wr %l0, PSR_ET, %psr
>> 357 WRITE_PAUSE
>> 358 RESTORE_ALL
>> 359
>> 360 .align 4
>> 361 .globl linux_trap_ipi15_sun4d
>> 362 linux_trap_ipi15_sun4d:
>> 363 SAVE_ALL
>> 364 sethi %hi(CC_BASE), %o4
>> 365 sethi %hi(MXCC_ERR_ME|MXCC_ERR_PEW|MXCC_ERR_ASE|MXCC_ERR_PEE), %o2
>> 366 or %o4, (CC_EREG - CC_BASE), %o0
>> 367 ldda [%o0] ASI_M_MXCC, %o0
>> 368 andcc %o0, %o2, %g0
>> 369 bne 1f
>> 370 sethi %hi(BB_STAT2), %o2
>> 371 lduba [%o2] ASI_M_CTL, %o2
>> 372 andcc %o2, BB_STAT2_MASK, %g0
>> 373 bne 2f
>> 374 or %o4, (CC_ICLR - CC_BASE), %o0
>> 375 sethi %hi(1 << 15), %o1
>> 376 stha %o1, [%o0] ASI_M_MXCC /* Clear PIL 15 in MXCC's ICLR */
>> 377 or %l0, PSR_PIL, %l4
>> 378 wr %l4, 0x0, %psr
>> 379 WRITE_PAUSE
>> 380 wr %l4, PSR_ET, %psr
>> 381 WRITE_PAUSE
>> 382 call smp4d_cross_call_irq
>> 383 nop
>> 384 b ret_trap_lockless_ipi
>> 385 clr %l6
>> 386
>> 387 1: /* MXCC error */
>> 388 2: /* BB error */
>> 389 /* Disable PIL 15 */
>> 390 set CC_IMSK, %l4
>> 391 lduha [%l4] ASI_M_MXCC, %l5
>> 392 sethi %hi(1 << 15), %l7
>> 393 or %l5, %l7, %l5
>> 394 stha %l5, [%l4] ASI_M_MXCC
>> 395 /* FIXME */
>> 396 1: b,a 1b
>> 397
>> 398 .globl smpleon_ipi
>> 399 .extern leon_ipi_interrupt
>> 400 /* SMP per-cpu IPI interrupts are handled specially. */
>> 401 smpleon_ipi:
>> 402 SAVE_ALL
>> 403 or %l0, PSR_PIL, %g2
>> 404 wr %g2, 0x0, %psr
>> 405 WRITE_PAUSE
>> 406 wr %g2, PSR_ET, %psr
>> 407 WRITE_PAUSE
>> 408 call leonsmp_ipi_interrupt
>> 409 add %sp, STACKFRAME_SZ, %o1 ! pt_regs
>> 410 wr %l0, PSR_ET, %psr
>> 411 WRITE_PAUSE
>> 412 RESTORE_ALL
>> 413
>> 414 .align 4
>> 415 .globl linux_trap_ipi15_leon
>> 416 linux_trap_ipi15_leon:
>> 417 SAVE_ALL
>> 418 or %l0, PSR_PIL, %l4
>> 419 wr %l4, 0x0, %psr
>> 420 WRITE_PAUSE
>> 421 wr %l4, PSR_ET, %psr
>> 422 WRITE_PAUSE
>> 423 call leon_cross_call_irq
>> 424 nop
>> 425 b ret_trap_lockless_ipi
>> 426 clr %l6
>> 427
>> 428 #endif /* CONFIG_SMP */
>> 429
>> 430 /* This routine handles illegal instructions and privileged
>> 431 * instruction attempts from user code.
>> 432 */
>> 433 .align 4
>> 434 .globl bad_instruction
>> 435 bad_instruction:
>> 436 sethi %hi(0xc1f80000), %l4
>> 437 ld [%l1], %l5
>> 438 sethi %hi(0x81d80000), %l7
>> 439 and %l5, %l4, %l5
>> 440 cmp %l5, %l7
>> 441 be 1f
>> 442 SAVE_ALL
>> 443
>> 444 wr %l0, PSR_ET, %psr ! re-enable traps
>> 445 WRITE_PAUSE
>> 446
>> 447 add %sp, STACKFRAME_SZ, %o0
>> 448 mov %l1, %o1
>> 449 mov %l2, %o2
>> 450 call do_illegal_instruction
>> 451 mov %l0, %o3
>> 452
>> 453 RESTORE_ALL
>> 454
>> 455 1: /* unimplemented flush - just skip */
>> 456 jmpl %l2, %g0
>> 457 rett %l2 + 4
>> 458
>> 459 .align 4
>> 460 .globl priv_instruction
>> 461 priv_instruction:
>> 462 SAVE_ALL
>> 463
>> 464 wr %l0, PSR_ET, %psr
>> 465 WRITE_PAUSE
>> 466
>> 467 add %sp, STACKFRAME_SZ, %o0
>> 468 mov %l1, %o1
>> 469 mov %l2, %o2
>> 470 call do_priv_instruction
>> 471 mov %l0, %o3
>> 472
>> 473 RESTORE_ALL
>> 474
>> 475 /* This routine handles unaligned data accesses. */
>> 476 .align 4
>> 477 .globl mna_handler
>> 478 mna_handler:
>> 479 andcc %l0, PSR_PS, %g0
>> 480 be mna_fromuser
>> 481 nop
>> 482
>> 483 SAVE_ALL
>> 484
>> 485 wr %l0, PSR_ET, %psr
>> 486 WRITE_PAUSE
>> 487
>> 488 ld [%l1], %o1
>> 489 call kernel_unaligned_trap
>> 490 add %sp, STACKFRAME_SZ, %o0
>> 491
>> 492 RESTORE_ALL
>> 493
>> 494 mna_fromuser:
>> 495 SAVE_ALL
>> 496
>> 497 wr %l0, PSR_ET, %psr ! re-enable traps
>> 498 WRITE_PAUSE
>> 499
>> 500 ld [%l1], %o1
>> 501 call user_unaligned_trap
>> 502 add %sp, STACKFRAME_SZ, %o0
>> 503
>> 504 RESTORE_ALL
>> 505
>> 506 /* This routine handles floating point disabled traps. */
>> 507 .align 4
>> 508 .globl fpd_trap_handler
>> 509 fpd_trap_handler:
>> 510 SAVE_ALL
>> 511
>> 512 wr %l0, PSR_ET, %psr ! re-enable traps
>> 513 WRITE_PAUSE
>> 514
>> 515 add %sp, STACKFRAME_SZ, %o0
>> 516 mov %l1, %o1
>> 517 mov %l2, %o2
>> 518 call do_fpd_trap
>> 519 mov %l0, %o3
>> 520
>> 521 RESTORE_ALL
>> 522
>> 523 /* This routine handles Floating Point Exceptions. */
>> 524 .align 4
>> 525 .globl fpe_trap_handler
>> 526 fpe_trap_handler:
>> 527 set fpsave_magic, %l5
>> 528 cmp %l1, %l5
>> 529 be 1f
>> 530 sethi %hi(fpsave), %l5
>> 531 or %l5, %lo(fpsave), %l5
>> 532 cmp %l1, %l5
>> 533 bne 2f
>> 534 sethi %hi(fpsave_catch2), %l5
>> 535 or %l5, %lo(fpsave_catch2), %l5
>> 536 wr %l0, 0x0, %psr
>> 537 WRITE_PAUSE
>> 538 jmp %l5
>> 539 rett %l5 + 4
>> 540 1:
>> 541 sethi %hi(fpsave_catch), %l5
>> 542 or %l5, %lo(fpsave_catch), %l5
>> 543 wr %l0, 0x0, %psr
>> 544 WRITE_PAUSE
>> 545 jmp %l5
>> 546 rett %l5 + 4
153 547
154 /* Clear the MTE asynchronous tag chec !! 548 2:
155 .macro clear_mte_async_tcf thread_sctl !! 549 SAVE_ALL
156 #ifdef CONFIG_ARM64_MTE <<
157 alternative_if ARM64_MTE <<
158 /* See comment in check_mte_async_tcf <<
159 tbz \thread_sctlr, #(SCTLR_EL1_TCF <<
160 dsb ish <<
161 msr_s SYS_TFSRE0_EL1, xzr <<
162 1: <<
163 alternative_else_nop_endif <<
164 #endif <<
165 .endm <<
166 550
167 .macro mte_set_gcr, mte_ctrl, tmp !! 551 wr %l0, PSR_ET, %psr ! re-enable traps
168 #ifdef CONFIG_ARM64_MTE !! 552 WRITE_PAUSE
169 ubfx \tmp, \mte_ctrl, #MTE_CTRL_GCR <<
170 orr \tmp, \tmp, #SYS_GCR_EL1_RRND <<
171 msr_s SYS_GCR_EL1, \tmp <<
172 #endif <<
173 .endm <<
174 553
175 .macro mte_set_kernel_gcr, tmp, tmp2 !! 554 add %sp, STACKFRAME_SZ, %o0
176 #ifdef CONFIG_KASAN_HW_TAGS !! 555 mov %l1, %o1
177 alternative_cb ARM64_ALWAYS_SYSTEM, kasan_hw_ !! 556 mov %l2, %o2
178 b 1f !! 557 call do_fpe_trap
179 alternative_cb_end !! 558 mov %l0, %o3
180 mov \tmp, KERNEL_GCR_EL1 !! 559
181 msr_s SYS_GCR_EL1, \tmp !! 560 RESTORE_ALL
182 1: !! 561
183 #endif !! 562 /* This routine handles Tag Overflow Exceptions. */
184 .endm !! 563 .align 4
>> 564 .globl do_tag_overflow
>> 565 do_tag_overflow:
>> 566 SAVE_ALL
>> 567
>> 568 wr %l0, PSR_ET, %psr ! re-enable traps
>> 569 WRITE_PAUSE
>> 570
>> 571 add %sp, STACKFRAME_SZ, %o0
>> 572 mov %l1, %o1
>> 573 mov %l2, %o2
>> 574 call handle_tag_overflow
>> 575 mov %l0, %o3
>> 576
>> 577 RESTORE_ALL
>> 578
>> 579 /* This routine handles Watchpoint Exceptions. */
>> 580 .align 4
>> 581 .globl do_watchpoint
>> 582 do_watchpoint:
>> 583 SAVE_ALL
>> 584
>> 585 wr %l0, PSR_ET, %psr ! re-enable traps
>> 586 WRITE_PAUSE
>> 587
>> 588 add %sp, STACKFRAME_SZ, %o0
>> 589 mov %l1, %o1
>> 590 mov %l2, %o2
>> 591 call handle_watchpoint
>> 592 mov %l0, %o3
>> 593
>> 594 RESTORE_ALL
>> 595
>> 596 /* This routine handles Register Access Exceptions. */
>> 597 .align 4
>> 598 .globl do_reg_access
>> 599 do_reg_access:
>> 600 SAVE_ALL
>> 601
>> 602 wr %l0, PSR_ET, %psr ! re-enable traps
>> 603 WRITE_PAUSE
>> 604
>> 605 add %sp, STACKFRAME_SZ, %o0
>> 606 mov %l1, %o1
>> 607 mov %l2, %o2
>> 608 call handle_reg_access
>> 609 mov %l0, %o3
>> 610
>> 611 RESTORE_ALL
>> 612
>> 613 /* This routine handles Co-Processor Disabled Exceptions. */
>> 614 .align 4
>> 615 .globl do_cp_disabled
>> 616 do_cp_disabled:
>> 617 SAVE_ALL
>> 618
>> 619 wr %l0, PSR_ET, %psr ! re-enable traps
>> 620 WRITE_PAUSE
>> 621
>> 622 add %sp, STACKFRAME_SZ, %o0
>> 623 mov %l1, %o1
>> 624 mov %l2, %o2
>> 625 call handle_cp_disabled
>> 626 mov %l0, %o3
>> 627
>> 628 RESTORE_ALL
>> 629
>> 630 /* This routine handles Co-Processor Exceptions. */
>> 631 .align 4
>> 632 .globl do_cp_exception
>> 633 do_cp_exception:
>> 634 SAVE_ALL
>> 635
>> 636 wr %l0, PSR_ET, %psr ! re-enable traps
>> 637 WRITE_PAUSE
>> 638
>> 639 add %sp, STACKFRAME_SZ, %o0
>> 640 mov %l1, %o1
>> 641 mov %l2, %o2
>> 642 call handle_cp_exception
>> 643 mov %l0, %o3
>> 644
>> 645 RESTORE_ALL
>> 646
>> 647 /* This routine handles Hardware Divide By Zero Exceptions. */
>> 648 .align 4
>> 649 .globl do_hw_divzero
>> 650 do_hw_divzero:
>> 651 SAVE_ALL
>> 652
>> 653 wr %l0, PSR_ET, %psr ! re-enable traps
>> 654 WRITE_PAUSE
>> 655
>> 656 add %sp, STACKFRAME_SZ, %o0
>> 657 mov %l1, %o1
>> 658 mov %l2, %o2
>> 659 call handle_hw_divzero
>> 660 mov %l0, %o3
>> 661
>> 662 RESTORE_ALL
>> 663
>> 664 .align 4
>> 665 .globl do_flush_windows
>> 666 do_flush_windows:
>> 667 SAVE_ALL
>> 668
>> 669 wr %l0, PSR_ET, %psr
>> 670 WRITE_PAUSE
>> 671
>> 672 andcc %l0, PSR_PS, %g0
>> 673 bne dfw_kernel
>> 674 nop
>> 675
>> 676 call flush_user_windows
>> 677 nop
>> 678
>> 679 /* Advance over the trap instruction. */
>> 680 ld [%sp + STACKFRAME_SZ + PT_NPC], %l1
>> 681 add %l1, 0x4, %l2
>> 682 st %l1, [%sp + STACKFRAME_SZ + PT_PC]
>> 683 st %l2, [%sp + STACKFRAME_SZ + PT_NPC]
>> 684
>> 685 RESTORE_ALL
>> 686
>> 687 .globl flush_patch_one
>> 688
>> 689 /* We get these for debugging routines using __builtin_return_address() */
>> 690 dfw_kernel:
>> 691 flush_patch_one:
>> 692 FLUSH_ALL_KERNEL_WINDOWS
>> 693
>> 694 /* Advance over the trap instruction. */
>> 695 ld [%sp + STACKFRAME_SZ + PT_NPC], %l1
>> 696 add %l1, 0x4, %l2
>> 697 st %l1, [%sp + STACKFRAME_SZ + PT_PC]
>> 698 st %l2, [%sp + STACKFRAME_SZ + PT_NPC]
>> 699
>> 700 RESTORE_ALL
>> 701
>> 702 /* The getcc software trap. The user wants the condition codes from
>> 703 * the %psr in register %g1.
>> 704 */
>> 705
>> 706 .align 4
>> 707 .globl getcc_trap_handler
>> 708 getcc_trap_handler:
>> 709 srl %l0, 20, %g1 ! give user
>> 710 and %g1, 0xf, %g1 ! only ICC bits in %psr
>> 711 jmp %l2 ! advance over trap instruction
>> 712 rett %l2 + 0x4 ! like this...
>> 713
>> 714 /* The setcc software trap. The user has condition codes in %g1
>> 715 * that it would like placed in the %psr. Be careful not to flip
>> 716 * any unintentional bits!
>> 717 */
>> 718
>> 719 .align 4
>> 720 .globl setcc_trap_handler
>> 721 setcc_trap_handler:
>> 722 sll %g1, 0x14, %l4
>> 723 set PSR_ICC, %l5
>> 724 andn %l0, %l5, %l0 ! clear ICC bits in %psr
>> 725 and %l4, %l5, %l4 ! clear non-ICC bits in user value
>> 726 or %l4, %l0, %l4 ! or them in... mix mix mix
>> 727
>> 728 wr %l4, 0x0, %psr ! set new %psr
>> 729 WRITE_PAUSE ! TI scumbags...
>> 730
>> 731 jmp %l2 ! advance over trap instruction
>> 732 rett %l2 + 0x4 ! like this...
>> 733
>> 734 sun4m_nmi_error:
>> 735 /* NMI async memory error handling. */
>> 736 sethi %hi(0x80000000), %l4
>> 737 sethi %hi(sun4m_irq_global), %o5
>> 738 ld [%o5 + %lo(sun4m_irq_global)], %l5
>> 739 st %l4, [%l5 + 0x0c] ! sun4m_irq_global->mask_set=0x80000000
>> 740 WRITE_PAUSE
>> 741 ld [%l5 + 0x00], %g0 ! sun4m_irq_global->pending
>> 742 WRITE_PAUSE
>> 743 or %l0, PSR_PIL, %l4
>> 744 wr %l4, 0x0, %psr
>> 745 WRITE_PAUSE
>> 746 wr %l4, PSR_ET, %psr
>> 747 WRITE_PAUSE
>> 748 call sun4m_nmi
>> 749 nop
>> 750 st %l4, [%l5 + 0x08] ! sun4m_irq_global->mask_clear=0x80000000
>> 751 WRITE_PAUSE
>> 752 ld [%l5 + 0x00], %g0 ! sun4m_irq_global->pending
>> 753 WRITE_PAUSE
>> 754 RESTORE_ALL
>> 755
>> 756 #ifndef CONFIG_SMP
>> 757 .align 4
>> 758 .globl linux_trap_ipi15_sun4m
>> 759 linux_trap_ipi15_sun4m:
>> 760 SAVE_ALL
>> 761
>> 762 ba sun4m_nmi_error
>> 763 nop
>> 764 #endif /* CONFIG_SMP */
>> 765
>> 766 .align 4
>> 767 .globl srmmu_fault
>> 768 srmmu_fault:
>> 769 mov 0x400, %l5
>> 770 mov 0x300, %l4
>> 771
>> 772 LEON_PI(lda [%l5] ASI_LEON_MMUREGS, %l6) ! read sfar first
>> 773 SUN_PI_(lda [%l5] ASI_M_MMUREGS, %l6) ! read sfar first
>> 774
>> 775 LEON_PI(lda [%l4] ASI_LEON_MMUREGS, %l5) ! read sfsr last
>> 776 SUN_PI_(lda [%l4] ASI_M_MMUREGS, %l5) ! read sfsr last
>> 777
>> 778 andn %l6, 0xfff, %l6
>> 779 srl %l5, 6, %l5 ! and encode all info into l7
>> 780
>> 781 and %l5, 2, %l5
>> 782 or %l5, %l6, %l6
>> 783
>> 784 or %l6, %l7, %l7 ! l7 = [addr,write,txtfault]
>> 785
>> 786 SAVE_ALL
>> 787
>> 788 mov %l7, %o1
>> 789 mov %l7, %o2
>> 790 and %o1, 1, %o1 ! arg2 = text_faultp
>> 791 mov %l7, %o3
>> 792 and %o2, 2, %o2 ! arg3 = writep
>> 793 andn %o3, 0xfff, %o3 ! arg4 = faulting address
>> 794
>> 795 wr %l0, PSR_ET, %psr
>> 796 WRITE_PAUSE
>> 797
>> 798 call do_sparc_fault
>> 799 add %sp, STACKFRAME_SZ, %o0 ! arg1 = pt_regs ptr
>> 800
>> 801 RESTORE_ALL
>> 802
>> 803 .align 4
>> 804 .globl sys_nis_syscall
>> 805 sys_nis_syscall:
>> 806 mov %o7, %l5
>> 807 add %sp, STACKFRAME_SZ, %o0 ! pt_regs *regs arg
>> 808 call c_sys_nis_syscall
>> 809 mov %l5, %o7
>> 810
>> 811 sunos_execv:
>> 812 .globl sunos_execv
>> 813 b sys_execve
>> 814 clr %i2
>> 815
>> 816 .align 4
>> 817 .globl sys_sparc_pipe
>> 818 sys_sparc_pipe:
>> 819 mov %o7, %l5
>> 820 add %sp, STACKFRAME_SZ, %o0 ! pt_regs *regs arg
>> 821 call sparc_pipe
>> 822 mov %l5, %o7
>> 823
>> 824 .align 4
>> 825 .globl sys_sigstack
>> 826 sys_sigstack:
>> 827 mov %o7, %l5
>> 828 mov %fp, %o2
>> 829 call do_sys_sigstack
>> 830 mov %l5, %o7
>> 831
>> 832 .align 4
>> 833 .globl sys_sigreturn
>> 834 sys_sigreturn:
>> 835 call do_sigreturn
>> 836 add %sp, STACKFRAME_SZ, %o0
>> 837
>> 838 ld [%curptr + TI_FLAGS], %l5
>> 839 andcc %l5, _TIF_SYSCALL_TRACE, %g0
>> 840 be 1f
>> 841 nop
185 842
186 .macro mte_set_user_gcr, tsk, tmp, tmp !! 843 call syscall_trace
187 #ifdef CONFIG_KASAN_HW_TAGS !! 844 mov 1, %o1
188 alternative_cb ARM64_ALWAYS_SYSTEM, kasan_hw_ <<
189 b 1f <<
190 alternative_cb_end <<
191 ldr \tmp, [\tsk, #THREAD_MTE_CTRL] <<
192 845
193 mte_set_gcr \tmp, \tmp2 <<
194 1: 846 1:
195 #endif !! 847 /* We don't want to muck with user registers like a
196 .endm !! 848 * normal syscall, just return.
197 <<
198 .macro kernel_entry, el, regsize = 64 <<
199 .if \el == 0 <<
200 alternative_insn nop, SET_PSTATE_DIT(1 <<
201 .endif <<
202 .if \regsize == 32 <<
203 mov w0, w0 <<
204 .endif <<
205 stp x0, x1, [sp, #16 * 0] <<
206 stp x2, x3, [sp, #16 * 1] <<
207 stp x4, x5, [sp, #16 * 2] <<
208 stp x6, x7, [sp, #16 * 3] <<
209 stp x8, x9, [sp, #16 * 4] <<
210 stp x10, x11, [sp, #16 * 5] <<
211 stp x12, x13, [sp, #16 * 6] <<
212 stp x14, x15, [sp, #16 * 7] <<
213 stp x16, x17, [sp, #16 * 8] <<
214 stp x18, x19, [sp, #16 * 9] <<
215 stp x20, x21, [sp, #16 * 10] <<
216 stp x22, x23, [sp, #16 * 11] <<
217 stp x24, x25, [sp, #16 * 12] <<
218 stp x26, x27, [sp, #16 * 13] <<
219 stp x28, x29, [sp, #16 * 14] <<
220 <<
221 .if \el == 0 <<
222 clear_gp_regs <<
223 mrs x21, sp_el0 <<
224 ldr_this_cpu tsk, __entry_task, x20 <<
225 msr sp_el0, tsk <<
226 <<
227 /* <<
228 * Ensure MDSCR_EL1.SS is clear, since <<
229 * when scheduling. <<
230 */ 849 */
231 ldr x19, [tsk, #TSK_TI_FLAGS] !! 850 RESTORE_ALL
232 disable_step_tsk x19, x20 <<
233 851
234 /* Check for asynchronous tag check fa !! 852 .align 4
235 ldr x0, [tsk, THREAD_SCTLR_USER] !! 853 .globl sys_rt_sigreturn
236 check_mte_async_tcf x22, x23, x0 !! 854 sys_rt_sigreturn:
>> 855 call do_rt_sigreturn
>> 856 add %sp, STACKFRAME_SZ, %o0
>> 857
>> 858 ld [%curptr + TI_FLAGS], %l5
>> 859 andcc %l5, _TIF_SYSCALL_TRACE, %g0
>> 860 be 1f
>> 861 nop
>> 862
>> 863 add %sp, STACKFRAME_SZ, %o0
>> 864 call syscall_trace
>> 865 mov 1, %o1
237 866
238 #ifdef CONFIG_ARM64_PTR_AUTH <<
239 alternative_if ARM64_HAS_ADDRESS_AUTH <<
240 /* <<
241 * Enable IA for in-kernel PAC if the <<
242 * this could be implemented with an u <<
243 * a load, this was measured to be slo <<
244 * <<
245 * Install the kernel IA key only if I <<
246 * was disabled on kernel exit then we <<
247 * installed so there is no need to in <<
248 */ <<
249 tbz x0, SCTLR_ELx_ENIA_SHIFT, 1f <<
250 __ptrauth_keys_install_kernel_nosync t <<
251 b 2f <<
252 1: 867 1:
253 mrs x0, sctlr_el1 !! 868 /* We are returning to a signal handler. */
254 orr x0, x0, SCTLR_ELx_ENIA !! 869 RESTORE_ALL
255 msr sctlr_el1, x0 <<
256 2: <<
257 alternative_else_nop_endif <<
258 #endif <<
259 <<
260 apply_ssbd 1, x22, x23 <<
261 <<
262 mte_set_kernel_gcr x22, x23 <<
263 870
264 /* !! 871 /* Now that we have a real sys_clone, sys_fork() is
265 * Any non-self-synchronizing system r !! 872 * implemented in terms of it. Our _real_ implementation
266 * kernel entry should be placed befor !! 873 * of SunOS vfork() will use sys_vfork().
>> 874 *
>> 875 * XXX These three should be consolidated into mostly shared
>> 876 * XXX code just like on sparc64... -DaveM
267 */ 877 */
268 alternative_if ARM64_MTE !! 878 .align 4
269 isb !! 879 .globl sys_fork, flush_patch_two
270 b 1f !! 880 sys_fork:
271 alternative_else_nop_endif !! 881 mov %o7, %l5
272 alternative_if ARM64_HAS_ADDRESS_AUTH !! 882 flush_patch_two:
273 isb !! 883 FLUSH_ALL_KERNEL_WINDOWS;
274 alternative_else_nop_endif !! 884 ld [%curptr + TI_TASK], %o4
>> 885 rd %psr, %g4
>> 886 WRITE_PAUSE
>> 887 mov SIGCHLD, %o0 ! arg0: clone flags
>> 888 rd %wim, %g5
>> 889 WRITE_PAUSE
>> 890 mov %fp, %o1 ! arg1: usp
>> 891 std %g4, [%o4 + AOFF_task_thread + AOFF_thread_fork_kpsr]
>> 892 add %sp, STACKFRAME_SZ, %o2 ! arg2: pt_regs ptr
>> 893 mov 0, %o3
>> 894 call sparc_do_fork
>> 895 mov %l5, %o7
>> 896
>> 897 /* Whee, kernel threads! */
>> 898 .globl sys_clone, flush_patch_three
>> 899 sys_clone:
>> 900 mov %o7, %l5
>> 901 flush_patch_three:
>> 902 FLUSH_ALL_KERNEL_WINDOWS;
>> 903 ld [%curptr + TI_TASK], %o4
>> 904 rd %psr, %g4
>> 905 WRITE_PAUSE
>> 906
>> 907 /* arg0,1: flags,usp -- loaded already */
>> 908 cmp %o1, 0x0 ! Is new_usp NULL?
>> 909 rd %wim, %g5
>> 910 WRITE_PAUSE
>> 911 be,a 1f
>> 912 mov %fp, %o1 ! yes, use callers usp
>> 913 andn %o1, 7, %o1 ! no, align to 8 bytes
275 1: 914 1:
>> 915 std %g4, [%o4 + AOFF_task_thread + AOFF_thread_fork_kpsr]
>> 916 add %sp, STACKFRAME_SZ, %o2 ! arg2: pt_regs ptr
>> 917 mov 0, %o3
>> 918 call sparc_do_fork
>> 919 mov %l5, %o7
>> 920
>> 921 /* Whee, real vfork! */
>> 922 .globl sys_vfork, flush_patch_four
>> 923 sys_vfork:
>> 924 flush_patch_four:
>> 925 FLUSH_ALL_KERNEL_WINDOWS;
>> 926 ld [%curptr + TI_TASK], %o4
>> 927 rd %psr, %g4
>> 928 WRITE_PAUSE
>> 929 rd %wim, %g5
>> 930 WRITE_PAUSE
>> 931 std %g4, [%o4 + AOFF_task_thread + AOFF_thread_fork_kpsr]
>> 932 sethi %hi(0x4000 | 0x0100 | SIGCHLD), %o0
>> 933 mov %fp, %o1
>> 934 or %o0, %lo(0x4000 | 0x0100 | SIGCHLD), %o0
>> 935 sethi %hi(sparc_do_fork), %l1
>> 936 mov 0, %o3
>> 937 jmpl %l1 + %lo(sparc_do_fork), %g0
>> 938 add %sp, STACKFRAME_SZ, %o2
>> 939
>> 940 .align 4
>> 941 linux_sparc_ni_syscall:
>> 942 sethi %hi(sys_ni_syscall), %l7
>> 943 b do_syscall
>> 944 or %l7, %lo(sys_ni_syscall), %l7
>> 945
>> 946 linux_syscall_trace:
>> 947 add %sp, STACKFRAME_SZ, %o0
>> 948 call syscall_trace
>> 949 mov 0, %o1
>> 950 cmp %o0, 0
>> 951 bne 3f
>> 952 mov -ENOSYS, %o0
>> 953
>> 954 /* Syscall tracing can modify the registers. */
>> 955 ld [%sp + STACKFRAME_SZ + PT_G1], %g1
>> 956 sethi %hi(sys_call_table), %l7
>> 957 ld [%sp + STACKFRAME_SZ + PT_I0], %i0
>> 958 or %l7, %lo(sys_call_table), %l7
>> 959 ld [%sp + STACKFRAME_SZ + PT_I1], %i1
>> 960 ld [%sp + STACKFRAME_SZ + PT_I2], %i2
>> 961 ld [%sp + STACKFRAME_SZ + PT_I3], %i3
>> 962 ld [%sp + STACKFRAME_SZ + PT_I4], %i4
>> 963 ld [%sp + STACKFRAME_SZ + PT_I5], %i5
>> 964 cmp %g1, NR_syscalls
>> 965 bgeu 3f
>> 966 mov -ENOSYS, %o0
>> 967
>> 968 sll %g1, 2, %l4
>> 969 mov %i0, %o0
>> 970 ld [%l7 + %l4], %l7
>> 971 mov %i1, %o1
>> 972 mov %i2, %o2
>> 973 mov %i3, %o3
>> 974 b 2f
>> 975 mov %i4, %o4
276 976
277 scs_load_current !! 977 .globl ret_from_fork
278 .else !! 978 ret_from_fork:
279 add x21, sp, #PT_REGS_SIZE !! 979 call schedule_tail
280 get_current_task tsk !! 980 ld [%g3 + TI_TASK], %o0
281 .endif /* \el == 0 */ !! 981 b ret_sys_call
282 mrs x22, elr_el1 !! 982 ld [%sp + STACKFRAME_SZ + PT_I0], %o0
283 mrs x23, spsr_el1 !! 983
284 stp lr, x21, [sp, #S_LR] !! 984 .globl ret_from_kernel_thread
285 !! 985 ret_from_kernel_thread:
286 /* !! 986 call schedule_tail
287 * For exceptions from EL0, create a f !! 987 ld [%g3 + TI_TASK], %o0
288 * For exceptions from EL1, create a s !! 988 ld [%sp + STACKFRAME_SZ + PT_G1], %l0
289 * interrupted code shows up in the ba !! 989 call %l0
290 */ !! 990 ld [%sp + STACKFRAME_SZ + PT_G2], %o0
291 .if \el == 0 !! 991 rd %psr, %l1
292 stp xzr, xzr, [sp, #S_STACKFRAME] !! 992 ld [%sp + STACKFRAME_SZ + PT_PSR], %l0
293 .else !! 993 andn %l0, PSR_CWP, %l0
294 stp x29, x22, [sp, #S_STACKFRAME] !! 994 nop
295 .endif !! 995 and %l1, PSR_CWP, %l1
296 add x29, sp, #S_STACKFRAME !! 996 or %l0, %l1, %l0
297 !! 997 st %l0, [%sp + STACKFRAME_SZ + PT_PSR]
298 #ifdef CONFIG_ARM64_SW_TTBR0_PAN !! 998 b ret_sys_call
299 alternative_if_not ARM64_HAS_PAN !! 999 mov 0, %o0
300 bl __swpan_entry_el\el !! 1000
301 alternative_else_nop_endif !! 1001 /* Linux native system calls enter here... */
302 #endif !! 1002 .align 4
303 !! 1003 .globl linux_sparc_syscall
304 stp x22, x23, [sp, #S_PC] !! 1004 linux_sparc_syscall:
305 !! 1005 sethi %hi(PSR_SYSCALL), %l4
306 /* Not in a syscall by default (el0_sv !! 1006 or %l0, %l4, %l0
307 .if \el == 0 !! 1007 /* Direct access to user regs, must faster. */
308 mov w21, #NO_SYSCALL !! 1008 cmp %g1, NR_syscalls
309 str w21, [sp, #S_SYSCALLNO] !! 1009 bgeu linux_sparc_ni_syscall
310 .endif !! 1010 sll %g1, 2, %l4
311 !! 1011 ld [%l7 + %l4], %l7
312 #ifdef CONFIG_ARM64_PSEUDO_NMI !! 1012
313 alternative_if_not ARM64_HAS_GIC_PRIO_MASKING !! 1013 do_syscall:
314 b .Lskip_pmr_save\@ !! 1014 SAVE_ALL_HEAD
315 alternative_else_nop_endif !! 1015 rd %wim, %l3
316 !! 1016
317 mrs_s x20, SYS_ICC_PMR_EL1 !! 1017 wr %l0, PSR_ET, %psr
318 str x20, [sp, #S_PMR_SAVE] !! 1018 mov %i0, %o0
319 mov x20, #GIC_PRIO_IRQON | GIC_PRI !! 1019 mov %i1, %o1
320 msr_s SYS_ICC_PMR_EL1, x20 !! 1020 mov %i2, %o2
321 !! 1021
322 .Lskip_pmr_save\@: !! 1022 ld [%curptr + TI_FLAGS], %l5
323 #endif !! 1023 mov %i3, %o3
324 !! 1024 andcc %l5, _TIF_SYSCALL_TRACE, %g0
325 /* !! 1025 mov %i4, %o4
326 * Registers that may be useful after !! 1026 bne linux_syscall_trace
327 * !! 1027 mov %i0, %l5
328 * x20 - ICC_PMR_EL1 !! 1028 2:
329 * x21 - aborted SP !! 1029 call %l7
330 * x22 - aborted PC !! 1030 mov %i5, %o5
331 * x23 - aborted PSTATE <<
332 */ <<
333 .endm <<
334 <<
335 .macro kernel_exit, el <<
336 .if \el != 0 <<
337 disable_daif <<
338 .endif <<
339 <<
340 #ifdef CONFIG_ARM64_PSEUDO_NMI <<
341 alternative_if_not ARM64_HAS_GIC_PRIO_MASKING <<
342 b .Lskip_pmr_restore\@ <<
343 alternative_else_nop_endif <<
344 <<
345 ldr x20, [sp, #S_PMR_SAVE] <<
346 msr_s SYS_ICC_PMR_EL1, x20 <<
347 <<
348 /* Ensure priority change is seen by r <<
349 alternative_if_not ARM64_HAS_GIC_PRIO_RELAXED_ <<
350 dsb sy <<
351 alternative_else_nop_endif <<
352 <<
353 .Lskip_pmr_restore\@: <<
354 #endif <<
355 <<
356 ldp x21, x22, [sp, #S_PC] <<
357 <<
358 #ifdef CONFIG_ARM64_SW_TTBR0_PAN <<
359 alternative_if_not ARM64_HAS_PAN <<
360 bl __swpan_exit_el\el <<
361 alternative_else_nop_endif <<
362 #endif <<
363 1031
364 .if \el == 0 <<
365 ldr x23, [sp, #S_SP] <<
366 msr sp_el0, x23 <<
367 tst x22, #PSR_MODE32_BIT <<
368 b.eq 3f <<
369 <<
370 #ifdef CONFIG_ARM64_ERRATUM_845719 <<
371 alternative_if ARM64_WORKAROUND_845719 <<
372 #ifdef CONFIG_PID_IN_CONTEXTIDR <<
373 mrs x29, contextidr_el1 <<
374 msr contextidr_el1, x29 <<
375 #else <<
376 msr contextidr_el1, xzr <<
377 #endif <<
378 alternative_else_nop_endif <<
379 #endif <<
380 3: 1032 3:
381 scs_save tsk !! 1033 st %o0, [%sp + STACKFRAME_SZ + PT_I0]
382 <<
383 /* Ignore asynchronous tag check fault <<
384 ldr x0, [tsk, THREAD_SCTLR_USER] <<
385 clear_mte_async_tcf x0 <<
386 1034
387 #ifdef CONFIG_ARM64_PTR_AUTH !! 1035 ret_sys_call:
388 alternative_if ARM64_HAS_ADDRESS_AUTH !! 1036 ld [%curptr + TI_FLAGS], %l6
389 /* !! 1037 cmp %o0, -ERESTART_RESTARTBLOCK
390 * IA was enabled for in-kernel PAC. D !! 1038 ld [%sp + STACKFRAME_SZ + PT_PSR], %g3
391 * alternatively install the user's IA !! 1039 set PSR_C, %g2
392 * SCTLR bits were updated on task swi !! 1040 bgeu 1f
393 * !! 1041 andcc %l6, _TIF_SYSCALL_TRACE, %g0
394 * No kernel C function calls after th !! 1042
395 */ !! 1043 /* System call success, clear Carry condition code. */
396 tbz x0, SCTLR_ELx_ENIA_SHIFT, 1f !! 1044 andn %g3, %g2, %g3
397 __ptrauth_keys_install_user tsk, x0, x !! 1045 clr %l6
398 b 2f !! 1046 st %g3, [%sp + STACKFRAME_SZ + PT_PSR]
>> 1047 bne linux_syscall_trace2
>> 1048 ld [%sp + STACKFRAME_SZ + PT_NPC], %l1 /* pc = npc */
>> 1049 add %l1, 0x4, %l2 /* npc = npc+4 */
>> 1050 st %l1, [%sp + STACKFRAME_SZ + PT_PC]
>> 1051 b ret_trap_entry
>> 1052 st %l2, [%sp + STACKFRAME_SZ + PT_NPC]
399 1: 1053 1:
400 mrs x0, sctlr_el1 !! 1054 /* System call failure, set Carry condition code.
401 bic x0, x0, SCTLR_ELx_ENIA !! 1055 * Also, get abs(errno) to return to the process.
402 msr sctlr_el1, x0 <<
403 2: <<
404 alternative_else_nop_endif <<
405 #endif <<
406 <<
407 mte_set_user_gcr tsk, x0, x1 <<
408 <<
409 apply_ssbd 0, x0, x1 <<
410 .endif <<
411 <<
412 msr elr_el1, x21 <<
413 msr spsr_el1, x22 <<
414 ldp x0, x1, [sp, #16 * 0] <<
415 ldp x2, x3, [sp, #16 * 1] <<
416 ldp x4, x5, [sp, #16 * 2] <<
417 ldp x6, x7, [sp, #16 * 3] <<
418 ldp x8, x9, [sp, #16 * 4] <<
419 ldp x10, x11, [sp, #16 * 5] <<
420 ldp x12, x13, [sp, #16 * 6] <<
421 ldp x14, x15, [sp, #16 * 7] <<
422 ldp x16, x17, [sp, #16 * 8] <<
423 ldp x18, x19, [sp, #16 * 9] <<
424 ldp x20, x21, [sp, #16 * 10] <<
425 ldp x22, x23, [sp, #16 * 11] <<
426 ldp x24, x25, [sp, #16 * 12] <<
427 ldp x26, x27, [sp, #16 * 13] <<
428 ldp x28, x29, [sp, #16 * 14] <<
429 <<
430 .if \el == 0 <<
431 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 <<
432 alternative_insn "b .L_skip_tramp_exit <<
433 <<
434 msr far_el1, x29 <<
435 <<
436 ldr_this_cpu x30, this_cpu_vector, <<
437 tramp_alias x29, tramp_exit <<
438 msr vbar_el1, x30 <<
439 ldr lr, [sp, #S_LR] <<
440 add sp, sp, #PT_REGS_SIZE <<
441 br x29 <<
442 <<
443 .L_skip_tramp_exit_\@: <<
444 #endif <<
445 .endif <<
446 <<
447 ldr lr, [sp, #S_LR] <<
448 add sp, sp, #PT_REGS_SIZE <<
449 <<
450 .if \el == 0 <<
451 /* This must be after the last explici <<
452 alternative_if ARM64_WORKAROUND_SPECULATIVE_UN <<
453 tlbi vale1, xzr <<
454 dsb nsh <<
455 alternative_else_nop_endif <<
456 .else <<
457 /* Ensure any device/NC reads complete <<
458 alternative_insn nop, "dmb sy", ARM64_ <<
459 .endif <<
460 <<
461 eret <<
462 sb <<
463 .endm <<
464 <<
465 #ifdef CONFIG_ARM64_SW_TTBR0_PAN <<
466 /* <<
467 * Set the TTBR0 PAN bit in SPSR. When <<
468 * EL0, there is no need to check the <<
469 * accesses are always enabled. <<
470 * Note that the meaning of this bit d <<
471 * feature as all TTBR0_EL1 accesses a <<
472 * user mappings. <<
473 */ <<
474 SYM_CODE_START_LOCAL(__swpan_entry_el1) <<
475 mrs x21, ttbr0_el1 <<
476 tst x21, #TTBR_ASID_MASK <<
477 orr x23, x23, #PSR_PAN_BIT <<
478 b.eq 1f <<
479 and x23, x23, #~PSR_PAN_BIT <<
480 SYM_INNER_LABEL(__swpan_entry_el0, SYM_L_LOCAL <<
481 __uaccess_ttbr0_disable x21 <<
482 1: ret <<
483 SYM_CODE_END(__swpan_entry_el1) <<
484 <<
485 /* <<
486 * Restore access to TTBR0_EL1. If ret <<
487 * PAN bit checking. <<
488 */ <<
489 SYM_CODE_START_LOCAL(__swpan_exit_el1) <<
490 tbnz x22, #22, 1f <<
491 __uaccess_ttbr0_enable x0, x1 <<
492 1: and x22, x22, #~PSR_PAN_BIT <<
493 ret <<
494 SYM_CODE_END(__swpan_exit_el1) <<
495 <<
496 SYM_CODE_START_LOCAL(__swpan_exit_el0) <<
497 __uaccess_ttbr0_enable x0, x1 <<
498 /* <<
499 * Enable errata workarounds only if r <<
500 * workaround currently required for T <<
501 * Cavium erratum 27456 (broadcast TLB <<
502 * corruption). <<
503 */ 1056 */
504 b post_ttbr_update_workaround !! 1057 sub %g0, %o0, %o0
505 SYM_CODE_END(__swpan_exit_el0) !! 1058 or %g3, %g2, %g3
506 #endif !! 1059 st %o0, [%sp + STACKFRAME_SZ + PT_I0]
507 !! 1060 mov 1, %l6
508 /* GPRs used by entry code */ !! 1061 st %g3, [%sp + STACKFRAME_SZ + PT_PSR]
509 tsk .req x28 // current thr !! 1062 bne linux_syscall_trace2
510 !! 1063 ld [%sp + STACKFRAME_SZ + PT_NPC], %l1 /* pc = npc */
511 .text !! 1064 add %l1, 0x4, %l2 /* npc = npc+4 */
>> 1065 st %l1, [%sp + STACKFRAME_SZ + PT_PC]
>> 1066 b ret_trap_entry
>> 1067 st %l2, [%sp + STACKFRAME_SZ + PT_NPC]
>> 1068
>> 1069 linux_syscall_trace2:
>> 1070 add %sp, STACKFRAME_SZ, %o0
>> 1071 mov 1, %o1
>> 1072 call syscall_trace
>> 1073 add %l1, 0x4, %l2 /* npc = npc+4 */
>> 1074 st %l1, [%sp + STACKFRAME_SZ + PT_PC]
>> 1075 b ret_trap_entry
>> 1076 st %l2, [%sp + STACKFRAME_SZ + PT_NPC]
512 1077
513 /* <<
514 * Exception vectors. <<
515 */ <<
516 .pushsection ".entry.text", "ax" <<
517 <<
518 .align 11 <<
519 SYM_CODE_START(vectors) <<
520 kernel_ventry 1, t, 64, sync <<
521 kernel_ventry 1, t, 64, irq <<
522 kernel_ventry 1, t, 64, fiq <<
523 kernel_ventry 1, t, 64, error <<
524 <<
525 kernel_ventry 1, h, 64, sync <<
526 kernel_ventry 1, h, 64, irq <<
527 kernel_ventry 1, h, 64, fiq <<
528 kernel_ventry 1, h, 64, error <<
529 <<
530 kernel_ventry 0, t, 64, sync <<
531 kernel_ventry 0, t, 64, irq <<
532 kernel_ventry 0, t, 64, fiq <<
533 kernel_ventry 0, t, 64, error <<
534 <<
535 kernel_ventry 0, t, 32, sync <<
536 kernel_ventry 0, t, 32, irq <<
537 kernel_ventry 0, t, 32, fiq <<
538 kernel_ventry 0, t, 32, error <<
539 SYM_CODE_END(vectors) <<
540 <<
541 #ifdef CONFIG_VMAP_STACK <<
542 SYM_CODE_START_LOCAL(__bad_stack) <<
543 /* <<
544 * We detected an overflow in kernel_v <<
545 * overflow stack. Stash the exception <<
546 * handler. <<
547 */ <<
548 1078
549 /* Restore the original x0 value */ !! 1079 /* Saving and restoring the FPU state is best done from lowlevel code.
550 mrs x0, tpidrro_el0 !! 1080 *
551 !! 1081 * void fpsave(unsigned long *fpregs, unsigned long *fsr,
552 /* !! 1082 * void *fpqueue, unsigned long *fpqdepth)
553 * Store the original GPRs to the new <<
554 * PT_REGS_SIZE) was stashed in tpidr_ <<
555 */ <<
556 sub sp, sp, #PT_REGS_SIZE <<
557 kernel_entry 1 <<
558 mrs x0, tpidr_el0 <<
559 add x0, x0, #PT_REGS_SIZE <<
560 str x0, [sp, #S_SP] <<
561 <<
562 /* Stash the regs for handle_bad_stack <<
563 mov x0, sp <<
564 <<
565 /* Time to die */ <<
566 bl handle_bad_stack <<
567 ASM_BUG() <<
568 SYM_CODE_END(__bad_stack) <<
569 #endif /* CONFIG_VMAP_STACK */ <<
570 <<
571 <<
572 .macro entry_handler el:req, ht:req, r <<
573 SYM_CODE_START_LOCAL(el\el\ht\()_\regsize\()_\ <<
574 kernel_entry \el, \regsize <<
575 mov x0, sp <<
576 bl el\el\ht\()_\regsize\()_\label <<
577 .if \el == 0 <<
578 b ret_to_user <<
579 .else <<
580 b ret_to_kernel <<
581 .endif <<
582 SYM_CODE_END(el\el\ht\()_\regsize\()_\label) <<
583 .endm <<
584 <<
585 /* <<
586 * Early exception handlers <<
587 */ 1083 */
588 entry_handler 1, t, 64, sync <<
589 entry_handler 1, t, 64, irq <<
590 entry_handler 1, t, 64, fiq <<
591 entry_handler 1, t, 64, error <<
592 <<
593 entry_handler 1, h, 64, sync <<
594 entry_handler 1, h, 64, irq <<
595 entry_handler 1, h, 64, fiq <<
596 entry_handler 1, h, 64, error <<
597 <<
598 entry_handler 0, t, 64, sync <<
599 entry_handler 0, t, 64, irq <<
600 entry_handler 0, t, 64, fiq <<
601 entry_handler 0, t, 64, error <<
602 <<
603 entry_handler 0, t, 32, sync <<
604 entry_handler 0, t, 32, irq <<
605 entry_handler 0, t, 32, fiq <<
606 entry_handler 0, t, 32, error <<
607 <<
608 SYM_CODE_START_LOCAL(ret_to_kernel) <<
609 kernel_exit 1 <<
610 SYM_CODE_END(ret_to_kernel) <<
611 <<
612 SYM_CODE_START_LOCAL(ret_to_user) <<
613 ldr x19, [tsk, #TSK_TI_FLAGS] <<
614 enable_step_tsk x19, x2 <<
615 #ifdef CONFIG_GCC_PLUGIN_STACKLEAK <<
616 bl stackleak_erase_on_task_stack <<
617 #endif <<
618 kernel_exit 0 <<
619 SYM_CODE_END(ret_to_user) <<
620 1084
621 .popsection !! 1085 .globl fpsave
>> 1086 fpsave:
>> 1087 st %fsr, [%o1] ! this can trap on us if fpu is in bogon state
>> 1088 ld [%o1], %g1
>> 1089 set 0x2000, %g4
>> 1090 andcc %g1, %g4, %g0
>> 1091 be 2f
>> 1092 mov 0, %g2
622 1093
623 // Move from tramp_pg_dir to swapper_p !! 1094 /* We have an fpqueue to save. */
624 .macro tramp_map_kernel, tmp <<
625 mrs \tmp, ttbr1_el1 <<
626 add \tmp, \tmp, #TRAMP_SWAPPER_OFF <<
627 bic \tmp, \tmp, #USER_ASID_FLAG <<
628 msr ttbr1_el1, \tmp <<
629 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003 <<
630 alternative_if ARM64_WORKAROUND_QCOM_FALKOR_E1 <<
631 /* ASID already in \tmp[63:48] */ <<
632 movk \tmp, #:abs_g2_nc:(TRAMP_VALIA <<
633 movk \tmp, #:abs_g1_nc:(TRAMP_VALIA <<
634 /* 2MB boundary containing the vectors <<
635 movk \tmp, #:abs_g0_nc:((TRAMP_VALI <<
636 isb <<
637 tlbi vae1, \tmp <<
638 dsb nsh <<
639 alternative_else_nop_endif <<
640 #endif /* CONFIG_QCOM_FALKOR_ERRATUM_1003 */ <<
641 .endm <<
642 <<
643 // Move from swapper_pg_dir to tramp_p <<
644 .macro tramp_unmap_kernel, tmp <<
645 mrs \tmp, ttbr1_el1 <<
646 sub \tmp, \tmp, #TRAMP_SWAPPER_OFF <<
647 orr \tmp, \tmp, #USER_ASID_FLAG <<
648 msr ttbr1_el1, \tmp <<
649 /* <<
650 * We avoid running the post_ttbr_upda <<
651 * it's only needed by Cavium ThunderX <<
652 * disabled. <<
653 */ <<
654 .endm <<
655 <<
656 .macro tramp_data_read_var <<
657 #ifdef CONFIG_RELOCATABLE <<
658 ldr \dst, .L__tramp_data_\ <<
659 .ifndef .L__tramp_data_\var <<
660 .pushsection ".entry.tramp.rodata", <<
661 .align 3 <<
662 .L__tramp_data_\var: <<
663 .quad \var <<
664 .popsection <<
665 .endif <<
666 #else <<
667 /* <<
668 * As !RELOCATABLE implies !RANDOMIZE_ <<
669 * compile time constant (and hence no <<
670 * <<
671 * As statically allocated kernel code <<
672 * 47 bits of the address space we can <<
673 * instruction to load the upper 16 bi <<
674 */ <<
675 movz \dst, :abs_g2_s:\var <<
676 movk \dst, :abs_g1_nc:\var <<
677 movk \dst, :abs_g0_nc:\var <<
678 #endif <<
679 .endm <<
680 <<
681 #define BHB_MITIGATION_NONE 0 <<
682 #define BHB_MITIGATION_LOOP 1 <<
683 #define BHB_MITIGATION_FW 2 <<
684 #define BHB_MITIGATION_INSN 3 <<
685 <<
686 .macro tramp_ventry, vector_start, reg <<
687 .align 7 <<
688 1: 1095 1:
689 .if \regsize == 64 !! 1096 std %fq, [%o2]
690 msr tpidrro_el0, x30 // Res !! 1097 fpsave_magic:
691 .endif !! 1098 st %fsr, [%o1]
>> 1099 ld [%o1], %g3
>> 1100 andcc %g3, %g4, %g0
>> 1101 add %g2, 1, %g2
>> 1102 bne 1b
>> 1103 add %o2, 8, %o2
692 1104
693 .if \bhb == BHB_MITIGATION_LOOP <<
694 /* <<
695 * This sequence must appear before th <<
696 * ret out of tramp_ventry. It appears <<
697 */ <<
698 __mitigate_spectre_bhb_loop x30 <<
699 .endif // \bhb == BHB_MITIGATION_LOOP <<
700 <<
701 .if \bhb == BHB_MITIGATION_INSN <<
702 clearbhb <<
703 isb <<
704 .endif // \bhb == BHB_MITIGATION_INSN <<
705 <<
706 .if \kpti == 1 <<
707 /* <<
708 * Defend against branch aliasing atta <<
709 * entry onto the return stack and usi <<
710 * enter the full-fat kernel vectors. <<
711 */ <<
712 bl 2f <<
713 b . <<
714 2: 1105 2:
715 tramp_map_kernel x30 !! 1106 st %g2, [%o3]
716 alternative_insn isb, nop, ARM64_WORKAROUND_QC <<
717 tramp_data_read_var x30, vectors <<
718 alternative_if_not ARM64_WORKAROUND_CAVIUM_TX2 <<
719 prfm plil1strm, [x30, #(1b - \vecto <<
720 alternative_else_nop_endif <<
721 <<
722 msr vbar_el1, x30 <<
723 isb <<
724 .else <<
725 adr_l x30, vectors <<
726 .endif // \kpti == 1 <<
727 1107
728 .if \bhb == BHB_MITIGATION_FW !! 1108 std %f0, [%o0 + 0x00]
729 /* !! 1109 std %f2, [%o0 + 0x08]
730 * The firmware sequence must appear b !! 1110 std %f4, [%o0 + 0x10]
731 * i.e. the ret out of tramp_ventry. B !! 1111 std %f6, [%o0 + 0x18]
732 * mapped to save/restore the register !! 1112 std %f8, [%o0 + 0x20]
>> 1113 std %f10, [%o0 + 0x28]
>> 1114 std %f12, [%o0 + 0x30]
>> 1115 std %f14, [%o0 + 0x38]
>> 1116 std %f16, [%o0 + 0x40]
>> 1117 std %f18, [%o0 + 0x48]
>> 1118 std %f20, [%o0 + 0x50]
>> 1119 std %f22, [%o0 + 0x58]
>> 1120 std %f24, [%o0 + 0x60]
>> 1121 std %f26, [%o0 + 0x68]
>> 1122 std %f28, [%o0 + 0x70]
>> 1123 retl
>> 1124 std %f30, [%o0 + 0x78]
>> 1125
>> 1126 /* Thanks for Theo Deraadt and the authors of the Sprite/netbsd/openbsd
>> 1127 * code for pointing out this possible deadlock, while we save state
>> 1128 * above we could trap on the fsr store so our low level fpu trap
>> 1129 * code has to know how to deal with this.
>> 1130 */
>> 1131 fpsave_catch:
>> 1132 b fpsave_magic + 4
>> 1133 st %fsr, [%o1]
>> 1134
>> 1135 fpsave_catch2:
>> 1136 b fpsave + 4
>> 1137 st %fsr, [%o1]
>> 1138
>> 1139 /* void fpload(unsigned long *fpregs, unsigned long *fsr); */
>> 1140
>> 1141 .globl fpload
>> 1142 fpload:
>> 1143 ldd [%o0 + 0x00], %f0
>> 1144 ldd [%o0 + 0x08], %f2
>> 1145 ldd [%o0 + 0x10], %f4
>> 1146 ldd [%o0 + 0x18], %f6
>> 1147 ldd [%o0 + 0x20], %f8
>> 1148 ldd [%o0 + 0x28], %f10
>> 1149 ldd [%o0 + 0x30], %f12
>> 1150 ldd [%o0 + 0x38], %f14
>> 1151 ldd [%o0 + 0x40], %f16
>> 1152 ldd [%o0 + 0x48], %f18
>> 1153 ldd [%o0 + 0x50], %f20
>> 1154 ldd [%o0 + 0x58], %f22
>> 1155 ldd [%o0 + 0x60], %f24
>> 1156 ldd [%o0 + 0x68], %f26
>> 1157 ldd [%o0 + 0x70], %f28
>> 1158 ldd [%o0 + 0x78], %f30
>> 1159 ld [%o1], %fsr
>> 1160 retl
>> 1161 nop
>> 1162
>> 1163 /* __ndelay and __udelay take two arguments:
>> 1164 * 0 - nsecs or usecs to delay
>> 1165 * 1 - per_cpu udelay_val (loops per jiffy)
>> 1166 *
>> 1167 * Note that ndelay gives HZ times higher resolution but has a 10ms
>> 1168 * limit. udelay can handle up to 1s.
733 */ 1169 */
734 __mitigate_spectre_bhb_fw !! 1170 .globl __ndelay
735 .endif // \bhb == BHB_MITIGATION_FW !! 1171 __ndelay:
736 !! 1172 save %sp, -STACKFRAME_SZ, %sp
737 add x30, x30, #(1b - \vector_start !! 1173 mov %i0, %o0 ! round multiplier up so large ns ok
738 ret !! 1174 mov 0x1ae, %o1 ! 2**32 / (1 000 000 000 / HZ)
739 .org 1b + 128 // Did we overflow the ventry !! 1175 umul %o0, %o1, %o0
740 .endm !! 1176 rd %y, %o1
741 !! 1177 mov %i1, %o1 ! udelay_val
742 .macro generate_tramp_vector, kpti, !! 1178 umul %o0, %o1, %o0
743 .Lvector_start\@: !! 1179 rd %y, %o1
744 .space 0x400 !! 1180 ba delay_continue
745 !! 1181 mov %o1, %o0 ! >>32 later for better resolution
746 .rept 4 !! 1182
747 tramp_ventry .Lvector_start\@, 64, !! 1183 .globl __udelay
748 .endr !! 1184 __udelay:
749 .rept 4 !! 1185 save %sp, -STACKFRAME_SZ, %sp
750 tramp_ventry .Lvector_start\@, 32, !! 1186 mov %i0, %o0
751 .endr !! 1187 sethi %hi(0x10c7), %o1 ! round multiplier up so large us ok
752 .endm !! 1188 or %o1, %lo(0x10c7), %o1 ! 2**32 / 1 000 000
753 !! 1189 umul %o0, %o1, %o0
754 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 !! 1190 rd %y, %o1
755 /* !! 1191 mov %i1, %o1 ! udelay_val
756 * Exception vectors trampoline. !! 1192 umul %o0, %o1, %o0
757 * The order must match __bp_harden_el1_vector !! 1193 rd %y, %o1
758 * arm64_bp_harden_el1_vectors enum. !! 1194 sethi %hi(0x028f4b62), %l0 ! Add in rounding constant * 2**32,
759 */ !! 1195 or %g0, %lo(0x028f4b62), %l0
760 .pushsection ".entry.tramp.text", "ax" !! 1196 addcc %o0, %l0, %o0 ! 2**32 * 0.009 999
761 .align 11 !! 1197 bcs,a 3f
762 SYM_CODE_START_LOCAL_NOALIGN(tramp_vectors) !! 1198 add %o1, 0x01, %o1
763 #ifdef CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY !! 1199 3:
764 generate_tramp_vector kpti=1, bhb=BH !! 1200 mov HZ, %o0 ! >>32 earlier for wider range
765 generate_tramp_vector kpti=1, bhb=BH !! 1201 umul %o0, %o1, %o0
766 generate_tramp_vector kpti=1, bhb=BH !! 1202 rd %y, %o1
767 #endif /* CONFIG_MITIGATE_SPECTRE_BRANCH_HISTO <<
768 generate_tramp_vector kpti=1, bhb=BH <<
769 SYM_CODE_END(tramp_vectors) <<
770 <<
771 SYM_CODE_START_LOCAL(tramp_exit) <<
772 tramp_unmap_kernel x29 <<
773 mrs x29, far_el1 <<
774 eret <<
775 sb <<
776 SYM_CODE_END(tramp_exit) <<
777 .popsection <<
778 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ <<
779 <<
780 /* <<
781 * Exception vectors for spectre mitigations o <<
782 * kpti is not in use. <<
783 */ <<
784 .macro generate_el1_vector, bhb <<
785 .Lvector_start\@: <<
786 kernel_ventry 1, t, 64, sync <<
787 kernel_ventry 1, t, 64, irq <<
788 kernel_ventry 1, t, 64, fiq <<
789 kernel_ventry 1, t, 64, error <<
790 <<
791 kernel_ventry 1, h, 64, sync <<
792 kernel_ventry 1, h, 64, irq <<
793 kernel_ventry 1, h, 64, fiq <<
794 kernel_ventry 1, h, 64, error <<
795 <<
796 .rept 4 <<
797 tramp_ventry .Lvector_start\@, 64, <<
798 .endr <<
799 .rept 4 <<
800 tramp_ventry .Lvector_start\@, 32, <<
801 .endr <<
802 .endm <<
803 <<
804 /* The order must match tramp_vecs and the arm <<
805 .pushsection ".entry.text", "ax" <<
806 .align 11 <<
807 SYM_CODE_START(__bp_harden_el1_vectors) <<
808 #ifdef CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY <<
809 generate_el1_vector bhb=BHB_MITIGA <<
810 generate_el1_vector bhb=BHB_MITIGA <<
811 generate_el1_vector bhb=BHB_MITIGA <<
812 #endif /* CONFIG_MITIGATE_SPECTRE_BRANCH_HISTO <<
813 SYM_CODE_END(__bp_harden_el1_vectors) <<
814 .popsection <<
815 <<
816 <<
817 /* <<
818 * Register switch for AArch64. The callee-sav <<
819 * and restored. On entry: <<
820 * x0 = previous task_struct (must be preser <<
821 * x1 = next task_struct <<
822 * Previous and next are guaranteed not to be <<
823 * <<
824 */ <<
825 SYM_FUNC_START(cpu_switch_to) <<
826 mov x10, #THREAD_CPU_CONTEXT <<
827 add x8, x0, x10 <<
828 mov x9, sp <<
829 stp x19, x20, [x8], #16 <<
830 stp x21, x22, [x8], #16 <<
831 stp x23, x24, [x8], #16 <<
832 stp x25, x26, [x8], #16 <<
833 stp x27, x28, [x8], #16 <<
834 stp x29, x9, [x8], #16 <<
835 str lr, [x8] <<
836 add x8, x1, x10 <<
837 ldp x19, x20, [x8], #16 <<
838 ldp x21, x22, [x8], #16 <<
839 ldp x23, x24, [x8], #16 <<
840 ldp x25, x26, [x8], #16 <<
841 ldp x27, x28, [x8], #16 <<
842 ldp x29, x9, [x8], #16 <<
843 ldr lr, [x8] <<
844 mov sp, x9 <<
845 msr sp_el0, x1 <<
846 ptrauth_keys_install_kernel x1, x8, x9 <<
847 scs_save x0 <<
848 scs_load_current <<
849 ret <<
850 SYM_FUNC_END(cpu_switch_to) <<
851 NOKPROBE(cpu_switch_to) <<
852 <<
853 /* <<
854 * This is how we return from a fork. <<
855 */ <<
856 SYM_CODE_START(ret_from_fork) <<
857 bl schedule_tail <<
858 cbz x19, 1f <<
859 mov x0, x20 <<
860 blr x19 <<
861 1: get_current_task tsk <<
862 mov x0, sp <<
863 bl asm_exit_to_user_mode <<
864 b ret_to_user <<
865 SYM_CODE_END(ret_from_fork) <<
866 NOKPROBE(ret_from_fork) <<
867 <<
868 /* <<
869 * void call_on_irq_stack(struct pt_regs *regs <<
870 * void (*func)(struct <<
871 * <<
872 * Calls func(regs) using this CPU's irq stack <<
873 */ <<
874 SYM_FUNC_START(call_on_irq_stack) <<
875 #ifdef CONFIG_SHADOW_CALL_STACK <<
876 get_current_task x16 <<
877 scs_save x16 <<
878 ldr_this_cpu scs_sp, irq_shadow_call_s <<
879 #endif <<
880 <<
881 /* Create a frame record to save our L <<
882 stp x29, x30, [sp, #-16]! <<
883 mov x29, sp <<
884 <<
885 ldr_this_cpu x16, irq_stack_ptr, x17 <<
886 <<
887 /* Move to the new stack and call the <<
888 add sp, x16, #IRQ_STACK_SIZE <<
889 blr x1 <<
890 1203
891 /* !! 1204 delay_continue:
892 * Restore the SP from the FP, and res !! 1205 cmp %o0, 0x0
893 * record. !! 1206 1:
894 */ !! 1207 bne 1b
895 mov sp, x29 !! 1208 subcc %o0, 1, %o0
896 ldp x29, x30, [sp], #16 !! 1209
897 scs_load_current <<
898 ret 1210 ret
899 SYM_FUNC_END(call_on_irq_stack) !! 1211 restore
900 NOKPROBE(call_on_irq_stack) !! 1212 EXPORT_SYMBOL(__udelay)
901 !! 1213 EXPORT_SYMBOL(__ndelay)
902 #ifdef CONFIG_ARM_SDE_INTERFACE !! 1214
903 !! 1215 /* Handle a software breakpoint */
904 #include <asm/sdei.h> !! 1216 /* We have to inform parent that child has stopped */
905 #include <uapi/linux/arm_sdei.h> !! 1217 .align 4
906 !! 1218 .globl breakpoint_trap
907 .macro sdei_handler_exit exit_mode !! 1219 breakpoint_trap:
908 /* On success, this call never returns !! 1220 rd %wim,%l3
909 cmp \exit_mode, #SDEI_EXIT_SMC !! 1221 SAVE_ALL
910 b.ne 99f !! 1222 wr %l0, PSR_ET, %psr
911 smc #0 !! 1223 WRITE_PAUSE
912 b . !! 1224
913 99: hvc #0 !! 1225 st %i0, [%sp + STACKFRAME_SZ + PT_G0] ! for restarting syscalls
914 b . !! 1226 call sparc_breakpoint
915 .endm !! 1227 add %sp, STACKFRAME_SZ, %o0
916 !! 1228
917 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 !! 1229 RESTORE_ALL
918 /* !! 1230
919 * The regular SDEI entry point may have been !! 1231 #ifdef CONFIG_KGDB
920 * the kernel. This trampoline restores the ke !! 1232 ENTRY(kgdb_trap_low)
921 * argument accessible. !! 1233 rd %wim,%l3
922 * !! 1234 SAVE_ALL
923 * This clobbers x4, __sdei_handler() will res !! 1235 wr %l0, PSR_ET, %psr
924 * copy. !! 1236 WRITE_PAUSE
925 */ !! 1237
926 .pushsection ".entry.tramp.text", "ax" !! 1238 mov %l7, %o0 ! trap_level
927 SYM_CODE_START(__sdei_asm_entry_trampoline) !! 1239 call kgdb_trap
928 mrs x4, ttbr1_el1 !! 1240 add %sp, STACKFRAME_SZ, %o1 ! struct pt_regs *regs
929 tbz x4, #USER_ASID_BIT, 1f !! 1241
930 !! 1242 RESTORE_ALL
931 tramp_map_kernel tmp=x4 !! 1243 ENDPROC(kgdb_trap_low)
932 isb !! 1244 #endif
933 mov x4, xzr !! 1245
934 !! 1246 .align 4
935 /* !! 1247 .globl flush_patch_exception
936 * Remember whether to unmap the kerne !! 1248 flush_patch_exception:
937 */ !! 1249 FLUSH_ALL_KERNEL_WINDOWS;
938 1: str x4, [x1, #(SDEI_EVENT_INTREGS !! 1250 ldd [%o0], %o6
939 tramp_data_read_var x4, __sdei_asm !! 1251 jmpl %o7 + 0xc, %g0 ! see asm-sparc/processor.h
940 br x4 !! 1252 mov 1, %g1 ! signal EFAULT condition
941 SYM_CODE_END(__sdei_asm_entry_trampoline) !! 1253
942 NOKPROBE(__sdei_asm_entry_trampoline) !! 1254 .align 4
943 !! 1255 .globl kill_user_windows, kuw_patch1_7win
944 /* !! 1256 .globl kuw_patch1
945 * Make the exit call and restore the original !! 1257 kuw_patch1_7win: sll %o3, 6, %o3
946 * !! 1258
947 * x0 & x1: setup for the exit API call !! 1259 /* No matter how much overhead this routine has in the worst
948 * x2: exit_mode !! 1260 * case scenario, it is several times better than taking the
949 * x4: struct sdei_registered_event argument f !! 1261 * traps with the old method of just doing flush_user_windows().
950 */ !! 1262 */
951 SYM_CODE_START(__sdei_asm_exit_trampoline) !! 1263 kill_user_windows:
952 ldr x4, [x4, #(SDEI_EVENT_INTREGS !! 1264 ld [%g6 + TI_UWINMASK], %o0 ! get current umask
953 cbnz x4, 1f !! 1265 orcc %g0, %o0, %g0 ! if no bits set, we are done
954 !! 1266 be 3f ! nothing to do
955 tramp_unmap_kernel tmp=x4 !! 1267 rd %psr, %o5 ! must clear interrupts
956 !! 1268 or %o5, PSR_PIL, %o4 ! or else that could change
957 1: sdei_handler_exit exit_mode=x2 !! 1269 wr %o4, 0x0, %psr ! the uwinmask state
958 SYM_CODE_END(__sdei_asm_exit_trampoline) !! 1270 WRITE_PAUSE ! burn them cycles
959 NOKPROBE(__sdei_asm_exit_trampoline) !! 1271 1:
960 .popsection // .entry.tramp.text !! 1272 ld [%g6 + TI_UWINMASK], %o0 ! get consistent state
961 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ !! 1273 orcc %g0, %o0, %g0 ! did an interrupt come in?
962 !! 1274 be 4f ! yep, we are done
963 /* !! 1275 rd %wim, %o3 ! get current wim
964 * Software Delegated Exception entry point. !! 1276 srl %o3, 1, %o4 ! simulate a save
965 * !! 1277 kuw_patch1:
966 * x0: Event number !! 1278 sll %o3, 7, %o3 ! compute next wim
967 * x1: struct sdei_registered_event argument f !! 1279 or %o4, %o3, %o3 ! result
968 * x2: interrupted PC !! 1280 andncc %o0, %o3, %o0 ! clean this bit in umask
969 * x3: interrupted PSTATE !! 1281 bne kuw_patch1 ! not done yet
970 * x4: maybe clobbered by the trampoline !! 1282 srl %o3, 1, %o4 ! begin another save simulation
971 * !! 1283 wr %o3, 0x0, %wim ! set the new wim
972 * Firmware has preserved x0->x17 for us, we m !! 1284 st %g0, [%g6 + TI_UWINMASK] ! clear uwinmask
973 * follow SMC-CC. We save (or retrieve) all th !! 1285 4:
974 * want them. !! 1286 wr %o5, 0x0, %psr ! re-enable interrupts
975 */ !! 1287 WRITE_PAUSE ! burn baby burn
976 SYM_CODE_START(__sdei_asm_handler) !! 1288 3:
977 stp x2, x3, [x1, #SDEI_EVENT_INTRE !! 1289 retl ! return
978 stp x4, x5, [x1, #SDEI_EVENT_INTRE !! 1290 st %g0, [%g6 + TI_W_SAVED] ! no windows saved
979 stp x6, x7, [x1, #SDEI_EVENT_INTRE <<
980 stp x8, x9, [x1, #SDEI_EVENT_INTRE <<
981 stp x10, x11, [x1, #SDEI_EVENT_INT <<
982 stp x12, x13, [x1, #SDEI_EVENT_INT <<
983 stp x14, x15, [x1, #SDEI_EVENT_INT <<
984 stp x16, x17, [x1, #SDEI_EVENT_INT <<
985 stp x18, x19, [x1, #SDEI_EVENT_INT <<
986 stp x20, x21, [x1, #SDEI_EVENT_INT <<
987 stp x22, x23, [x1, #SDEI_EVENT_INT <<
988 stp x24, x25, [x1, #SDEI_EVENT_INT <<
989 stp x26, x27, [x1, #SDEI_EVENT_INT <<
990 stp x28, x29, [x1, #SDEI_EVENT_INT <<
991 mov x4, sp <<
992 stp lr, x4, [x1, #SDEI_EVENT_INTRE <<
993 <<
994 mov x19, x1 <<
995 <<
996 /* Store the registered-event for cras <<
997 ldrb w4, [x19, #SDEI_EVENT_PRIORITY <<
998 cbnz w4, 1f <<
999 adr_this_cpu dst=x5, sym=sdei_active_n <<
1000 b 2f <<
1001 1: adr_this_cpu dst=x5, sym=sdei_active_ <<
1002 2: str x19, [x5] <<
1003 1291
1004 #ifdef CONFIG_VMAP_STACK !! 1292 .align 4
1005 /* !! 1293 .globl restore_current
1006 * entry.S may have been using sp as !! 1294 restore_current:
1007 * this is a normal or critical event !! 1295 LOAD_CURRENT(g6, o0)
1008 * stack for this CPU. !! 1296 retl
>> 1297 nop
>> 1298
>> 1299 #ifdef CONFIG_PCIC_PCI
>> 1300 #include <asm/pcic.h>
>> 1301
>> 1302 .align 4
>> 1303 .globl linux_trap_ipi15_pcic
>> 1304 linux_trap_ipi15_pcic:
>> 1305 rd %wim, %l3
>> 1306 SAVE_ALL
>> 1307
>> 1308 /*
>> 1309 * First deactivate NMI
>> 1310 * or we cannot drop ET, cannot get window spill traps.
>> 1311 * The busy loop is necessary because the PIO error
>> 1312 * sometimes does not go away quickly and we trap again.
1009 */ 1313 */
1010 cbnz w4, 1f !! 1314 sethi %hi(pcic_regs), %o1
1011 ldr_this_cpu dst=x5, sym=sdei_stack_n !! 1315 ld [%o1 + %lo(pcic_regs)], %o2
1012 b 2f <<
1013 1: ldr_this_cpu dst=x5, sym=sdei_stack_c <<
1014 2: mov x6, #SDEI_STACK_SIZE <<
1015 add x5, x5, x6 <<
1016 mov sp, x5 <<
1017 #endif <<
1018 1316
1019 #ifdef CONFIG_SHADOW_CALL_STACK !! 1317 ! Get pending status for printouts later.
1020 /* Use a separate shadow call stack f !! 1318 ld [%o2 + PCI_SYS_INT_PENDING], %o0
1021 cbnz w4, 3f <<
1022 ldr_this_cpu dst=scs_sp, sym=sdei_sha <<
1023 b 4f <<
1024 3: ldr_this_cpu dst=scs_sp, sym=sdei_sha <<
1025 4: <<
1026 #endif <<
1027 1319
1028 /* !! 1320 mov PCI_SYS_INT_PENDING_CLEAR_ALL, %o1
1029 * We may have interrupted userspace, !! 1321 stb %o1, [%o2 + PCI_SYS_INT_PENDING_CLEAR]
1030 * return-to either of these. We can' !! 1322 1:
1031 */ !! 1323 ld [%o2 + PCI_SYS_INT_PENDING], %o1
1032 mrs x28, sp_el0 !! 1324 andcc %o1, ((PCI_SYS_INT_PENDING_PIO|PCI_SYS_INT_PENDING_PCI)>>24), %g0
1033 ldr_this_cpu dst=x0, sym=__entry_t !! 1325 bne 1b
1034 msr sp_el0, x0 !! 1326 nop
1035 !! 1327
1036 /* If we interrupted the kernel point !! 1328 or %l0, PSR_PIL, %l4
1037 and x0, x3, #0xc !! 1329 wr %l4, 0x0, %psr
1038 mrs x1, CurrentEL !! 1330 WRITE_PAUSE
1039 cmp x0, x1 !! 1331 wr %l4, PSR_ET, %psr
1040 csel x29, x29, xzr, eq // fp !! 1332 WRITE_PAUSE
1041 csel x4, x2, xzr, eq // el !! 1333
1042 !! 1334 call pcic_nmi
1043 stp x29, x4, [sp, #-16]! !! 1335 add %sp, STACKFRAME_SZ, %o1 ! struct pt_regs *regs
1044 mov x29, sp !! 1336 RESTORE_ALL
1045 !! 1337
1046 add x0, x19, #SDEI_EVENT_INTREGS !! 1338 .globl pcic_nmi_trap_patch
1047 mov x1, x19 !! 1339 pcic_nmi_trap_patch:
1048 bl __sdei_handler !! 1340 sethi %hi(linux_trap_ipi15_pcic), %l3
1049 !! 1341 jmpl %l3 + %lo(linux_trap_ipi15_pcic), %g0
1050 msr sp_el0, x28 !! 1342 rd %psr, %l0
1051 /* restore regs >x17 that we clobbere !! 1343 .word 0
1052 mov x4, x19 // keep x4 fo !! 1344
1053 ldp x28, x29, [x4, #SDEI_EVENT_IN !! 1345 #endif /* CONFIG_PCIC_PCI */
1054 ldp x18, x19, [x4, #SDEI_EVENT_IN !! 1346
1055 ldp lr, x1, [x4, #SDEI_EVENT_INTR !! 1347 .globl flushw_all
1056 mov sp, x1 !! 1348 flushw_all:
1057 !! 1349 save %sp, -0x40, %sp
1058 mov x1, x0 // ad !! 1350 save %sp, -0x40, %sp
1059 /* x0 = (x0 <= SDEI_EV_FAILED) ? !! 1351 save %sp, -0x40, %sp
1060 * EVENT_COMPLETE:EVENT_COMPLETE_AND_ !! 1352 save %sp, -0x40, %sp
1061 */ !! 1353 save %sp, -0x40, %sp
1062 cmp x0, #SDEI_EV_FAILED !! 1354 save %sp, -0x40, %sp
1063 mov_q x2, SDEI_1_0_FN_SDEI_EVENT_CO !! 1355 save %sp, -0x40, %sp
1064 mov_q x3, SDEI_1_0_FN_SDEI_EVENT_CO !! 1356 restore
1065 csel x0, x2, x3, ls !! 1357 restore
1066 !! 1358 restore
1067 ldr_l x2, sdei_exit_mode !! 1359 restore
1068 !! 1360 restore
1069 /* Clear the registered-event seen by !! 1361 restore
1070 ldrb w3, [x4, #SDEI_EVENT_PRIORITY !! 1362 ret
1071 cbnz w3, 1f !! 1363 restore
1072 adr_this_cpu dst=x5, sym=sdei_active_ <<
1073 b 2f <<
1074 1: adr_this_cpu dst=x5, sym=sdei_active_ <<
1075 2: str xzr, [x5] <<
1076 1364
1077 alternative_if_not ARM64_UNMAP_KERNEL_AT_EL0 !! 1365 #ifdef CONFIG_SMP
1078 sdei_handler_exit exit_mode=x2 !! 1366 ENTRY(hard_smp_processor_id)
1079 alternative_else_nop_endif !! 1367 661: rd %tbr, %g1
1080 !! 1368 srl %g1, 12, %o0
1081 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 !! 1369 and %o0, 3, %o0
1082 tramp_alias dst=x5, sym=__sdei_as !! 1370 .section .cpuid_patch, "ax"
1083 br x5 !! 1371 /* Instruction location. */
>> 1372 .word 661b
>> 1373 /* SUN4D implementation. */
>> 1374 lda [%g0] ASI_M_VIKING_TMP1, %o0
>> 1375 nop
>> 1376 nop
>> 1377 /* LEON implementation. */
>> 1378 rd %asr17, %o0
>> 1379 srl %o0, 0x1c, %o0
>> 1380 nop
>> 1381 .previous
>> 1382 retl
>> 1383 nop
>> 1384 ENDPROC(hard_smp_processor_id)
1084 #endif 1385 #endif
1085 SYM_CODE_END(__sdei_asm_handler) <<
1086 NOKPROBE(__sdei_asm_handler) <<
1087 1386
1088 SYM_CODE_START(__sdei_handler_abort) !! 1387 /* End of entry.S */
1089 mov_q x0, SDEI_1_0_FN_SDEI_EVENT_CO <<
1090 adr x1, 1f <<
1091 ldr_l x2, sdei_exit_mode <<
1092 sdei_handler_exit exit_mode=x2 <<
1093 // exit the handler and jump to the n <<
1094 // Exit will stomp x0-x17, PSTATE, EL <<
1095 1: ret <<
1096 SYM_CODE_END(__sdei_handler_abort) <<
1097 NOKPROBE(__sdei_handler_abort) <<
1098 #endif /* CONFIG_ARM_SDE_INTERFACE */ <<
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