1 # SPDX-License-Identifier: GPL-2.0-only !! 1 # SPDX-License-Identifier: GPL-2.0
2 config CSKY !! 2 config MIPS
3 def_bool y !! 3 bool
4 select ARCH_32BIT_OFF_T !! 4 default y
5 select ARCH_HAS_CPU_CACHE_ALIASING !! 5 select ARCH_32BIT_OFF_T if !64BIT
6 select ARCH_HAS_DMA_PREP_COHERENT !! 6 select ARCH_BINFMT_ELF_STATE if MIPS_FP_SUPPORT
>> 7 select ARCH_HAS_CURRENT_STACK_POINTER if !CC_IS_CLANG || CLANG_VERSION >= 140000
>> 8 select ARCH_HAS_DEBUG_VIRTUAL if !64BIT
>> 9 select ARCH_HAS_FORTIFY_SOURCE
>> 10 select ARCH_HAS_KCOV
>> 11 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE if !EVA
>> 12 select ARCH_HAS_PTE_SPECIAL if !(32BIT && CPU_HAS_RIXI)
>> 13 select ARCH_HAS_STRNCPY_FROM_USER
>> 14 select ARCH_HAS_STRNLEN_USER
>> 15 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
>> 16 select ARCH_HAS_UBSAN_SANITIZE_ALL
7 select ARCH_HAS_GCOV_PROFILE_ALL 17 select ARCH_HAS_GCOV_PROFILE_ALL
8 select ARCH_HAS_SYNC_DMA_FOR_CPU !! 18 select ARCH_KEEP_MEMBLOCK
9 select ARCH_HAS_SYNC_DMA_FOR_DEVICE !! 19 select ARCH_SUPPORTS_UPROBES
10 select ARCH_USE_BUILTIN_BSWAP 20 select ARCH_USE_BUILTIN_BSWAP
>> 21 select ARCH_USE_CMPXCHG_LOCKREF if 64BIT
>> 22 select ARCH_USE_MEMTEST
11 select ARCH_USE_QUEUED_RWLOCKS 23 select ARCH_USE_QUEUED_RWLOCKS
12 select ARCH_USE_QUEUED_SPINLOCKS 24 select ARCH_USE_QUEUED_SPINLOCKS
13 select ARCH_HAS_CURRENT_STACK_POINTER !! 25 select ARCH_SUPPORTS_HUGETLBFS if CPU_SUPPORTS_HUGEPAGES
14 select ARCH_INLINE_READ_LOCK if !PREEM !! 26 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
15 select ARCH_INLINE_READ_LOCK_BH if !PR !! 27 select ARCH_WANT_IPC_PARSE_VERSION
16 select ARCH_INLINE_READ_LOCK_IRQ if !P !! 28 select ARCH_WANT_LD_ORPHAN_WARN
17 select ARCH_INLINE_READ_LOCK_IRQSAVE i !! 29 select BUILDTIME_TABLE_SORT
18 select ARCH_INLINE_READ_UNLOCK if !PRE !! 30 select CLONE_BACKWARDS
19 select ARCH_INLINE_READ_UNLOCK_BH if ! !! 31 select CPU_NO_EFFICIENT_FFS if (TARGET_ISA_REV < 1)
20 select ARCH_INLINE_READ_UNLOCK_IRQ if !! 32 select CPU_PM if CPU_IDLE
21 select ARCH_INLINE_READ_UNLOCK_IRQREST !! 33 select GENERIC_ATOMIC64 if !64BIT
22 select ARCH_INLINE_WRITE_LOCK if !PREE !! 34 select GENERIC_CMOS_UPDATE
23 select ARCH_INLINE_WRITE_LOCK_BH if !P !! 35 select GENERIC_CPU_AUTOPROBE
24 select ARCH_INLINE_WRITE_LOCK_IRQ if ! !! 36 select GENERIC_GETTIMEOFDAY
25 select ARCH_INLINE_WRITE_LOCK_IRQSAVE !! 37 select GENERIC_IOMAP
26 select ARCH_INLINE_WRITE_UNLOCK if !PR !! 38 select GENERIC_IRQ_PROBE
27 select ARCH_INLINE_WRITE_UNLOCK_BH if !! 39 select GENERIC_IRQ_SHOW
28 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !! 40 select GENERIC_ISA_DMA if EISA
29 select ARCH_INLINE_WRITE_UNLOCK_IRQRES <<
30 select ARCH_INLINE_SPIN_TRYLOCK if !PR <<
31 select ARCH_INLINE_SPIN_TRYLOCK_BH if <<
32 select ARCH_INLINE_SPIN_LOCK if !PREEM <<
33 select ARCH_INLINE_SPIN_LOCK_BH if !PR <<
34 select ARCH_INLINE_SPIN_LOCK_IRQ if !P <<
35 select ARCH_INLINE_SPIN_LOCK_IRQSAVE i <<
36 select ARCH_INLINE_SPIN_UNLOCK if !PRE <<
37 select ARCH_INLINE_SPIN_UNLOCK_BH if ! <<
38 select ARCH_INLINE_SPIN_UNLOCK_IRQ if <<
39 select ARCH_INLINE_SPIN_UNLOCK_IRQREST <<
40 select ARCH_NEED_CMPXCHG_1_EMU <<
41 select ARCH_WANT_FRAME_POINTERS if !CP <<
42 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_ <<
43 select COMMON_CLK <<
44 select CLKSRC_MMIO <<
45 select CSKY_MPINTC if CPU_CK860 <<
46 select CSKY_MP_TIMER if CPU_CK860 <<
47 select CSKY_APB_INTC <<
48 select DMA_DIRECT_REMAP <<
49 select IRQ_DOMAIN <<
50 select DW_APB_TIMER_OF <<
51 select GENERIC_IOREMAP <<
52 select GENERIC_LIB_ASHLDI3 41 select GENERIC_LIB_ASHLDI3
53 select GENERIC_LIB_ASHRDI3 42 select GENERIC_LIB_ASHRDI3
54 select GENERIC_LIB_LSHRDI3 <<
55 select GENERIC_LIB_MULDI3 <<
56 select GENERIC_LIB_CMPDI2 43 select GENERIC_LIB_CMPDI2
>> 44 select GENERIC_LIB_LSHRDI3
57 select GENERIC_LIB_UCMPDI2 45 select GENERIC_LIB_UCMPDI2
58 select GENERIC_ALLOCATOR !! 46 select GENERIC_SCHED_CLOCK if !CAVIUM_OCTEON_SOC
59 select GENERIC_ATOMIC64 <<
60 select GENERIC_CPU_DEVICES <<
61 select GENERIC_IRQ_CHIP <<
62 select GENERIC_IRQ_PROBE <<
63 select GENERIC_IRQ_SHOW <<
64 select GENERIC_IRQ_MULTI_HANDLER <<
65 select GENERIC_SCHED_CLOCK <<
66 select GENERIC_SMP_IDLE_THREAD 47 select GENERIC_SMP_IDLE_THREAD
67 select GENERIC_TIME_VSYSCALL 48 select GENERIC_TIME_VSYSCALL
68 select GENERIC_VDSO_32 !! 49 select GUP_GET_PTE_LOW_HIGH if CPU_MIPS32 && PHYS_ADDR_T_64BIT
69 select GENERIC_GETTIMEOFDAY !! 50 select HAVE_ARCH_COMPILER_H
70 select GX6605S_TIMER if CPU_CK610 !! 51 select HAVE_ARCH_JUMP_LABEL
71 select HAVE_ARCH_TRACEHOOK !! 52 select HAVE_ARCH_KGDB if MIPS_FP_SUPPORT
72 select HAVE_ARCH_AUDITSYSCALL !! 53 select HAVE_ARCH_MMAP_RND_BITS if MMU
73 select HAVE_ARCH_JUMP_LABEL if !CPU_CK !! 54 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if MMU && COMPAT
74 select HAVE_ARCH_JUMP_LABEL_RELATIVE <<
75 select HAVE_ARCH_MMAP_RND_BITS <<
76 select HAVE_ARCH_SECCOMP_FILTER 55 select HAVE_ARCH_SECCOMP_FILTER
77 select HAVE_CONTEXT_TRACKING_USER !! 56 select HAVE_ARCH_TRACEHOOK
78 select HAVE_VIRT_CPU_ACCOUNTING_GEN !! 57 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES
79 select HAVE_DEBUG_BUGVERBOSE !! 58 select HAVE_ASM_MODVERSIONS
>> 59 select HAVE_CONTEXT_TRACKING
>> 60 select HAVE_TIF_NOHZ
>> 61 select HAVE_C_RECORDMCOUNT
80 select HAVE_DEBUG_KMEMLEAK 62 select HAVE_DEBUG_KMEMLEAK
>> 63 select HAVE_DEBUG_STACKOVERFLOW
>> 64 select HAVE_DMA_CONTIGUOUS
81 select HAVE_DYNAMIC_FTRACE 65 select HAVE_DYNAMIC_FTRACE
82 select HAVE_DYNAMIC_FTRACE_WITH_REGS !! 66 select HAVE_EBPF_JIT if !CPU_MICROMIPS && \
83 select HAVE_GENERIC_VDSO !! 67 !CPU_DADDI_WORKAROUNDS && \
84 select HAVE_FUNCTION_TRACER !! 68 !CPU_R4000_WORKAROUNDS && \
85 select HAVE_FUNCTION_GRAPH_TRACER !! 69 !CPU_R4400_WORKAROUNDS
86 select HAVE_FUNCTION_ERROR_INJECTION !! 70 select HAVE_EXIT_THREAD
>> 71 select HAVE_FAST_GUP
87 select HAVE_FTRACE_MCOUNT_RECORD 72 select HAVE_FTRACE_MCOUNT_RECORD
88 select HAVE_KERNEL_GZIP !! 73 select HAVE_FUNCTION_GRAPH_TRACER
89 select HAVE_KERNEL_LZO !! 74 select HAVE_FUNCTION_TRACER
90 select HAVE_KERNEL_LZMA !! 75 select HAVE_GCC_PLUGINS
91 select HAVE_KPROBES if !CPU_CK610 !! 76 select HAVE_GENERIC_VDSO
92 select HAVE_KPROBES_ON_FTRACE if !CPU_ !! 77 select HAVE_IOREMAP_PROT
93 select HAVE_KRETPROBES if !CPU_CK610 !! 78 select HAVE_IRQ_EXIT_ON_IRQ_STACK
94 select HAVE_PAGE_SIZE_4KB !! 79 select HAVE_IRQ_TIME_ACCOUNTING
>> 80 select HAVE_KPROBES
>> 81 select HAVE_KRETPROBES
>> 82 select HAVE_LD_DEAD_CODE_DATA_ELIMINATION
>> 83 select HAVE_MOD_ARCH_SPECIFIC
>> 84 select HAVE_NMI
95 select HAVE_PERF_EVENTS 85 select HAVE_PERF_EVENTS
96 select HAVE_PERF_REGS 86 select HAVE_PERF_REGS
97 select HAVE_PERF_USER_STACK_DUMP 87 select HAVE_PERF_USER_STACK_DUMP
98 select HAVE_DMA_CONTIGUOUS <<
99 select HAVE_REGS_AND_STACK_ACCESS_API 88 select HAVE_REGS_AND_STACK_ACCESS_API
>> 89 select HAVE_RSEQ
>> 90 select HAVE_SPARSE_SYSCALL_NR
100 select HAVE_STACKPROTECTOR 91 select HAVE_STACKPROTECTOR
101 select HAVE_SYSCALL_TRACEPOINTS 92 select HAVE_SYSCALL_TRACEPOINTS
102 select HOTPLUG_CORE_SYNC_DEAD if HOTPL !! 93 select HAVE_VIRT_CPU_ACCOUNTING_GEN if 64BIT || !SMP
103 select LOCK_MM_AND_FIND_VMA !! 94 select IRQ_FORCED_THREADING
104 select MAY_HAVE_SPARSE_IRQ !! 95 select ISA if EISA
105 select MODULES_USE_ELF_RELA if MODULES !! 96 select MODULES_USE_ELF_REL if MODULES
106 select OF !! 97 select MODULES_USE_ELF_RELA if MODULES && 64BIT
107 select OF_EARLY_FLATTREE !! 98 select PERF_USE_VMALLOC
108 select PERF_USE_VMALLOC if CPU_CK610 !! 99 select PCI_MSI_ARCH_FALLBACKS if PCI_MSI
109 select RTC_LIB 100 select RTC_LIB
110 select TIMER_OF !! 101 select SYSCTL_EXCEPTION_TRACE
111 select GENERIC_PCI_IOMAP <<
112 select HAVE_PCI <<
113 select PCI_DOMAINS_GENERIC if PCI <<
114 select PCI_SYSCALL if PCI <<
115 select PCI_MSI if PCI <<
116 select TRACE_IRQFLAGS_SUPPORT 102 select TRACE_IRQFLAGS_SUPPORT
>> 103 select VIRT_TO_BUS
>> 104 select ARCH_HAS_ELFCORE_COMPAT
>> 105 select HAVE_ARCH_KCSAN if 64BIT
117 106
118 config LOCKDEP_SUPPORT !! 107 config MIPS_FIXUP_BIGPHYS_ADDR
119 def_bool y !! 108 bool
>> 109
>> 110 config MIPS_GENERIC
>> 111 bool
>> 112
>> 113 config MACH_INGENIC
>> 114 bool
>> 115 select SYS_SUPPORTS_32BIT_KERNEL
>> 116 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 117 select SYS_SUPPORTS_ZBOOT
>> 118 select DMA_NONCOHERENT
>> 119 select ARCH_HAS_SYNC_DMA_FOR_CPU
>> 120 select IRQ_MIPS_CPU
>> 121 select PINCTRL
>> 122 select GPIOLIB
>> 123 select COMMON_CLK
>> 124 select GENERIC_IRQ_CHIP
>> 125 select BUILTIN_DTB if MIPS_NO_APPENDED_DTB
>> 126 select USE_OF
>> 127 select CPU_SUPPORTS_CPUFREQ
>> 128 select MIPS_EXTERNAL_TIMER
>> 129
>> 130 menu "Machine selection"
>> 131
>> 132 choice
>> 133 prompt "System type"
>> 134 default MIPS_GENERIC_KERNEL
>> 135
>> 136 config MIPS_GENERIC_KERNEL
>> 137 bool "Generic board-agnostic MIPS kernel"
>> 138 select ARCH_HAS_SETUP_DMA_OPS
>> 139 select MIPS_GENERIC
>> 140 select BOOT_RAW
>> 141 select BUILTIN_DTB
>> 142 select CEVT_R4K
>> 143 select CLKSRC_MIPS_GIC
>> 144 select COMMON_CLK
>> 145 select CPU_MIPSR2_IRQ_EI
>> 146 select CPU_MIPSR2_IRQ_VI
>> 147 select CSRC_R4K
>> 148 select DMA_NONCOHERENT
>> 149 select HAVE_PCI
>> 150 select IRQ_MIPS_CPU
>> 151 select MIPS_AUTO_PFN_OFFSET
>> 152 select MIPS_CPU_SCACHE
>> 153 select MIPS_GIC
>> 154 select MIPS_L1_CACHE_SHIFT_7
>> 155 select NO_EXCEPT_FILL
>> 156 select PCI_DRIVERS_GENERIC
>> 157 select SMP_UP if SMP
>> 158 select SWAP_IO_SPACE
>> 159 select SYS_HAS_CPU_MIPS32_R1
>> 160 select SYS_HAS_CPU_MIPS32_R2
>> 161 select SYS_HAS_CPU_MIPS32_R6
>> 162 select SYS_HAS_CPU_MIPS64_R1
>> 163 select SYS_HAS_CPU_MIPS64_R2
>> 164 select SYS_HAS_CPU_MIPS64_R6
>> 165 select SYS_SUPPORTS_32BIT_KERNEL
>> 166 select SYS_SUPPORTS_64BIT_KERNEL
>> 167 select SYS_SUPPORTS_BIG_ENDIAN
>> 168 select SYS_SUPPORTS_HIGHMEM
>> 169 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 170 select SYS_SUPPORTS_MICROMIPS
>> 171 select SYS_SUPPORTS_MIPS16
>> 172 select SYS_SUPPORTS_MIPS_CPS
>> 173 select SYS_SUPPORTS_MULTITHREADING
>> 174 select SYS_SUPPORTS_RELOCATABLE
>> 175 select SYS_SUPPORTS_SMARTMIPS
>> 176 select SYS_SUPPORTS_ZBOOT
>> 177 select UHI_BOOT
>> 178 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 179 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 180 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 181 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 182 select USB_UHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 183 select USB_UHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 184 select USE_OF
>> 185 help
>> 186 Select this to build a kernel which aims to support multiple boards,
>> 187 generally using a flattened device tree passed from the bootloader
>> 188 using the boot protocol defined in the UHI (Unified Hosting
>> 189 Interface) specification.
>> 190
>> 191 config MIPS_ALCHEMY
>> 192 bool "Alchemy processor based machines"
>> 193 select PHYS_ADDR_T_64BIT
>> 194 select CEVT_R4K
>> 195 select CSRC_R4K
>> 196 select IRQ_MIPS_CPU
>> 197 select DMA_NONCOHERENT # Au1000,1500,1100 aren't, rest is
>> 198 select MIPS_FIXUP_BIGPHYS_ADDR if PCI
>> 199 select SYS_HAS_CPU_MIPS32_R1
>> 200 select SYS_SUPPORTS_32BIT_KERNEL
>> 201 select SYS_SUPPORTS_APM_EMULATION
>> 202 select GPIOLIB
>> 203 select SYS_SUPPORTS_ZBOOT
>> 204 select COMMON_CLK
>> 205
>> 206 config AR7
>> 207 bool "Texas Instruments AR7"
>> 208 select BOOT_ELF32
>> 209 select COMMON_CLK
>> 210 select DMA_NONCOHERENT
>> 211 select CEVT_R4K
>> 212 select CSRC_R4K
>> 213 select IRQ_MIPS_CPU
>> 214 select NO_EXCEPT_FILL
>> 215 select SWAP_IO_SPACE
>> 216 select SYS_HAS_CPU_MIPS32_R1
>> 217 select SYS_HAS_EARLY_PRINTK
>> 218 select SYS_SUPPORTS_32BIT_KERNEL
>> 219 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 220 select SYS_SUPPORTS_MIPS16
>> 221 select SYS_SUPPORTS_ZBOOT_UART16550
>> 222 select GPIOLIB
>> 223 select VLYNQ
>> 224 help
>> 225 Support for the Texas Instruments AR7 System-on-a-Chip
>> 226 family: TNETD7100, 7200 and 7300.
>> 227
>> 228 config ATH25
>> 229 bool "Atheros AR231x/AR531x SoC support"
>> 230 select CEVT_R4K
>> 231 select CSRC_R4K
>> 232 select DMA_NONCOHERENT
>> 233 select IRQ_MIPS_CPU
>> 234 select IRQ_DOMAIN
>> 235 select SYS_HAS_CPU_MIPS32_R1
>> 236 select SYS_SUPPORTS_BIG_ENDIAN
>> 237 select SYS_SUPPORTS_32BIT_KERNEL
>> 238 select SYS_HAS_EARLY_PRINTK
>> 239 help
>> 240 Support for Atheros AR231x and Atheros AR531x based boards
>> 241
>> 242 config ATH79
>> 243 bool "Atheros AR71XX/AR724X/AR913X based boards"
>> 244 select ARCH_HAS_RESET_CONTROLLER
>> 245 select BOOT_RAW
>> 246 select CEVT_R4K
>> 247 select CSRC_R4K
>> 248 select DMA_NONCOHERENT
>> 249 select GPIOLIB
>> 250 select PINCTRL
>> 251 select COMMON_CLK
>> 252 select IRQ_MIPS_CPU
>> 253 select SYS_HAS_CPU_MIPS32_R2
>> 254 select SYS_HAS_EARLY_PRINTK
>> 255 select SYS_SUPPORTS_32BIT_KERNEL
>> 256 select SYS_SUPPORTS_BIG_ENDIAN
>> 257 select SYS_SUPPORTS_MIPS16
>> 258 select SYS_SUPPORTS_ZBOOT_UART_PROM
>> 259 select USE_OF
>> 260 select USB_EHCI_ROOT_HUB_TT if USB_EHCI_HCD_PLATFORM
>> 261 help
>> 262 Support for the Atheros AR71XX/AR724X/AR913X SoCs.
>> 263
>> 264 config BMIPS_GENERIC
>> 265 bool "Broadcom Generic BMIPS kernel"
>> 266 select ARCH_HAS_RESET_CONTROLLER
>> 267 select ARCH_HAS_SYNC_DMA_FOR_CPU_ALL
>> 268 select BOOT_RAW
>> 269 select NO_EXCEPT_FILL
>> 270 select USE_OF
>> 271 select CEVT_R4K
>> 272 select CSRC_R4K
>> 273 select SYNC_R4K
>> 274 select COMMON_CLK
>> 275 select BCM6345_L1_IRQ
>> 276 select BCM7038_L1_IRQ
>> 277 select BCM7120_L2_IRQ
>> 278 select BRCMSTB_L2_IRQ
>> 279 select IRQ_MIPS_CPU
>> 280 select DMA_NONCOHERENT
>> 281 select SYS_SUPPORTS_32BIT_KERNEL
>> 282 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 283 select SYS_SUPPORTS_BIG_ENDIAN
>> 284 select SYS_SUPPORTS_HIGHMEM
>> 285 select SYS_HAS_CPU_BMIPS32_3300
>> 286 select SYS_HAS_CPU_BMIPS4350
>> 287 select SYS_HAS_CPU_BMIPS4380
>> 288 select SYS_HAS_CPU_BMIPS5000
>> 289 select SWAP_IO_SPACE
>> 290 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 291 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 292 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 293 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 294 select HARDIRQS_SW_RESEND
>> 295 select HAVE_PCI
>> 296 select PCI_DRIVERS_GENERIC
>> 297 help
>> 298 Build a generic DT-based kernel image that boots on select
>> 299 BCM33xx cable modem chips, BCM63xx DSL chips, and BCM7xxx set-top
>> 300 box chips. Note that CONFIG_CPU_BIG_ENDIAN/CONFIG_CPU_LITTLE_ENDIAN
>> 301 must be set appropriately for your board.
>> 302
>> 303 config BCM47XX
>> 304 bool "Broadcom BCM47XX based boards"
>> 305 select BOOT_RAW
>> 306 select CEVT_R4K
>> 307 select CSRC_R4K
>> 308 select DMA_NONCOHERENT
>> 309 select HAVE_PCI
>> 310 select IRQ_MIPS_CPU
>> 311 select SYS_HAS_CPU_MIPS32_R1
>> 312 select NO_EXCEPT_FILL
>> 313 select SYS_SUPPORTS_32BIT_KERNEL
>> 314 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 315 select SYS_SUPPORTS_MIPS16
>> 316 select SYS_SUPPORTS_ZBOOT
>> 317 select SYS_HAS_EARLY_PRINTK
>> 318 select USE_GENERIC_EARLY_PRINTK_8250
>> 319 select GPIOLIB
>> 320 select LEDS_GPIO_REGISTER
>> 321 select BCM47XX_NVRAM
>> 322 select BCM47XX_SPROM
>> 323 select BCM47XX_SSB if !BCM47XX_BCMA
>> 324 help
>> 325 Support for BCM47XX based boards
>> 326
>> 327 config BCM63XX
>> 328 bool "Broadcom BCM63XX based boards"
>> 329 select BOOT_RAW
>> 330 select CEVT_R4K
>> 331 select CSRC_R4K
>> 332 select SYNC_R4K
>> 333 select DMA_NONCOHERENT
>> 334 select IRQ_MIPS_CPU
>> 335 select SYS_SUPPORTS_32BIT_KERNEL
>> 336 select SYS_SUPPORTS_BIG_ENDIAN
>> 337 select SYS_HAS_EARLY_PRINTK
>> 338 select SYS_HAS_CPU_BMIPS32_3300
>> 339 select SYS_HAS_CPU_BMIPS4350
>> 340 select SYS_HAS_CPU_BMIPS4380
>> 341 select SWAP_IO_SPACE
>> 342 select GPIOLIB
>> 343 select MIPS_L1_CACHE_SHIFT_4
>> 344 select HAVE_LEGACY_CLK
>> 345 help
>> 346 Support for BCM63XX based boards
>> 347
>> 348 config MIPS_COBALT
>> 349 bool "Cobalt Server"
>> 350 select CEVT_R4K
>> 351 select CSRC_R4K
>> 352 select CEVT_GT641XX
>> 353 select DMA_NONCOHERENT
>> 354 select FORCE_PCI
>> 355 select I8253
>> 356 select I8259
>> 357 select IRQ_MIPS_CPU
>> 358 select IRQ_GT641XX
>> 359 select PCI_GT64XXX_PCI0
>> 360 select SYS_HAS_CPU_NEVADA
>> 361 select SYS_HAS_EARLY_PRINTK
>> 362 select SYS_SUPPORTS_32BIT_KERNEL
>> 363 select SYS_SUPPORTS_64BIT_KERNEL
>> 364 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 365 select USE_GENERIC_EARLY_PRINTK_8250
>> 366
>> 367 config MACH_DECSTATION
>> 368 bool "DECstations"
>> 369 select BOOT_ELF32
>> 370 select CEVT_DS1287
>> 371 select CEVT_R4K if CPU_R4X00
>> 372 select CSRC_IOASIC
>> 373 select CSRC_R4K if CPU_R4X00
>> 374 select CPU_DADDI_WORKAROUNDS if 64BIT
>> 375 select CPU_R4000_WORKAROUNDS if 64BIT
>> 376 select CPU_R4400_WORKAROUNDS if 64BIT
>> 377 select DMA_NONCOHERENT
>> 378 select NO_IOPORT_MAP
>> 379 select IRQ_MIPS_CPU
>> 380 select SYS_HAS_CPU_R3000
>> 381 select SYS_HAS_CPU_R4X00
>> 382 select SYS_SUPPORTS_32BIT_KERNEL
>> 383 select SYS_SUPPORTS_64BIT_KERNEL
>> 384 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 385 select SYS_SUPPORTS_128HZ
>> 386 select SYS_SUPPORTS_256HZ
>> 387 select SYS_SUPPORTS_1024HZ
>> 388 select MIPS_L1_CACHE_SHIFT_4
>> 389 help
>> 390 This enables support for DEC's MIPS based workstations. For details
>> 391 see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the
>> 392 DECstation porting pages on <http://decstation.unix-ag.org/>.
>> 393
>> 394 If you have one of the following DECstation Models you definitely
>> 395 want to choose R4xx0 for the CPU Type:
>> 396
>> 397 DECstation 5000/50
>> 398 DECstation 5000/150
>> 399 DECstation 5000/260
>> 400 DECsystem 5900/260
>> 401
>> 402 otherwise choose R3000.
>> 403
>> 404 config MACH_JAZZ
>> 405 bool "Jazz family of machines"
>> 406 select ARC_MEMORY
>> 407 select ARC_PROMLIB
>> 408 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 409 select ARCH_MIGHT_HAVE_PC_SERIO
>> 410 select DMA_OPS
>> 411 select FW_ARC
>> 412 select FW_ARC32
>> 413 select ARCH_MAY_HAVE_PC_FDC
>> 414 select CEVT_R4K
>> 415 select CSRC_R4K
>> 416 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 417 select GENERIC_ISA_DMA
>> 418 select HAVE_PCSPKR_PLATFORM
>> 419 select IRQ_MIPS_CPU
>> 420 select I8253
>> 421 select I8259
>> 422 select ISA
>> 423 select SYS_HAS_CPU_R4X00
>> 424 select SYS_SUPPORTS_32BIT_KERNEL
>> 425 select SYS_SUPPORTS_64BIT_KERNEL
>> 426 select SYS_SUPPORTS_100HZ
>> 427 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 428 help
>> 429 This a family of machines based on the MIPS R4030 chipset which was
>> 430 used by several vendors to build RISC/os and Windows NT workstations.
>> 431 Members include the Acer PICA, MIPS Magnum 4000, MIPS Millennium and
>> 432 Olivetti M700-10 workstations.
>> 433
>> 434 config MACH_INGENIC_SOC
>> 435 bool "Ingenic SoC based machines"
>> 436 select MIPS_GENERIC
>> 437 select MACH_INGENIC
>> 438 select SYS_SUPPORTS_ZBOOT_UART16550
>> 439 select CPU_SUPPORTS_CPUFREQ
>> 440 select MIPS_EXTERNAL_TIMER
>> 441
>> 442 config LANTIQ
>> 443 bool "Lantiq based platforms"
>> 444 select DMA_NONCOHERENT
>> 445 select IRQ_MIPS_CPU
>> 446 select CEVT_R4K
>> 447 select CSRC_R4K
>> 448 select SYS_HAS_CPU_MIPS32_R1
>> 449 select SYS_HAS_CPU_MIPS32_R2
>> 450 select SYS_SUPPORTS_BIG_ENDIAN
>> 451 select SYS_SUPPORTS_32BIT_KERNEL
>> 452 select SYS_SUPPORTS_MIPS16
>> 453 select SYS_SUPPORTS_MULTITHREADING
>> 454 select SYS_SUPPORTS_VPE_LOADER
>> 455 select SYS_HAS_EARLY_PRINTK
>> 456 select GPIOLIB
>> 457 select SWAP_IO_SPACE
>> 458 select BOOT_RAW
>> 459 select HAVE_LEGACY_CLK
>> 460 select USE_OF
>> 461 select PINCTRL
>> 462 select PINCTRL_LANTIQ
>> 463 select ARCH_HAS_RESET_CONTROLLER
>> 464 select RESET_CONTROLLER
>> 465
>> 466 config MACH_LOONGSON32
>> 467 bool "Loongson 32-bit family of machines"
>> 468 select SYS_SUPPORTS_ZBOOT
>> 469 help
>> 470 This enables support for the Loongson-1 family of machines.
>> 471
>> 472 Loongson-1 is a family of 32-bit MIPS-compatible SoCs developed by
>> 473 the Institute of Computing Technology (ICT), Chinese Academy of
>> 474 Sciences (CAS).
>> 475
>> 476 config MACH_LOONGSON2EF
>> 477 bool "Loongson-2E/F family of machines"
>> 478 select SYS_SUPPORTS_ZBOOT
>> 479 help
>> 480 This enables the support of early Loongson-2E/F family of machines.
>> 481
>> 482 config MACH_LOONGSON64
>> 483 bool "Loongson 64-bit family of machines"
>> 484 select ARCH_SPARSEMEM_ENABLE
>> 485 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 486 select ARCH_MIGHT_HAVE_PC_SERIO
>> 487 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 488 select BOOT_ELF32
>> 489 select BOARD_SCACHE
>> 490 select CSRC_R4K
>> 491 select CEVT_R4K
>> 492 select CPU_HAS_WB
>> 493 select FORCE_PCI
>> 494 select ISA
>> 495 select I8259
>> 496 select IRQ_MIPS_CPU
>> 497 select NO_EXCEPT_FILL
>> 498 select NR_CPUS_DEFAULT_64
>> 499 select USE_GENERIC_EARLY_PRINTK_8250
>> 500 select PCI_DRIVERS_GENERIC
>> 501 select SYS_HAS_CPU_LOONGSON64
>> 502 select SYS_HAS_EARLY_PRINTK
>> 503 select SYS_SUPPORTS_SMP
>> 504 select SYS_SUPPORTS_HOTPLUG_CPU
>> 505 select SYS_SUPPORTS_NUMA
>> 506 select SYS_SUPPORTS_64BIT_KERNEL
>> 507 select SYS_SUPPORTS_HIGHMEM
>> 508 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 509 select SYS_SUPPORTS_ZBOOT
>> 510 select SYS_SUPPORTS_RELOCATABLE
>> 511 select ZONE_DMA32
>> 512 select COMMON_CLK
>> 513 select USE_OF
>> 514 select BUILTIN_DTB
>> 515 select PCI_HOST_GENERIC
>> 516 select HAVE_ARCH_NODEDATA_EXTENSION if NUMA
>> 517 help
>> 518 This enables the support of Loongson-2/3 family of machines.
>> 519
>> 520 Loongson-2 and Loongson-3 are 64-bit general-purpose processors with
>> 521 GS264/GS464/GS464E/GS464V microarchitecture (except old Loongson-2E
>> 522 and Loongson-2F which will be removed), developed by the Institute
>> 523 of Computing Technology (ICT), Chinese Academy of Sciences (CAS).
>> 524
>> 525 config MIPS_MALTA
>> 526 bool "MIPS Malta board"
>> 527 select ARCH_MAY_HAVE_PC_FDC
>> 528 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 529 select ARCH_MIGHT_HAVE_PC_SERIO
>> 530 select BOOT_ELF32
>> 531 select BOOT_RAW
>> 532 select BUILTIN_DTB
>> 533 select CEVT_R4K
>> 534 select CLKSRC_MIPS_GIC
>> 535 select COMMON_CLK
>> 536 select CSRC_R4K
>> 537 select DMA_NONCOHERENT
>> 538 select GENERIC_ISA_DMA
>> 539 select HAVE_PCSPKR_PLATFORM
>> 540 select HAVE_PCI
>> 541 select I8253
>> 542 select I8259
>> 543 select IRQ_MIPS_CPU
>> 544 select MIPS_BONITO64
>> 545 select MIPS_CPU_SCACHE
>> 546 select MIPS_GIC
>> 547 select MIPS_L1_CACHE_SHIFT_6
>> 548 select MIPS_MSC
>> 549 select PCI_GT64XXX_PCI0
>> 550 select SMP_UP if SMP
>> 551 select SWAP_IO_SPACE
>> 552 select SYS_HAS_CPU_MIPS32_R1
>> 553 select SYS_HAS_CPU_MIPS32_R2
>> 554 select SYS_HAS_CPU_MIPS32_R3_5
>> 555 select SYS_HAS_CPU_MIPS32_R5
>> 556 select SYS_HAS_CPU_MIPS32_R6
>> 557 select SYS_HAS_CPU_MIPS64_R1
>> 558 select SYS_HAS_CPU_MIPS64_R2
>> 559 select SYS_HAS_CPU_MIPS64_R6
>> 560 select SYS_HAS_CPU_NEVADA
>> 561 select SYS_HAS_CPU_RM7000
>> 562 select SYS_SUPPORTS_32BIT_KERNEL
>> 563 select SYS_SUPPORTS_64BIT_KERNEL
>> 564 select SYS_SUPPORTS_BIG_ENDIAN
>> 565 select SYS_SUPPORTS_HIGHMEM
>> 566 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 567 select SYS_SUPPORTS_MICROMIPS
>> 568 select SYS_SUPPORTS_MIPS16
>> 569 select SYS_SUPPORTS_MIPS_CMP
>> 570 select SYS_SUPPORTS_MIPS_CPS
>> 571 select SYS_SUPPORTS_MULTITHREADING
>> 572 select SYS_SUPPORTS_RELOCATABLE
>> 573 select SYS_SUPPORTS_SMARTMIPS
>> 574 select SYS_SUPPORTS_VPE_LOADER
>> 575 select SYS_SUPPORTS_ZBOOT
>> 576 select USE_OF
>> 577 select WAR_ICACHE_REFILLS
>> 578 select ZONE_DMA32 if 64BIT
>> 579 help
>> 580 This enables support for the MIPS Technologies Malta evaluation
>> 581 board.
>> 582
>> 583 config MACH_PIC32
>> 584 bool "Microchip PIC32 Family"
>> 585 help
>> 586 This enables support for the Microchip PIC32 family of platforms.
>> 587
>> 588 Microchip PIC32 is a family of general-purpose 32 bit MIPS core
>> 589 microcontrollers.
>> 590
>> 591 config MACH_VR41XX
>> 592 bool "NEC VR4100 series based machines"
>> 593 select CEVT_R4K
>> 594 select CSRC_R4K
>> 595 select SYS_HAS_CPU_VR41XX
>> 596 select SYS_SUPPORTS_MIPS16
>> 597 select GPIOLIB
>> 598
>> 599 config MACH_NINTENDO64
>> 600 bool "Nintendo 64 console"
>> 601 select CEVT_R4K
>> 602 select CSRC_R4K
>> 603 select SYS_HAS_CPU_R4300
>> 604 select SYS_SUPPORTS_BIG_ENDIAN
>> 605 select SYS_SUPPORTS_ZBOOT
>> 606 select SYS_SUPPORTS_32BIT_KERNEL
>> 607 select SYS_SUPPORTS_64BIT_KERNEL
>> 608 select DMA_NONCOHERENT
>> 609 select IRQ_MIPS_CPU
>> 610
>> 611 config RALINK
>> 612 bool "Ralink based machines"
>> 613 select CEVT_R4K
>> 614 select COMMON_CLK
>> 615 select CSRC_R4K
>> 616 select BOOT_RAW
>> 617 select DMA_NONCOHERENT
>> 618 select IRQ_MIPS_CPU
>> 619 select USE_OF
>> 620 select SYS_HAS_CPU_MIPS32_R1
>> 621 select SYS_HAS_CPU_MIPS32_R2
>> 622 select SYS_SUPPORTS_32BIT_KERNEL
>> 623 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 624 select SYS_SUPPORTS_MIPS16
>> 625 select SYS_SUPPORTS_ZBOOT
>> 626 select SYS_HAS_EARLY_PRINTK
>> 627 select ARCH_HAS_RESET_CONTROLLER
>> 628 select RESET_CONTROLLER
>> 629
>> 630 config MACH_REALTEK_RTL
>> 631 bool "Realtek RTL838x/RTL839x based machines"
>> 632 select MIPS_GENERIC
>> 633 select DMA_NONCOHERENT
>> 634 select IRQ_MIPS_CPU
>> 635 select CSRC_R4K
>> 636 select CEVT_R4K
>> 637 select SYS_HAS_CPU_MIPS32_R1
>> 638 select SYS_HAS_CPU_MIPS32_R2
>> 639 select SYS_SUPPORTS_BIG_ENDIAN
>> 640 select SYS_SUPPORTS_32BIT_KERNEL
>> 641 select SYS_SUPPORTS_MIPS16
>> 642 select SYS_SUPPORTS_MULTITHREADING
>> 643 select SYS_SUPPORTS_VPE_LOADER
>> 644 select BOOT_RAW
>> 645 select PINCTRL
>> 646 select USE_OF
>> 647
>> 648 config SGI_IP22
>> 649 bool "SGI IP22 (Indy/Indigo2)"
>> 650 select ARC_MEMORY
>> 651 select ARC_PROMLIB
>> 652 select FW_ARC
>> 653 select FW_ARC32
>> 654 select ARCH_MIGHT_HAVE_PC_SERIO
>> 655 select BOOT_ELF32
>> 656 select CEVT_R4K
>> 657 select CSRC_R4K
>> 658 select DEFAULT_SGI_PARTITION
>> 659 select DMA_NONCOHERENT
>> 660 select HAVE_EISA
>> 661 select I8253
>> 662 select I8259
>> 663 select IP22_CPU_SCACHE
>> 664 select IRQ_MIPS_CPU
>> 665 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 666 select SGI_HAS_I8042
>> 667 select SGI_HAS_INDYDOG
>> 668 select SGI_HAS_HAL2
>> 669 select SGI_HAS_SEEQ
>> 670 select SGI_HAS_WD93
>> 671 select SGI_HAS_ZILOG
>> 672 select SWAP_IO_SPACE
>> 673 select SYS_HAS_CPU_R4X00
>> 674 select SYS_HAS_CPU_R5000
>> 675 select SYS_HAS_EARLY_PRINTK
>> 676 select SYS_SUPPORTS_32BIT_KERNEL
>> 677 select SYS_SUPPORTS_64BIT_KERNEL
>> 678 select SYS_SUPPORTS_BIG_ENDIAN
>> 679 select WAR_R4600_V1_INDEX_ICACHEOP
>> 680 select WAR_R4600_V1_HIT_CACHEOP
>> 681 select WAR_R4600_V2_HIT_CACHEOP
>> 682 select MIPS_L1_CACHE_SHIFT_7
>> 683 help
>> 684 This are the SGI Indy, Challenge S and Indigo2, as well as certain
>> 685 OEM variants like the Tandem CMN B006S. To compile a Linux kernel
>> 686 that runs on these, say Y here.
>> 687
>> 688 config SGI_IP27
>> 689 bool "SGI IP27 (Origin200/2000)"
>> 690 select ARCH_HAS_PHYS_TO_DMA
>> 691 select ARCH_SPARSEMEM_ENABLE
>> 692 select FW_ARC
>> 693 select FW_ARC64
>> 694 select ARC_CMDLINE_ONLY
>> 695 select BOOT_ELF64
>> 696 select DEFAULT_SGI_PARTITION
>> 697 select FORCE_PCI
>> 698 select SYS_HAS_EARLY_PRINTK
>> 699 select HAVE_PCI
>> 700 select IRQ_MIPS_CPU
>> 701 select IRQ_DOMAIN_HIERARCHY
>> 702 select NR_CPUS_DEFAULT_64
>> 703 select PCI_DRIVERS_GENERIC
>> 704 select PCI_XTALK_BRIDGE
>> 705 select SYS_HAS_CPU_R10000
>> 706 select SYS_SUPPORTS_64BIT_KERNEL
>> 707 select SYS_SUPPORTS_BIG_ENDIAN
>> 708 select SYS_SUPPORTS_NUMA
>> 709 select SYS_SUPPORTS_SMP
>> 710 select WAR_R10000_LLSC
>> 711 select MIPS_L1_CACHE_SHIFT_7
>> 712 select NUMA
>> 713 select HAVE_ARCH_NODEDATA_EXTENSION
>> 714 help
>> 715 This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics
>> 716 workstations. To compile a Linux kernel that runs on these, say Y
>> 717 here.
>> 718
>> 719 config SGI_IP28
>> 720 bool "SGI IP28 (Indigo2 R10k)"
>> 721 select ARC_MEMORY
>> 722 select ARC_PROMLIB
>> 723 select FW_ARC
>> 724 select FW_ARC64
>> 725 select ARCH_MIGHT_HAVE_PC_SERIO
>> 726 select BOOT_ELF64
>> 727 select CEVT_R4K
>> 728 select CSRC_R4K
>> 729 select DEFAULT_SGI_PARTITION
>> 730 select DMA_NONCOHERENT
>> 731 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 732 select IRQ_MIPS_CPU
>> 733 select HAVE_EISA
>> 734 select I8253
>> 735 select I8259
>> 736 select SGI_HAS_I8042
>> 737 select SGI_HAS_INDYDOG
>> 738 select SGI_HAS_HAL2
>> 739 select SGI_HAS_SEEQ
>> 740 select SGI_HAS_WD93
>> 741 select SGI_HAS_ZILOG
>> 742 select SWAP_IO_SPACE
>> 743 select SYS_HAS_CPU_R10000
>> 744 select SYS_HAS_EARLY_PRINTK
>> 745 select SYS_SUPPORTS_64BIT_KERNEL
>> 746 select SYS_SUPPORTS_BIG_ENDIAN
>> 747 select WAR_R10000_LLSC
>> 748 select MIPS_L1_CACHE_SHIFT_7
>> 749 help
>> 750 This is the SGI Indigo2 with R10000 processor. To compile a Linux
>> 751 kernel that runs on these, say Y here.
>> 752
>> 753 config SGI_IP30
>> 754 bool "SGI IP30 (Octane/Octane2)"
>> 755 select ARCH_HAS_PHYS_TO_DMA
>> 756 select FW_ARC
>> 757 select FW_ARC64
>> 758 select BOOT_ELF64
>> 759 select CEVT_R4K
>> 760 select CSRC_R4K
>> 761 select FORCE_PCI
>> 762 select SYNC_R4K if SMP
>> 763 select ZONE_DMA32
>> 764 select HAVE_PCI
>> 765 select IRQ_MIPS_CPU
>> 766 select IRQ_DOMAIN_HIERARCHY
>> 767 select PCI_DRIVERS_GENERIC
>> 768 select PCI_XTALK_BRIDGE
>> 769 select SYS_HAS_EARLY_PRINTK
>> 770 select SYS_HAS_CPU_R10000
>> 771 select SYS_SUPPORTS_64BIT_KERNEL
>> 772 select SYS_SUPPORTS_BIG_ENDIAN
>> 773 select SYS_SUPPORTS_SMP
>> 774 select WAR_R10000_LLSC
>> 775 select MIPS_L1_CACHE_SHIFT_7
>> 776 select ARC_MEMORY
>> 777 help
>> 778 These are the SGI Octane and Octane2 graphics workstations. To
>> 779 compile a Linux kernel that runs on these, say Y here.
>> 780
>> 781 config SGI_IP32
>> 782 bool "SGI IP32 (O2)"
>> 783 select ARC_MEMORY
>> 784 select ARC_PROMLIB
>> 785 select ARCH_HAS_PHYS_TO_DMA
>> 786 select FW_ARC
>> 787 select FW_ARC32
>> 788 select BOOT_ELF32
>> 789 select CEVT_R4K
>> 790 select CSRC_R4K
>> 791 select DMA_NONCOHERENT
>> 792 select HAVE_PCI
>> 793 select IRQ_MIPS_CPU
>> 794 select R5000_CPU_SCACHE
>> 795 select RM7000_CPU_SCACHE
>> 796 select SYS_HAS_CPU_R5000
>> 797 select SYS_HAS_CPU_R10000 if BROKEN
>> 798 select SYS_HAS_CPU_RM7000
>> 799 select SYS_HAS_CPU_NEVADA
>> 800 select SYS_SUPPORTS_64BIT_KERNEL
>> 801 select SYS_SUPPORTS_BIG_ENDIAN
>> 802 select WAR_ICACHE_REFILLS
>> 803 help
>> 804 If you want this kernel to run on SGI O2 workstation, say Y here.
>> 805
>> 806 config SIBYTE_CRHINE
>> 807 bool "Sibyte BCM91120C-CRhine"
>> 808 select BOOT_ELF32
>> 809 select SIBYTE_BCM1120
>> 810 select SWAP_IO_SPACE
>> 811 select SYS_HAS_CPU_SB1
>> 812 select SYS_SUPPORTS_BIG_ENDIAN
>> 813 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 814
>> 815 config SIBYTE_CARMEL
>> 816 bool "Sibyte BCM91120x-Carmel"
>> 817 select BOOT_ELF32
>> 818 select SIBYTE_BCM1120
>> 819 select SWAP_IO_SPACE
>> 820 select SYS_HAS_CPU_SB1
>> 821 select SYS_SUPPORTS_BIG_ENDIAN
>> 822 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 823
>> 824 config SIBYTE_CRHONE
>> 825 bool "Sibyte BCM91125C-CRhone"
>> 826 select BOOT_ELF32
>> 827 select SIBYTE_BCM1125
>> 828 select SWAP_IO_SPACE
>> 829 select SYS_HAS_CPU_SB1
>> 830 select SYS_SUPPORTS_BIG_ENDIAN
>> 831 select SYS_SUPPORTS_HIGHMEM
>> 832 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 833
>> 834 config SIBYTE_RHONE
>> 835 bool "Sibyte BCM91125E-Rhone"
>> 836 select BOOT_ELF32
>> 837 select SIBYTE_BCM1125H
>> 838 select SWAP_IO_SPACE
>> 839 select SYS_HAS_CPU_SB1
>> 840 select SYS_SUPPORTS_BIG_ENDIAN
>> 841 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 842
>> 843 config SIBYTE_SWARM
>> 844 bool "Sibyte BCM91250A-SWARM"
>> 845 select BOOT_ELF32
>> 846 select HAVE_PATA_PLATFORM
>> 847 select SIBYTE_SB1250
>> 848 select SWAP_IO_SPACE
>> 849 select SYS_HAS_CPU_SB1
>> 850 select SYS_SUPPORTS_BIG_ENDIAN
>> 851 select SYS_SUPPORTS_HIGHMEM
>> 852 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 853 select ZONE_DMA32 if 64BIT
>> 854 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 855
>> 856 config SIBYTE_LITTLESUR
>> 857 bool "Sibyte BCM91250C2-LittleSur"
>> 858 select BOOT_ELF32
>> 859 select HAVE_PATA_PLATFORM
>> 860 select SIBYTE_SB1250
>> 861 select SWAP_IO_SPACE
>> 862 select SYS_HAS_CPU_SB1
>> 863 select SYS_SUPPORTS_BIG_ENDIAN
>> 864 select SYS_SUPPORTS_HIGHMEM
>> 865 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 866 select ZONE_DMA32 if 64BIT
>> 867
>> 868 config SIBYTE_SENTOSA
>> 869 bool "Sibyte BCM91250E-Sentosa"
>> 870 select BOOT_ELF32
>> 871 select SIBYTE_SB1250
>> 872 select SWAP_IO_SPACE
>> 873 select SYS_HAS_CPU_SB1
>> 874 select SYS_SUPPORTS_BIG_ENDIAN
>> 875 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 876 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 877
>> 878 config SIBYTE_BIGSUR
>> 879 bool "Sibyte BCM91480B-BigSur"
>> 880 select BOOT_ELF32
>> 881 select NR_CPUS_DEFAULT_4
>> 882 select SIBYTE_BCM1x80
>> 883 select SWAP_IO_SPACE
>> 884 select SYS_HAS_CPU_SB1
>> 885 select SYS_SUPPORTS_BIG_ENDIAN
>> 886 select SYS_SUPPORTS_HIGHMEM
>> 887 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 888 select ZONE_DMA32 if 64BIT
>> 889 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 890
>> 891 config SNI_RM
>> 892 bool "SNI RM200/300/400"
>> 893 select ARC_MEMORY
>> 894 select ARC_PROMLIB
>> 895 select FW_ARC if CPU_LITTLE_ENDIAN
>> 896 select FW_ARC32 if CPU_LITTLE_ENDIAN
>> 897 select FW_SNIPROM if CPU_BIG_ENDIAN
>> 898 select ARCH_MAY_HAVE_PC_FDC
>> 899 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 900 select ARCH_MIGHT_HAVE_PC_SERIO
>> 901 select BOOT_ELF32
>> 902 select CEVT_R4K
>> 903 select CSRC_R4K
>> 904 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 905 select DMA_NONCOHERENT
>> 906 select GENERIC_ISA_DMA
>> 907 select HAVE_EISA
>> 908 select HAVE_PCSPKR_PLATFORM
>> 909 select HAVE_PCI
>> 910 select IRQ_MIPS_CPU
>> 911 select I8253
>> 912 select I8259
>> 913 select ISA
>> 914 select MIPS_L1_CACHE_SHIFT_6
>> 915 select SWAP_IO_SPACE if CPU_BIG_ENDIAN
>> 916 select SYS_HAS_CPU_R4X00
>> 917 select SYS_HAS_CPU_R5000
>> 918 select SYS_HAS_CPU_R10000
>> 919 select R5000_CPU_SCACHE
>> 920 select SYS_HAS_EARLY_PRINTK
>> 921 select SYS_SUPPORTS_32BIT_KERNEL
>> 922 select SYS_SUPPORTS_64BIT_KERNEL
>> 923 select SYS_SUPPORTS_BIG_ENDIAN
>> 924 select SYS_SUPPORTS_HIGHMEM
>> 925 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 926 select WAR_R4600_V2_HIT_CACHEOP
>> 927 help
>> 928 The SNI RM200/300/400 are MIPS-based machines manufactured by
>> 929 Siemens Nixdorf Informationssysteme (SNI), parent company of Pyramid
>> 930 Technology and now in turn merged with Fujitsu. Say Y here to
>> 931 support this machine type.
>> 932
>> 933 config MACH_TX49XX
>> 934 bool "Toshiba TX49 series based machines"
>> 935 select WAR_TX49XX_ICACHE_INDEX_INV
>> 936
>> 937 config MIKROTIK_RB532
>> 938 bool "Mikrotik RB532 boards"
>> 939 select CEVT_R4K
>> 940 select CSRC_R4K
>> 941 select DMA_NONCOHERENT
>> 942 select HAVE_PCI
>> 943 select IRQ_MIPS_CPU
>> 944 select SYS_HAS_CPU_MIPS32_R1
>> 945 select SYS_SUPPORTS_32BIT_KERNEL
>> 946 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 947 select SWAP_IO_SPACE
>> 948 select BOOT_RAW
>> 949 select GPIOLIB
>> 950 select MIPS_L1_CACHE_SHIFT_4
>> 951 help
>> 952 Support the Mikrotik(tm) RouterBoard 532 series,
>> 953 based on the IDT RC32434 SoC.
>> 954
>> 955 config CAVIUM_OCTEON_SOC
>> 956 bool "Cavium Networks Octeon SoC based boards"
>> 957 select CEVT_R4K
>> 958 select ARCH_HAS_PHYS_TO_DMA
>> 959 select HAVE_RAPIDIO
>> 960 select PHYS_ADDR_T_64BIT
>> 961 select SYS_SUPPORTS_64BIT_KERNEL
>> 962 select SYS_SUPPORTS_BIG_ENDIAN
>> 963 select EDAC_SUPPORT
>> 964 select EDAC_ATOMIC_SCRUB
>> 965 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 966 select SYS_SUPPORTS_HOTPLUG_CPU if CPU_BIG_ENDIAN
>> 967 select SYS_HAS_EARLY_PRINTK
>> 968 select SYS_HAS_CPU_CAVIUM_OCTEON
>> 969 select HAVE_PCI
>> 970 select HAVE_PLAT_DELAY
>> 971 select HAVE_PLAT_FW_INIT_CMDLINE
>> 972 select HAVE_PLAT_MEMCPY
>> 973 select ZONE_DMA32
>> 974 select GPIOLIB
>> 975 select USE_OF
>> 976 select ARCH_SPARSEMEM_ENABLE
>> 977 select SYS_SUPPORTS_SMP
>> 978 select NR_CPUS_DEFAULT_64
>> 979 select MIPS_NR_CPU_NR_MAP_1024
>> 980 select BUILTIN_DTB
>> 981 select MTD
>> 982 select MTD_COMPLEX_MAPPINGS
>> 983 select SWIOTLB
>> 984 select SYS_SUPPORTS_RELOCATABLE
>> 985 help
>> 986 This option supports all of the Octeon reference boards from Cavium
>> 987 Networks. It builds a kernel that dynamically determines the Octeon
>> 988 CPU type and supports all known board reference implementations.
>> 989 Some of the supported boards are:
>> 990 EBT3000
>> 991 EBH3000
>> 992 EBH3100
>> 993 Thunder
>> 994 Kodama
>> 995 Hikari
>> 996 Say Y here for most Octeon reference boards.
>> 997
>> 998 endchoice
>> 999
>> 1000 source "arch/mips/alchemy/Kconfig"
>> 1001 source "arch/mips/ath25/Kconfig"
>> 1002 source "arch/mips/ath79/Kconfig"
>> 1003 source "arch/mips/bcm47xx/Kconfig"
>> 1004 source "arch/mips/bcm63xx/Kconfig"
>> 1005 source "arch/mips/bmips/Kconfig"
>> 1006 source "arch/mips/generic/Kconfig"
>> 1007 source "arch/mips/ingenic/Kconfig"
>> 1008 source "arch/mips/jazz/Kconfig"
>> 1009 source "arch/mips/lantiq/Kconfig"
>> 1010 source "arch/mips/pic32/Kconfig"
>> 1011 source "arch/mips/ralink/Kconfig"
>> 1012 source "arch/mips/sgi-ip27/Kconfig"
>> 1013 source "arch/mips/sibyte/Kconfig"
>> 1014 source "arch/mips/txx9/Kconfig"
>> 1015 source "arch/mips/vr41xx/Kconfig"
>> 1016 source "arch/mips/cavium-octeon/Kconfig"
>> 1017 source "arch/mips/loongson2ef/Kconfig"
>> 1018 source "arch/mips/loongson32/Kconfig"
>> 1019 source "arch/mips/loongson64/Kconfig"
>> 1020
>> 1021 endmenu
>> 1022
>> 1023 config GENERIC_HWEIGHT
>> 1024 bool
>> 1025 default y
>> 1026
>> 1027 config GENERIC_CALIBRATE_DELAY
>> 1028 bool
>> 1029 default y
>> 1030
>> 1031 config SCHED_OMIT_FRAME_POINTER
>> 1032 bool
>> 1033 default y
>> 1034
>> 1035 #
>> 1036 # Select some configuration options automatically based on user selections.
>> 1037 #
>> 1038 config FW_ARC
>> 1039 bool
>> 1040
>> 1041 config ARCH_MAY_HAVE_PC_FDC
>> 1042 bool
>> 1043
>> 1044 config BOOT_RAW
>> 1045 bool
>> 1046
>> 1047 config CEVT_BCM1480
>> 1048 bool
>> 1049
>> 1050 config CEVT_DS1287
>> 1051 bool
>> 1052
>> 1053 config CEVT_GT641XX
>> 1054 bool
>> 1055
>> 1056 config CEVT_R4K
>> 1057 bool
>> 1058
>> 1059 config CEVT_SB1250
>> 1060 bool
>> 1061
>> 1062 config CEVT_TXX9
>> 1063 bool
>> 1064
>> 1065 config CSRC_BCM1480
>> 1066 bool
>> 1067
>> 1068 config CSRC_IOASIC
>> 1069 bool
>> 1070
>> 1071 config CSRC_R4K
>> 1072 select CLOCKSOURCE_WATCHDOG if CPU_FREQ
>> 1073 bool
>> 1074
>> 1075 config CSRC_SB1250
>> 1076 bool
>> 1077
>> 1078 config MIPS_CLOCK_VSYSCALL
>> 1079 def_bool CSRC_R4K || CLKSRC_MIPS_GIC
>> 1080
>> 1081 config GPIO_TXX9
>> 1082 select GPIOLIB
>> 1083 bool
>> 1084
>> 1085 config FW_CFE
>> 1086 bool
120 1087
121 config ARCH_SUPPORTS_UPROBES 1088 config ARCH_SUPPORTS_UPROBES
122 def_bool y if !CPU_CK610 !! 1089 bool
>> 1090
>> 1091 config DMA_PERDEV_COHERENT
>> 1092 bool
>> 1093 select ARCH_HAS_SETUP_DMA_OPS
>> 1094 select DMA_NONCOHERENT
123 1095
124 config CPU_HAS_CACHEV2 !! 1096 config DMA_NONCOHERENT
125 bool 1097 bool
>> 1098 #
>> 1099 # MIPS allows mixing "slightly different" Cacheability and Coherency
>> 1100 # Attribute bits. It is believed that the uncached access through
>> 1101 # KSEG1 and the implementation specific "uncached accelerated" used
>> 1102 # by pgprot_writcombine can be mixed, and the latter sometimes provides
>> 1103 # significant advantages.
>> 1104 #
>> 1105 select ARCH_HAS_DMA_WRITE_COMBINE
>> 1106 select ARCH_HAS_DMA_PREP_COHERENT
>> 1107 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
>> 1108 select ARCH_HAS_DMA_SET_UNCACHED
>> 1109 select DMA_NONCOHERENT_MMAP
>> 1110 select NEED_DMA_MAP_STATE
126 1111
127 config CPU_HAS_FPUV2 !! 1112 config SYS_HAS_EARLY_PRINTK
128 bool 1113 bool
129 1114
130 config CPU_HAS_HILO !! 1115 config SYS_SUPPORTS_HOTPLUG_CPU
131 bool 1116 bool
132 1117
133 config CPU_HAS_TLBI !! 1118 config MIPS_BONITO64
134 bool 1119 bool
135 1120
136 config CPU_HAS_LDSTEX !! 1121 config MIPS_MSC
>> 1122 bool
>> 1123
>> 1124 config SYNC_R4K
>> 1125 bool
>> 1126
>> 1127 config NO_IOPORT_MAP
>> 1128 def_bool n
>> 1129
>> 1130 config GENERIC_CSUM
>> 1131 def_bool CPU_NO_LOAD_STORE_LR
>> 1132
>> 1133 config GENERIC_ISA_DMA
>> 1134 bool
>> 1135 select ZONE_DMA if GENERIC_ISA_DMA_SUPPORT_BROKEN=n
>> 1136 select ISA_DMA_API
>> 1137
>> 1138 config GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 1139 bool
>> 1140 select GENERIC_ISA_DMA
>> 1141
>> 1142 config HAVE_PLAT_DELAY
>> 1143 bool
>> 1144
>> 1145 config HAVE_PLAT_FW_INIT_CMDLINE
137 bool 1146 bool
138 help <<
139 For SMP, CPU needs "ldex&stex" instr <<
140 1147
141 config CPU_NEED_TLBSYNC !! 1148 config HAVE_PLAT_MEMCPY
142 bool 1149 bool
143 1150
144 config CPU_NEED_SOFTALIGN !! 1151 config ISA_DMA_API
145 bool 1152 bool
146 1153
147 config CPU_NO_USER_BKPT !! 1154 config SYS_SUPPORTS_RELOCATABLE
148 bool 1155 bool
149 help 1156 help
150 For abiv2 we couldn't use "trap 1" a !! 1157 Selected if the platform supports relocating the kernel.
151 abiv2 is 16/32bit instruction set an !! 1158 The platform must provide plat_get_fdt() if it selects CONFIG_USE_OF
152 So we need a 16bit instruction as us !! 1159 to allow access to command line and entropy sources.
153 instruction exception. !! 1160
154 In kernel we parse the *regs->pc to !! 1161 #
>> 1162 # Endianness selection. Sufficiently obscure so many users don't know what to
>> 1163 # answer,so we try hard to limit the available choices. Also the use of a
>> 1164 # choice statement should be more obvious to the user.
>> 1165 #
>> 1166 choice
>> 1167 prompt "Endianness selection"
>> 1168 help
>> 1169 Some MIPS machines can be configured for either little or big endian
>> 1170 byte order. These modes require different kernels and a different
>> 1171 Linux distribution. In general there is one preferred byteorder for a
>> 1172 particular system but some systems are just as commonly used in the
>> 1173 one or the other endianness.
>> 1174
>> 1175 config CPU_BIG_ENDIAN
>> 1176 bool "Big endian"
>> 1177 depends on SYS_SUPPORTS_BIG_ENDIAN
>> 1178
>> 1179 config CPU_LITTLE_ENDIAN
>> 1180 bool "Little endian"
>> 1181 depends on SYS_SUPPORTS_LITTLE_ENDIAN
155 1182
156 config GENERIC_CALIBRATE_DELAY !! 1183 endchoice
157 def_bool y <<
158 1184
159 config GENERIC_CSUM !! 1185 config EXPORT_UASM
160 def_bool y !! 1186 bool
161 1187
162 config GENERIC_HWEIGHT !! 1188 config SYS_SUPPORTS_APM_EMULATION
163 def_bool y !! 1189 bool
164 1190
165 config MMU !! 1191 config SYS_SUPPORTS_BIG_ENDIAN
166 def_bool y !! 1192 bool
167 1193
168 config STACKTRACE_SUPPORT !! 1194 config SYS_SUPPORTS_LITTLE_ENDIAN
169 def_bool y !! 1195 bool
170 1196
171 config TIME_LOW_RES !! 1197 config MIPS_HUGE_TLB_SUPPORT
172 def_bool y !! 1198 def_bool HUGETLB_PAGE || TRANSPARENT_HUGEPAGE
173 1199
174 config CPU_ASID_BITS !! 1200 config IRQ_MSP_SLP
175 int !! 1201 bool
176 default "8" if (CPU_CK610 || CPU_C <<
177 default "12" if (CPU_CK860) <<
178 1202
179 config L1_CACHE_SHIFT !! 1203 config IRQ_MSP_CIC
>> 1204 bool
>> 1205
>> 1206 config IRQ_TXX9
>> 1207 bool
>> 1208
>> 1209 config IRQ_GT641XX
>> 1210 bool
>> 1211
>> 1212 config PCI_GT64XXX_PCI0
>> 1213 bool
>> 1214
>> 1215 config PCI_XTALK_BRIDGE
>> 1216 bool
>> 1217
>> 1218 config NO_EXCEPT_FILL
>> 1219 bool
>> 1220
>> 1221 config MIPS_SPRAM
>> 1222 bool
>> 1223
>> 1224 config SWAP_IO_SPACE
>> 1225 bool
>> 1226
>> 1227 config SGI_HAS_INDYDOG
>> 1228 bool
>> 1229
>> 1230 config SGI_HAS_HAL2
>> 1231 bool
>> 1232
>> 1233 config SGI_HAS_SEEQ
>> 1234 bool
>> 1235
>> 1236 config SGI_HAS_WD93
>> 1237 bool
>> 1238
>> 1239 config SGI_HAS_ZILOG
>> 1240 bool
>> 1241
>> 1242 config SGI_HAS_I8042
>> 1243 bool
>> 1244
>> 1245 config DEFAULT_SGI_PARTITION
>> 1246 bool
>> 1247
>> 1248 config FW_ARC32
>> 1249 bool
>> 1250
>> 1251 config FW_SNIPROM
>> 1252 bool
>> 1253
>> 1254 config BOOT_ELF32
>> 1255 bool
>> 1256
>> 1257 config MIPS_L1_CACHE_SHIFT_4
>> 1258 bool
>> 1259
>> 1260 config MIPS_L1_CACHE_SHIFT_5
>> 1261 bool
>> 1262
>> 1263 config MIPS_L1_CACHE_SHIFT_6
>> 1264 bool
>> 1265
>> 1266 config MIPS_L1_CACHE_SHIFT_7
>> 1267 bool
>> 1268
>> 1269 config MIPS_L1_CACHE_SHIFT
180 int 1270 int
181 default "4" if (CPU_CK610) !! 1271 default "7" if MIPS_L1_CACHE_SHIFT_7
182 default "5" if (CPU_CK807 || CPU_C !! 1272 default "6" if MIPS_L1_CACHE_SHIFT_6
183 default "6" if (CPU_CK860) !! 1273 default "5" if MIPS_L1_CACHE_SHIFT_5
>> 1274 default "4" if MIPS_L1_CACHE_SHIFT_4
>> 1275 default "5"
184 1276
185 config ARCH_MMAP_RND_BITS_MIN !! 1277 config ARC_CMDLINE_ONLY
186 default 8 !! 1278 bool
187 1279
188 # max bits determined by the following formula !! 1280 config ARC_CONSOLE
189 # VA_BITS - PAGE_SHIFT - 3 !! 1281 bool "ARC console support"
190 config ARCH_MMAP_RND_BITS_MAX !! 1282 depends on SGI_IP22 || SGI_IP28 || (SNI_RM && CPU_LITTLE_ENDIAN)
191 default 17 !! 1283
>> 1284 config ARC_MEMORY
>> 1285 bool
192 1286
193 menu "Processor type and features" !! 1287 config ARC_PROMLIB
>> 1288 bool
>> 1289
>> 1290 config FW_ARC64
>> 1291 bool
>> 1292
>> 1293 config BOOT_ELF64
>> 1294 bool
>> 1295
>> 1296 menu "CPU selection"
194 1297
195 choice 1298 choice
196 prompt "CPU MODEL" !! 1299 prompt "CPU type"
197 default CPU_CK807 !! 1300 default CPU_R4X00
>> 1301
>> 1302 config CPU_LOONGSON64
>> 1303 bool "Loongson 64-bit CPU"
>> 1304 depends on SYS_HAS_CPU_LOONGSON64
>> 1305 select ARCH_HAS_PHYS_TO_DMA
>> 1306 select CPU_MIPSR2
>> 1307 select CPU_HAS_PREFETCH
>> 1308 select CPU_SUPPORTS_64BIT_KERNEL
>> 1309 select CPU_SUPPORTS_HIGHMEM
>> 1310 select CPU_SUPPORTS_HUGEPAGES
>> 1311 select CPU_SUPPORTS_MSA
>> 1312 select CPU_DIEI_BROKEN if !LOONGSON3_ENHANCEMENT
>> 1313 select CPU_MIPSR2_IRQ_VI
>> 1314 select WEAK_ORDERING
>> 1315 select WEAK_REORDERING_BEYOND_LLSC
>> 1316 select MIPS_ASID_BITS_VARIABLE
>> 1317 select MIPS_PGD_C0_CONTEXT
>> 1318 select MIPS_L1_CACHE_SHIFT_6
>> 1319 select MIPS_FP_SUPPORT
>> 1320 select GPIOLIB
>> 1321 select SWIOTLB
>> 1322 select HAVE_KVM
>> 1323 help
>> 1324 The Loongson GSx64(GS264/GS464/GS464E/GS464V) series of processor
>> 1325 cores implements the MIPS64R2 instruction set with many extensions,
>> 1326 including most 64-bit Loongson-2 (2H, 2K) and Loongson-3 (3A1000,
>> 1327 3B1000, 3B1500, 3A2000, 3A3000 and 3A4000) processors. However, old
>> 1328 Loongson-2E/2F is not covered here and will be removed in future.
>> 1329
>> 1330 config LOONGSON3_ENHANCEMENT
>> 1331 bool "New Loongson-3 CPU Enhancements"
>> 1332 default n
>> 1333 depends on CPU_LOONGSON64
>> 1334 help
>> 1335 New Loongson-3 cores (since Loongson-3A R2, as opposed to Loongson-3A
>> 1336 R1, Loongson-3B R1 and Loongson-3B R2) has many enhancements, such as
>> 1337 FTLB, L1-VCache, EI/DI/Wait/Prefetch instruction, DSP/DSPr2 ASE, User
>> 1338 Local register, Read-Inhibit/Execute-Inhibit, SFB (Store Fill Buffer),
>> 1339 Fast TLB refill support, etc.
>> 1340
>> 1341 This option enable those enhancements which are not probed at run
>> 1342 time. If you want a generic kernel to run on all Loongson 3 machines,
>> 1343 please say 'N' here. If you want a high-performance kernel to run on
>> 1344 new Loongson-3 machines only, please say 'Y' here.
>> 1345
>> 1346 config CPU_LOONGSON3_WORKAROUNDS
>> 1347 bool "Loongson-3 LLSC Workarounds"
>> 1348 default y if SMP
>> 1349 depends on CPU_LOONGSON64
>> 1350 help
>> 1351 Loongson-3 processors have the llsc issues which require workarounds.
>> 1352 Without workarounds the system may hang unexpectedly.
>> 1353
>> 1354 Say Y, unless you know what you are doing.
>> 1355
>> 1356 config CPU_LOONGSON3_CPUCFG_EMULATION
>> 1357 bool "Emulate the CPUCFG instruction on older Loongson cores"
>> 1358 default y
>> 1359 depends on CPU_LOONGSON64
>> 1360 help
>> 1361 Loongson-3A R4 and newer have the CPUCFG instruction available for
>> 1362 userland to query CPU capabilities, much like CPUID on x86. This
>> 1363 option provides emulation of the instruction on older Loongson
>> 1364 cores, back to Loongson-3A1000.
>> 1365
>> 1366 If unsure, please say Y.
>> 1367
>> 1368 config CPU_LOONGSON2E
>> 1369 bool "Loongson 2E"
>> 1370 depends on SYS_HAS_CPU_LOONGSON2E
>> 1371 select CPU_LOONGSON2EF
>> 1372 help
>> 1373 The Loongson 2E processor implements the MIPS III instruction set
>> 1374 with many extensions.
>> 1375
>> 1376 It has an internal FPGA northbridge, which is compatible to
>> 1377 bonito64.
>> 1378
>> 1379 config CPU_LOONGSON2F
>> 1380 bool "Loongson 2F"
>> 1381 depends on SYS_HAS_CPU_LOONGSON2F
>> 1382 select CPU_LOONGSON2EF
>> 1383 select GPIOLIB
>> 1384 help
>> 1385 The Loongson 2F processor implements the MIPS III instruction set
>> 1386 with many extensions.
>> 1387
>> 1388 Loongson2F have built-in DDR2 and PCIX controller. The PCIX controller
>> 1389 have a similar programming interface with FPGA northbridge used in
>> 1390 Loongson2E.
>> 1391
>> 1392 config CPU_LOONGSON1B
>> 1393 bool "Loongson 1B"
>> 1394 depends on SYS_HAS_CPU_LOONGSON1B
>> 1395 select CPU_LOONGSON32
>> 1396 select LEDS_GPIO_REGISTER
>> 1397 help
>> 1398 The Loongson 1B is a 32-bit SoC, which implements the MIPS32
>> 1399 Release 1 instruction set and part of the MIPS32 Release 2
>> 1400 instruction set.
>> 1401
>> 1402 config CPU_LOONGSON1C
>> 1403 bool "Loongson 1C"
>> 1404 depends on SYS_HAS_CPU_LOONGSON1C
>> 1405 select CPU_LOONGSON32
>> 1406 select LEDS_GPIO_REGISTER
>> 1407 help
>> 1408 The Loongson 1C is a 32-bit SoC, which implements the MIPS32
>> 1409 Release 1 instruction set and part of the MIPS32 Release 2
>> 1410 instruction set.
>> 1411
>> 1412 config CPU_MIPS32_R1
>> 1413 bool "MIPS32 Release 1"
>> 1414 depends on SYS_HAS_CPU_MIPS32_R1
>> 1415 select CPU_HAS_PREFETCH
>> 1416 select CPU_SUPPORTS_32BIT_KERNEL
>> 1417 select CPU_SUPPORTS_HIGHMEM
>> 1418 help
>> 1419 Choose this option to build a kernel for release 1 or later of the
>> 1420 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1421 MIPS processor are based on a MIPS32 processor. If you know the
>> 1422 specific type of processor in your system, choose those that one
>> 1423 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1424 Release 2 of the MIPS32 architecture is available since several
>> 1425 years so chances are you even have a MIPS32 Release 2 processor
>> 1426 in which case you should choose CPU_MIPS32_R2 instead for better
>> 1427 performance.
>> 1428
>> 1429 config CPU_MIPS32_R2
>> 1430 bool "MIPS32 Release 2"
>> 1431 depends on SYS_HAS_CPU_MIPS32_R2
>> 1432 select CPU_HAS_PREFETCH
>> 1433 select CPU_SUPPORTS_32BIT_KERNEL
>> 1434 select CPU_SUPPORTS_HIGHMEM
>> 1435 select CPU_SUPPORTS_MSA
>> 1436 select HAVE_KVM
>> 1437 help
>> 1438 Choose this option to build a kernel for release 2 or later of the
>> 1439 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1440 MIPS processor are based on a MIPS32 processor. If you know the
>> 1441 specific type of processor in your system, choose those that one
>> 1442 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1443
>> 1444 config CPU_MIPS32_R5
>> 1445 bool "MIPS32 Release 5"
>> 1446 depends on SYS_HAS_CPU_MIPS32_R5
>> 1447 select CPU_HAS_PREFETCH
>> 1448 select CPU_SUPPORTS_32BIT_KERNEL
>> 1449 select CPU_SUPPORTS_HIGHMEM
>> 1450 select CPU_SUPPORTS_MSA
>> 1451 select HAVE_KVM
>> 1452 select MIPS_O32_FP64_SUPPORT
>> 1453 help
>> 1454 Choose this option to build a kernel for release 5 or later of the
>> 1455 MIPS32 architecture. New MIPS processors, starting with the Warrior
>> 1456 family, are based on a MIPS32r5 processor. If you own an older
>> 1457 processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
>> 1458
>> 1459 config CPU_MIPS32_R6
>> 1460 bool "MIPS32 Release 6"
>> 1461 depends on SYS_HAS_CPU_MIPS32_R6
>> 1462 select CPU_HAS_PREFETCH
>> 1463 select CPU_NO_LOAD_STORE_LR
>> 1464 select CPU_SUPPORTS_32BIT_KERNEL
>> 1465 select CPU_SUPPORTS_HIGHMEM
>> 1466 select CPU_SUPPORTS_MSA
>> 1467 select HAVE_KVM
>> 1468 select MIPS_O32_FP64_SUPPORT
>> 1469 help
>> 1470 Choose this option to build a kernel for release 6 or later of the
>> 1471 MIPS32 architecture. New MIPS processors, starting with the Warrior
>> 1472 family, are based on a MIPS32r6 processor. If you own an older
>> 1473 processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
>> 1474
>> 1475 config CPU_MIPS64_R1
>> 1476 bool "MIPS64 Release 1"
>> 1477 depends on SYS_HAS_CPU_MIPS64_R1
>> 1478 select CPU_HAS_PREFETCH
>> 1479 select CPU_SUPPORTS_32BIT_KERNEL
>> 1480 select CPU_SUPPORTS_64BIT_KERNEL
>> 1481 select CPU_SUPPORTS_HIGHMEM
>> 1482 select CPU_SUPPORTS_HUGEPAGES
>> 1483 help
>> 1484 Choose this option to build a kernel for release 1 or later of the
>> 1485 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1486 MIPS processor are based on a MIPS64 processor. If you know the
>> 1487 specific type of processor in your system, choose those that one
>> 1488 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1489 Release 2 of the MIPS64 architecture is available since several
>> 1490 years so chances are you even have a MIPS64 Release 2 processor
>> 1491 in which case you should choose CPU_MIPS64_R2 instead for better
>> 1492 performance.
>> 1493
>> 1494 config CPU_MIPS64_R2
>> 1495 bool "MIPS64 Release 2"
>> 1496 depends on SYS_HAS_CPU_MIPS64_R2
>> 1497 select CPU_HAS_PREFETCH
>> 1498 select CPU_SUPPORTS_32BIT_KERNEL
>> 1499 select CPU_SUPPORTS_64BIT_KERNEL
>> 1500 select CPU_SUPPORTS_HIGHMEM
>> 1501 select CPU_SUPPORTS_HUGEPAGES
>> 1502 select CPU_SUPPORTS_MSA
>> 1503 select HAVE_KVM
>> 1504 help
>> 1505 Choose this option to build a kernel for release 2 or later of the
>> 1506 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1507 MIPS processor are based on a MIPS64 processor. If you know the
>> 1508 specific type of processor in your system, choose those that one
>> 1509 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1510
>> 1511 config CPU_MIPS64_R5
>> 1512 bool "MIPS64 Release 5"
>> 1513 depends on SYS_HAS_CPU_MIPS64_R5
>> 1514 select CPU_HAS_PREFETCH
>> 1515 select CPU_SUPPORTS_32BIT_KERNEL
>> 1516 select CPU_SUPPORTS_64BIT_KERNEL
>> 1517 select CPU_SUPPORTS_HIGHMEM
>> 1518 select CPU_SUPPORTS_HUGEPAGES
>> 1519 select CPU_SUPPORTS_MSA
>> 1520 select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
>> 1521 select HAVE_KVM
>> 1522 help
>> 1523 Choose this option to build a kernel for release 5 or later of the
>> 1524 MIPS64 architecture. This is a intermediate MIPS architecture
>> 1525 release partly implementing release 6 features. Though there is no
>> 1526 any hardware known to be based on this release.
>> 1527
>> 1528 config CPU_MIPS64_R6
>> 1529 bool "MIPS64 Release 6"
>> 1530 depends on SYS_HAS_CPU_MIPS64_R6
>> 1531 select CPU_HAS_PREFETCH
>> 1532 select CPU_NO_LOAD_STORE_LR
>> 1533 select CPU_SUPPORTS_32BIT_KERNEL
>> 1534 select CPU_SUPPORTS_64BIT_KERNEL
>> 1535 select CPU_SUPPORTS_HIGHMEM
>> 1536 select CPU_SUPPORTS_HUGEPAGES
>> 1537 select CPU_SUPPORTS_MSA
>> 1538 select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
>> 1539 select HAVE_KVM
>> 1540 help
>> 1541 Choose this option to build a kernel for release 6 or later of the
>> 1542 MIPS64 architecture. New MIPS processors, starting with the Warrior
>> 1543 family, are based on a MIPS64r6 processor. If you own an older
>> 1544 processor, you probably need to select MIPS64r1 or MIPS64r2 instead.
>> 1545
>> 1546 config CPU_P5600
>> 1547 bool "MIPS Warrior P5600"
>> 1548 depends on SYS_HAS_CPU_P5600
>> 1549 select CPU_HAS_PREFETCH
>> 1550 select CPU_SUPPORTS_32BIT_KERNEL
>> 1551 select CPU_SUPPORTS_HIGHMEM
>> 1552 select CPU_SUPPORTS_MSA
>> 1553 select CPU_SUPPORTS_CPUFREQ
>> 1554 select CPU_MIPSR2_IRQ_VI
>> 1555 select CPU_MIPSR2_IRQ_EI
>> 1556 select HAVE_KVM
>> 1557 select MIPS_O32_FP64_SUPPORT
>> 1558 help
>> 1559 Choose this option to build a kernel for MIPS Warrior P5600 CPU.
>> 1560 It's based on MIPS32r5 ISA with XPA, EVA, dual/quad issue exec pipes,
>> 1561 MMU with two-levels TLB, UCA, MSA, MDU core level features and system
>> 1562 level features like up to six P5600 calculation cores, CM2 with L2
>> 1563 cache, IOCU/IOMMU (though might be unused depending on the system-
>> 1564 specific IP core configuration), GIC, CPC, virtualisation module,
>> 1565 eJTAG and PDtrace.
>> 1566
>> 1567 config CPU_R3000
>> 1568 bool "R3000"
>> 1569 depends on SYS_HAS_CPU_R3000
>> 1570 select CPU_HAS_WB
>> 1571 select CPU_R3K_TLB
>> 1572 select CPU_SUPPORTS_32BIT_KERNEL
>> 1573 select CPU_SUPPORTS_HIGHMEM
>> 1574 help
>> 1575 Please make sure to pick the right CPU type. Linux/MIPS is not
>> 1576 designed to be generic, i.e. Kernels compiled for R3000 CPUs will
>> 1577 *not* work on R4000 machines and vice versa. However, since most
>> 1578 of the supported machines have an R4000 (or similar) CPU, R4x00
>> 1579 might be a safe bet. If the resulting kernel does not work,
>> 1580 try to recompile with R3000.
>> 1581
>> 1582 config CPU_VR41XX
>> 1583 bool "R41xx"
>> 1584 depends on SYS_HAS_CPU_VR41XX
>> 1585 select CPU_SUPPORTS_32BIT_KERNEL
>> 1586 select CPU_SUPPORTS_64BIT_KERNEL
>> 1587 help
>> 1588 The options selects support for the NEC VR4100 series of processors.
>> 1589 Only choose this option if you have one of these processors as a
>> 1590 kernel built with this option will not run on any other type of
>> 1591 processor or vice versa.
>> 1592
>> 1593 config CPU_R4300
>> 1594 bool "R4300"
>> 1595 depends on SYS_HAS_CPU_R4300
>> 1596 select CPU_SUPPORTS_32BIT_KERNEL
>> 1597 select CPU_SUPPORTS_64BIT_KERNEL
>> 1598 help
>> 1599 MIPS Technologies R4300-series processors.
>> 1600
>> 1601 config CPU_R4X00
>> 1602 bool "R4x00"
>> 1603 depends on SYS_HAS_CPU_R4X00
>> 1604 select CPU_SUPPORTS_32BIT_KERNEL
>> 1605 select CPU_SUPPORTS_64BIT_KERNEL
>> 1606 select CPU_SUPPORTS_HUGEPAGES
>> 1607 help
>> 1608 MIPS Technologies R4000-series processors other than 4300, including
>> 1609 the R4000, R4400, R4600, and 4700.
>> 1610
>> 1611 config CPU_TX49XX
>> 1612 bool "R49XX"
>> 1613 depends on SYS_HAS_CPU_TX49XX
>> 1614 select CPU_HAS_PREFETCH
>> 1615 select CPU_SUPPORTS_32BIT_KERNEL
>> 1616 select CPU_SUPPORTS_64BIT_KERNEL
>> 1617 select CPU_SUPPORTS_HUGEPAGES
>> 1618
>> 1619 config CPU_R5000
>> 1620 bool "R5000"
>> 1621 depends on SYS_HAS_CPU_R5000
>> 1622 select CPU_SUPPORTS_32BIT_KERNEL
>> 1623 select CPU_SUPPORTS_64BIT_KERNEL
>> 1624 select CPU_SUPPORTS_HUGEPAGES
>> 1625 help
>> 1626 MIPS Technologies R5000-series processors other than the Nevada.
>> 1627
>> 1628 config CPU_R5500
>> 1629 bool "R5500"
>> 1630 depends on SYS_HAS_CPU_R5500
>> 1631 select CPU_SUPPORTS_32BIT_KERNEL
>> 1632 select CPU_SUPPORTS_64BIT_KERNEL
>> 1633 select CPU_SUPPORTS_HUGEPAGES
>> 1634 help
>> 1635 NEC VR5500 and VR5500A series processors implement 64-bit MIPS IV
>> 1636 instruction set.
>> 1637
>> 1638 config CPU_NEVADA
>> 1639 bool "RM52xx"
>> 1640 depends on SYS_HAS_CPU_NEVADA
>> 1641 select CPU_SUPPORTS_32BIT_KERNEL
>> 1642 select CPU_SUPPORTS_64BIT_KERNEL
>> 1643 select CPU_SUPPORTS_HUGEPAGES
>> 1644 help
>> 1645 QED / PMC-Sierra RM52xx-series ("Nevada") processors.
>> 1646
>> 1647 config CPU_R10000
>> 1648 bool "R10000"
>> 1649 depends on SYS_HAS_CPU_R10000
>> 1650 select CPU_HAS_PREFETCH
>> 1651 select CPU_SUPPORTS_32BIT_KERNEL
>> 1652 select CPU_SUPPORTS_64BIT_KERNEL
>> 1653 select CPU_SUPPORTS_HIGHMEM
>> 1654 select CPU_SUPPORTS_HUGEPAGES
>> 1655 help
>> 1656 MIPS Technologies R10000-series processors.
>> 1657
>> 1658 config CPU_RM7000
>> 1659 bool "RM7000"
>> 1660 depends on SYS_HAS_CPU_RM7000
>> 1661 select CPU_HAS_PREFETCH
>> 1662 select CPU_SUPPORTS_32BIT_KERNEL
>> 1663 select CPU_SUPPORTS_64BIT_KERNEL
>> 1664 select CPU_SUPPORTS_HIGHMEM
>> 1665 select CPU_SUPPORTS_HUGEPAGES
>> 1666
>> 1667 config CPU_SB1
>> 1668 bool "SB1"
>> 1669 depends on SYS_HAS_CPU_SB1
>> 1670 select CPU_SUPPORTS_32BIT_KERNEL
>> 1671 select CPU_SUPPORTS_64BIT_KERNEL
>> 1672 select CPU_SUPPORTS_HIGHMEM
>> 1673 select CPU_SUPPORTS_HUGEPAGES
>> 1674 select WEAK_ORDERING
>> 1675
>> 1676 config CPU_CAVIUM_OCTEON
>> 1677 bool "Cavium Octeon processor"
>> 1678 depends on SYS_HAS_CPU_CAVIUM_OCTEON
>> 1679 select CPU_HAS_PREFETCH
>> 1680 select CPU_SUPPORTS_64BIT_KERNEL
>> 1681 select WEAK_ORDERING
>> 1682 select CPU_SUPPORTS_HIGHMEM
>> 1683 select CPU_SUPPORTS_HUGEPAGES
>> 1684 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1685 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1686 select MIPS_L1_CACHE_SHIFT_7
>> 1687 select HAVE_KVM
>> 1688 help
>> 1689 The Cavium Octeon processor is a highly integrated chip containing
>> 1690 many ethernet hardware widgets for networking tasks. The processor
>> 1691 can have up to 16 Mips64v2 cores and 8 integrated gigabit ethernets.
>> 1692 Full details can be found at http://www.caviumnetworks.com.
>> 1693
>> 1694 config CPU_BMIPS
>> 1695 bool "Broadcom BMIPS"
>> 1696 depends on SYS_HAS_CPU_BMIPS
>> 1697 select CPU_MIPS32
>> 1698 select CPU_BMIPS32_3300 if SYS_HAS_CPU_BMIPS32_3300
>> 1699 select CPU_BMIPS4350 if SYS_HAS_CPU_BMIPS4350
>> 1700 select CPU_BMIPS4380 if SYS_HAS_CPU_BMIPS4380
>> 1701 select CPU_BMIPS5000 if SYS_HAS_CPU_BMIPS5000
>> 1702 select CPU_SUPPORTS_32BIT_KERNEL
>> 1703 select DMA_NONCOHERENT
>> 1704 select IRQ_MIPS_CPU
>> 1705 select SWAP_IO_SPACE
>> 1706 select WEAK_ORDERING
>> 1707 select CPU_SUPPORTS_HIGHMEM
>> 1708 select CPU_HAS_PREFETCH
>> 1709 select CPU_SUPPORTS_CPUFREQ
>> 1710 select MIPS_EXTERNAL_TIMER
>> 1711 select GENERIC_IRQ_MIGRATION if HOTPLUG_CPU
>> 1712 help
>> 1713 Support for BMIPS32/3300/4350/4380 and BMIPS5000 processors.
198 1714
199 config CPU_CK610 <<
200 bool "CSKY CPU ck610" <<
201 select CPU_NEED_TLBSYNC <<
202 select CPU_NEED_SOFTALIGN <<
203 select CPU_NO_USER_BKPT <<
204 <<
205 config CPU_CK810 <<
206 bool "CSKY CPU ck810" <<
207 select CPU_HAS_HILO <<
208 select CPU_NEED_TLBSYNC <<
209 <<
210 config CPU_CK807 <<
211 bool "CSKY CPU ck807" <<
212 select CPU_HAS_HILO <<
213 <<
214 config CPU_CK860 <<
215 bool "CSKY CPU ck860" <<
216 select CPU_HAS_TLBI <<
217 select CPU_HAS_CACHEV2 <<
218 select CPU_HAS_LDSTEX <<
219 select CPU_HAS_FPUV2 <<
220 endchoice 1715 endchoice
221 1716
>> 1717 config CPU_MIPS32_3_5_FEATURES
>> 1718 bool "MIPS32 Release 3.5 Features"
>> 1719 depends on SYS_HAS_CPU_MIPS32_R3_5
>> 1720 depends on CPU_MIPS32_R2 || CPU_MIPS32_R5 || CPU_MIPS32_R6 || \
>> 1721 CPU_P5600
>> 1722 help
>> 1723 Choose this option to build a kernel for release 2 or later of the
>> 1724 MIPS32 architecture including features from the 3.5 release such as
>> 1725 support for Enhanced Virtual Addressing (EVA).
>> 1726
>> 1727 config CPU_MIPS32_3_5_EVA
>> 1728 bool "Enhanced Virtual Addressing (EVA)"
>> 1729 depends on CPU_MIPS32_3_5_FEATURES
>> 1730 select EVA
>> 1731 default y
>> 1732 help
>> 1733 Choose this option if you want to enable the Enhanced Virtual
>> 1734 Addressing (EVA) on your MIPS32 core (such as proAptiv).
>> 1735 One of its primary benefits is an increase in the maximum size
>> 1736 of lowmem (up to 3GB). If unsure, say 'N' here.
>> 1737
>> 1738 config CPU_MIPS32_R5_FEATURES
>> 1739 bool "MIPS32 Release 5 Features"
>> 1740 depends on SYS_HAS_CPU_MIPS32_R5
>> 1741 depends on CPU_MIPS32_R2 || CPU_MIPS32_R5 || CPU_P5600
>> 1742 help
>> 1743 Choose this option to build a kernel for release 2 or later of the
>> 1744 MIPS32 architecture including features from release 5 such as
>> 1745 support for Extended Physical Addressing (XPA).
>> 1746
>> 1747 config CPU_MIPS32_R5_XPA
>> 1748 bool "Extended Physical Addressing (XPA)"
>> 1749 depends on CPU_MIPS32_R5_FEATURES
>> 1750 depends on !EVA
>> 1751 depends on !PAGE_SIZE_4KB
>> 1752 depends on SYS_SUPPORTS_HIGHMEM
>> 1753 select XPA
>> 1754 select HIGHMEM
>> 1755 select PHYS_ADDR_T_64BIT
>> 1756 default n
>> 1757 help
>> 1758 Choose this option if you want to enable the Extended Physical
>> 1759 Addressing (XPA) on your MIPS32 core (such as P5600 series). The
>> 1760 benefit is to increase physical addressing equal to or greater
>> 1761 than 40 bits. Note that this has the side effect of turning on
>> 1762 64-bit addressing which in turn makes the PTEs 64-bit in size.
>> 1763 If unsure, say 'N' here.
>> 1764
>> 1765 if CPU_LOONGSON2F
>> 1766 config CPU_NOP_WORKAROUNDS
>> 1767 bool
>> 1768
>> 1769 config CPU_JUMP_WORKAROUNDS
>> 1770 bool
>> 1771
>> 1772 config CPU_LOONGSON2F_WORKAROUNDS
>> 1773 bool "Loongson 2F Workarounds"
>> 1774 default y
>> 1775 select CPU_NOP_WORKAROUNDS
>> 1776 select CPU_JUMP_WORKAROUNDS
>> 1777 help
>> 1778 Loongson 2F01 / 2F02 processors have the NOP & JUMP issues which
>> 1779 require workarounds. Without workarounds the system may hang
>> 1780 unexpectedly. For more information please refer to the gas
>> 1781 -mfix-loongson2f-nop and -mfix-loongson2f-jump options.
>> 1782
>> 1783 Loongson 2F03 and later have fixed these issues and no workarounds
>> 1784 are needed. The workarounds have no significant side effect on them
>> 1785 but may decrease the performance of the system so this option should
>> 1786 be disabled unless the kernel is intended to be run on 2F01 or 2F02
>> 1787 systems.
>> 1788
>> 1789 If unsure, please say Y.
>> 1790 endif # CPU_LOONGSON2F
>> 1791
>> 1792 config SYS_SUPPORTS_ZBOOT
>> 1793 bool
>> 1794 select HAVE_KERNEL_GZIP
>> 1795 select HAVE_KERNEL_BZIP2
>> 1796 select HAVE_KERNEL_LZ4
>> 1797 select HAVE_KERNEL_LZMA
>> 1798 select HAVE_KERNEL_LZO
>> 1799 select HAVE_KERNEL_XZ
>> 1800 select HAVE_KERNEL_ZSTD
>> 1801
>> 1802 config SYS_SUPPORTS_ZBOOT_UART16550
>> 1803 bool
>> 1804 select SYS_SUPPORTS_ZBOOT
>> 1805
>> 1806 config SYS_SUPPORTS_ZBOOT_UART_PROM
>> 1807 bool
>> 1808 select SYS_SUPPORTS_ZBOOT
>> 1809
>> 1810 config CPU_LOONGSON2EF
>> 1811 bool
>> 1812 select CPU_SUPPORTS_32BIT_KERNEL
>> 1813 select CPU_SUPPORTS_64BIT_KERNEL
>> 1814 select CPU_SUPPORTS_HIGHMEM
>> 1815 select CPU_SUPPORTS_HUGEPAGES
>> 1816 select ARCH_HAS_PHYS_TO_DMA
>> 1817
>> 1818 config CPU_LOONGSON32
>> 1819 bool
>> 1820 select CPU_MIPS32
>> 1821 select CPU_MIPSR2
>> 1822 select CPU_HAS_PREFETCH
>> 1823 select CPU_SUPPORTS_32BIT_KERNEL
>> 1824 select CPU_SUPPORTS_HIGHMEM
>> 1825 select CPU_SUPPORTS_CPUFREQ
>> 1826
>> 1827 config CPU_BMIPS32_3300
>> 1828 select SMP_UP if SMP
>> 1829 bool
>> 1830
>> 1831 config CPU_BMIPS4350
>> 1832 bool
>> 1833 select SYS_SUPPORTS_SMP
>> 1834 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1835
>> 1836 config CPU_BMIPS4380
>> 1837 bool
>> 1838 select MIPS_L1_CACHE_SHIFT_6
>> 1839 select SYS_SUPPORTS_SMP
>> 1840 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1841 select CPU_HAS_RIXI
>> 1842
>> 1843 config CPU_BMIPS5000
>> 1844 bool
>> 1845 select MIPS_CPU_SCACHE
>> 1846 select MIPS_L1_CACHE_SHIFT_7
>> 1847 select SYS_SUPPORTS_SMP
>> 1848 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1849 select CPU_HAS_RIXI
>> 1850
>> 1851 config SYS_HAS_CPU_LOONGSON64
>> 1852 bool
>> 1853 select CPU_SUPPORTS_CPUFREQ
>> 1854 select CPU_HAS_RIXI
>> 1855
>> 1856 config SYS_HAS_CPU_LOONGSON2E
>> 1857 bool
>> 1858
>> 1859 config SYS_HAS_CPU_LOONGSON2F
>> 1860 bool
>> 1861 select CPU_SUPPORTS_CPUFREQ
>> 1862 select CPU_SUPPORTS_ADDRWINCFG if 64BIT
>> 1863
>> 1864 config SYS_HAS_CPU_LOONGSON1B
>> 1865 bool
>> 1866
>> 1867 config SYS_HAS_CPU_LOONGSON1C
>> 1868 bool
>> 1869
>> 1870 config SYS_HAS_CPU_MIPS32_R1
>> 1871 bool
>> 1872
>> 1873 config SYS_HAS_CPU_MIPS32_R2
>> 1874 bool
>> 1875
>> 1876 config SYS_HAS_CPU_MIPS32_R3_5
>> 1877 bool
>> 1878
>> 1879 config SYS_HAS_CPU_MIPS32_R5
>> 1880 bool
>> 1881 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
>> 1882
>> 1883 config SYS_HAS_CPU_MIPS32_R6
>> 1884 bool
>> 1885 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
>> 1886
>> 1887 config SYS_HAS_CPU_MIPS64_R1
>> 1888 bool
>> 1889
>> 1890 config SYS_HAS_CPU_MIPS64_R2
>> 1891 bool
>> 1892
>> 1893 config SYS_HAS_CPU_MIPS64_R5
>> 1894 bool
>> 1895 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
>> 1896
>> 1897 config SYS_HAS_CPU_MIPS64_R6
>> 1898 bool
>> 1899 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
>> 1900
>> 1901 config SYS_HAS_CPU_P5600
>> 1902 bool
>> 1903 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
>> 1904
>> 1905 config SYS_HAS_CPU_R3000
>> 1906 bool
>> 1907
>> 1908 config SYS_HAS_CPU_VR41XX
>> 1909 bool
>> 1910
>> 1911 config SYS_HAS_CPU_R4300
>> 1912 bool
>> 1913
>> 1914 config SYS_HAS_CPU_R4X00
>> 1915 bool
>> 1916
>> 1917 config SYS_HAS_CPU_TX49XX
>> 1918 bool
>> 1919
>> 1920 config SYS_HAS_CPU_R5000
>> 1921 bool
>> 1922
>> 1923 config SYS_HAS_CPU_R5500
>> 1924 bool
>> 1925
>> 1926 config SYS_HAS_CPU_NEVADA
>> 1927 bool
>> 1928
>> 1929 config SYS_HAS_CPU_R10000
>> 1930 bool
>> 1931 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
>> 1932
>> 1933 config SYS_HAS_CPU_RM7000
>> 1934 bool
>> 1935
>> 1936 config SYS_HAS_CPU_SB1
>> 1937 bool
>> 1938
>> 1939 config SYS_HAS_CPU_CAVIUM_OCTEON
>> 1940 bool
>> 1941
>> 1942 config SYS_HAS_CPU_BMIPS
>> 1943 bool
>> 1944
>> 1945 config SYS_HAS_CPU_BMIPS32_3300
>> 1946 bool
>> 1947 select SYS_HAS_CPU_BMIPS
>> 1948
>> 1949 config SYS_HAS_CPU_BMIPS4350
>> 1950 bool
>> 1951 select SYS_HAS_CPU_BMIPS
>> 1952
>> 1953 config SYS_HAS_CPU_BMIPS4380
>> 1954 bool
>> 1955 select SYS_HAS_CPU_BMIPS
>> 1956
>> 1957 config SYS_HAS_CPU_BMIPS5000
>> 1958 bool
>> 1959 select SYS_HAS_CPU_BMIPS
>> 1960 select ARCH_HAS_SYNC_DMA_FOR_CPU
>> 1961
>> 1962 #
>> 1963 # CPU may reorder R->R, R->W, W->R, W->W
>> 1964 # Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC
>> 1965 #
>> 1966 config WEAK_ORDERING
>> 1967 bool
>> 1968
>> 1969 #
>> 1970 # CPU may reorder reads and writes beyond LL/SC
>> 1971 # CPU may reorder R->LL, R->LL, W->LL, W->LL, R->SC, R->SC, W->SC, W->SC
>> 1972 #
>> 1973 config WEAK_REORDERING_BEYOND_LLSC
>> 1974 bool
>> 1975 endmenu
>> 1976
>> 1977 #
>> 1978 # These two indicate any level of the MIPS32 and MIPS64 architecture
>> 1979 #
>> 1980 config CPU_MIPS32
>> 1981 bool
>> 1982 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R5 || \
>> 1983 CPU_MIPS32_R6 || CPU_P5600
>> 1984
>> 1985 config CPU_MIPS64
>> 1986 bool
>> 1987 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R5 || \
>> 1988 CPU_MIPS64_R6 || CPU_LOONGSON64 || CPU_CAVIUM_OCTEON
>> 1989
>> 1990 #
>> 1991 # These indicate the revision of the architecture
>> 1992 #
>> 1993 config CPU_MIPSR1
>> 1994 bool
>> 1995 default y if CPU_MIPS32_R1 || CPU_MIPS64_R1
>> 1996
>> 1997 config CPU_MIPSR2
>> 1998 bool
>> 1999 default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_CAVIUM_OCTEON
>> 2000 select CPU_HAS_RIXI
>> 2001 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
>> 2002 select MIPS_SPRAM
>> 2003
>> 2004 config CPU_MIPSR5
>> 2005 bool
>> 2006 default y if CPU_MIPS32_R5 || CPU_MIPS64_R5 || CPU_P5600
>> 2007 select CPU_HAS_RIXI
>> 2008 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
>> 2009 select MIPS_SPRAM
>> 2010
>> 2011 config CPU_MIPSR6
>> 2012 bool
>> 2013 default y if CPU_MIPS32_R6 || CPU_MIPS64_R6
>> 2014 select CPU_HAS_RIXI
>> 2015 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
>> 2016 select HAVE_ARCH_BITREVERSE
>> 2017 select MIPS_ASID_BITS_VARIABLE
>> 2018 select MIPS_CRC_SUPPORT
>> 2019 select MIPS_SPRAM
>> 2020
>> 2021 config TARGET_ISA_REV
>> 2022 int
>> 2023 default 1 if CPU_MIPSR1
>> 2024 default 2 if CPU_MIPSR2
>> 2025 default 5 if CPU_MIPSR5
>> 2026 default 6 if CPU_MIPSR6
>> 2027 default 0
>> 2028 help
>> 2029 Reflects the ISA revision being targeted by the kernel build. This
>> 2030 is effectively the Kconfig equivalent of MIPS_ISA_REV.
>> 2031
>> 2032 config EVA
>> 2033 bool
>> 2034
>> 2035 config XPA
>> 2036 bool
>> 2037
>> 2038 config SYS_SUPPORTS_32BIT_KERNEL
>> 2039 bool
>> 2040 config SYS_SUPPORTS_64BIT_KERNEL
>> 2041 bool
>> 2042 config CPU_SUPPORTS_32BIT_KERNEL
>> 2043 bool
>> 2044 config CPU_SUPPORTS_64BIT_KERNEL
>> 2045 bool
>> 2046 config CPU_SUPPORTS_CPUFREQ
>> 2047 bool
>> 2048 config CPU_SUPPORTS_ADDRWINCFG
>> 2049 bool
>> 2050 config CPU_SUPPORTS_HUGEPAGES
>> 2051 bool
>> 2052 depends on !(32BIT && (PHYS_ADDR_T_64BIT || EVA))
>> 2053 config MIPS_PGD_C0_CONTEXT
>> 2054 bool
>> 2055 depends on 64BIT
>> 2056 default y if (CPU_MIPSR2 || CPU_MIPSR6)
>> 2057
>> 2058 #
>> 2059 # Set to y for ptrace access to watch registers.
>> 2060 #
>> 2061 config HARDWARE_WATCHPOINTS
>> 2062 bool
>> 2063 default y if CPU_MIPSR1 || CPU_MIPSR2 || CPU_MIPSR6
>> 2064
>> 2065 menu "Kernel type"
>> 2066
222 choice 2067 choice
223 prompt "PAGE OFFSET" !! 2068 prompt "Kernel code model"
224 default PAGE_OFFSET_80000000 !! 2069 help
>> 2070 You should only select this option if you have a workload that
>> 2071 actually benefits from 64-bit processing or if your machine has
>> 2072 large memory. You will only be presented a single option in this
>> 2073 menu if your system does not support both 32-bit and 64-bit kernels.
>> 2074
>> 2075 config 32BIT
>> 2076 bool "32-bit kernel"
>> 2077 depends on CPU_SUPPORTS_32BIT_KERNEL && SYS_SUPPORTS_32BIT_KERNEL
>> 2078 select TRAD_SIGNALS
>> 2079 help
>> 2080 Select this option if you want to build a 32-bit kernel.
225 2081
226 config PAGE_OFFSET_80000000 !! 2082 config 64BIT
227 bool "PAGE OFFSET 2G (user:kernel = 2: !! 2083 bool "64-bit kernel"
>> 2084 depends on CPU_SUPPORTS_64BIT_KERNEL && SYS_SUPPORTS_64BIT_KERNEL
>> 2085 help
>> 2086 Select this option if you want to build a 64-bit kernel.
228 2087
229 config PAGE_OFFSET_A0000000 <<
230 bool "PAGE OFFSET 2.5G (user:kernel = <<
231 endchoice 2088 endchoice
232 2089
233 config PAGE_OFFSET !! 2090 config MIPS_VA_BITS_48
234 hex !! 2091 bool "48 bits virtual memory"
235 default 0x80000000 if PAGE_OFFSET_8000 !! 2092 depends on 64BIT
236 default 0xa0000000 if PAGE_OFFSET_A000 !! 2093 help
237 choice !! 2094 Support a maximum at least 48 bits of application virtual
>> 2095 memory. Default is 40 bits or less, depending on the CPU.
>> 2096 For page sizes 16k and above, this option results in a small
>> 2097 memory overhead for page tables. For 4k page size, a fourth
>> 2098 level of page tables is added which imposes both a memory
>> 2099 overhead as well as slower TLB fault handling.
>> 2100
>> 2101 If unsure, say N.
>> 2102
>> 2103 config ZBOOT_LOAD_ADDRESS
>> 2104 hex "Compressed kernel load address"
>> 2105 default 0xffffffff80400000 if BCM47XX
>> 2106 default 0x0
>> 2107 depends on SYS_SUPPORTS_ZBOOT
>> 2108 help
>> 2109 The address to load compressed kernel, aka vmlinuz.
238 2110
239 prompt "C-SKY PMU type" !! 2111 This is only used if non-zero.
240 depends on PERF_EVENTS <<
241 depends on CPU_CK807 || CPU_CK810 || C <<
242 2112
243 config CPU_PMU_NONE !! 2113 choice
244 bool "None" !! 2114 prompt "Kernel page size"
>> 2115 default PAGE_SIZE_4KB
245 2116
246 config CSKY_PMU_V1 !! 2117 config PAGE_SIZE_4KB
247 bool "Performance Monitoring Unit Ver. !! 2118 bool "4kB"
>> 2119 depends on !CPU_LOONGSON2EF && !CPU_LOONGSON64
>> 2120 help
>> 2121 This option select the standard 4kB Linux page size. On some
>> 2122 R3000-family processors this is the only available page size. Using
>> 2123 4kB page size will minimize memory consumption and is therefore
>> 2124 recommended for low memory systems.
>> 2125
>> 2126 config PAGE_SIZE_8KB
>> 2127 bool "8kB"
>> 2128 depends on CPU_CAVIUM_OCTEON
>> 2129 depends on !MIPS_VA_BITS_48
>> 2130 help
>> 2131 Using 8kB page size will result in higher performance kernel at
>> 2132 the price of higher memory consumption. This option is available
>> 2133 only on cnMIPS processors. Note that you will need a suitable Linux
>> 2134 distribution to support this.
>> 2135
>> 2136 config PAGE_SIZE_16KB
>> 2137 bool "16kB"
>> 2138 depends on !CPU_R3000
>> 2139 help
>> 2140 Using 16kB page size will result in higher performance kernel at
>> 2141 the price of higher memory consumption. This option is available on
>> 2142 all non-R3000 family processors. Note that you will need a suitable
>> 2143 Linux distribution to support this.
>> 2144
>> 2145 config PAGE_SIZE_32KB
>> 2146 bool "32kB"
>> 2147 depends on CPU_CAVIUM_OCTEON
>> 2148 depends on !MIPS_VA_BITS_48
>> 2149 help
>> 2150 Using 32kB page size will result in higher performance kernel at
>> 2151 the price of higher memory consumption. This option is available
>> 2152 only on cnMIPS cores. Note that you will need a suitable Linux
>> 2153 distribution to support this.
>> 2154
>> 2155 config PAGE_SIZE_64KB
>> 2156 bool "64kB"
>> 2157 depends on !CPU_R3000
>> 2158 help
>> 2159 Using 64kB page size will result in higher performance kernel at
>> 2160 the price of higher memory consumption. This option is available on
>> 2161 all non-R3000 family processor. Not that at the time of this
>> 2162 writing this option is still high experimental.
248 2163
249 endchoice 2164 endchoice
250 2165
>> 2166 config FORCE_MAX_ZONEORDER
>> 2167 int "Maximum zone order"
>> 2168 range 14 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
>> 2169 default "14" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
>> 2170 range 13 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
>> 2171 default "13" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
>> 2172 range 12 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
>> 2173 default "12" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
>> 2174 range 0 64
>> 2175 default "11"
>> 2176 help
>> 2177 The kernel memory allocator divides physically contiguous memory
>> 2178 blocks into "zones", where each zone is a power of two number of
>> 2179 pages. This option selects the largest power of two that the kernel
>> 2180 keeps in the memory allocator. If you need to allocate very large
>> 2181 blocks of physically contiguous memory, then you may need to
>> 2182 increase this value.
>> 2183
>> 2184 This config option is actually maximum order plus one. For example,
>> 2185 a value of 11 means that the largest free memory block is 2^10 pages.
>> 2186
>> 2187 The page size is not necessarily 4KB. Keep this in mind
>> 2188 when choosing a value for this option.
>> 2189
>> 2190 config BOARD_SCACHE
>> 2191 bool
>> 2192
>> 2193 config IP22_CPU_SCACHE
>> 2194 bool
>> 2195 select BOARD_SCACHE
>> 2196
>> 2197 #
>> 2198 # Support for a MIPS32 / MIPS64 style S-caches
>> 2199 #
>> 2200 config MIPS_CPU_SCACHE
>> 2201 bool
>> 2202 select BOARD_SCACHE
>> 2203
>> 2204 config R5000_CPU_SCACHE
>> 2205 bool
>> 2206 select BOARD_SCACHE
>> 2207
>> 2208 config RM7000_CPU_SCACHE
>> 2209 bool
>> 2210 select BOARD_SCACHE
>> 2211
>> 2212 config SIBYTE_DMA_PAGEOPS
>> 2213 bool "Use DMA to clear/copy pages"
>> 2214 depends on CPU_SB1
>> 2215 help
>> 2216 Instead of using the CPU to zero and copy pages, use a Data Mover
>> 2217 channel. These DMA channels are otherwise unused by the standard
>> 2218 SiByte Linux port. Seems to give a small performance benefit.
>> 2219
>> 2220 config CPU_HAS_PREFETCH
>> 2221 bool
>> 2222
>> 2223 config CPU_GENERIC_DUMP_TLB
>> 2224 bool
>> 2225 default y if !CPU_R3000
>> 2226
>> 2227 config MIPS_FP_SUPPORT
>> 2228 bool "Floating Point support" if EXPERT
>> 2229 default y
>> 2230 help
>> 2231 Select y to include support for floating point in the kernel
>> 2232 including initialization of FPU hardware, FP context save & restore
>> 2233 and emulation of an FPU where necessary. Without this support any
>> 2234 userland program attempting to use floating point instructions will
>> 2235 receive a SIGILL.
>> 2236
>> 2237 If you know that your userland will not attempt to use floating point
>> 2238 instructions then you can say n here to shrink the kernel a little.
>> 2239
>> 2240 If unsure, say y.
>> 2241
>> 2242 config CPU_R2300_FPU
>> 2243 bool
>> 2244 depends on MIPS_FP_SUPPORT
>> 2245 default y if CPU_R3000
>> 2246
>> 2247 config CPU_R3K_TLB
>> 2248 bool
>> 2249
>> 2250 config CPU_R4K_FPU
>> 2251 bool
>> 2252 depends on MIPS_FP_SUPPORT
>> 2253 default y if !CPU_R2300_FPU
>> 2254
>> 2255 config CPU_R4K_CACHE_TLB
>> 2256 bool
>> 2257 default y if !(CPU_R3K_TLB || CPU_SB1 || CPU_CAVIUM_OCTEON)
>> 2258
>> 2259 config MIPS_MT_SMP
>> 2260 bool "MIPS MT SMP support (1 TC on each available VPE)"
>> 2261 default y
>> 2262 depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MIPSR6 && !CPU_MICROMIPS
>> 2263 select CPU_MIPSR2_IRQ_VI
>> 2264 select CPU_MIPSR2_IRQ_EI
>> 2265 select SYNC_R4K
>> 2266 select MIPS_MT
>> 2267 select SMP
>> 2268 select SMP_UP
>> 2269 select SYS_SUPPORTS_SMP
>> 2270 select SYS_SUPPORTS_SCHED_SMT
>> 2271 select MIPS_PERF_SHARED_TC_COUNTERS
>> 2272 help
>> 2273 This is a kernel model which is known as SMVP. This is supported
>> 2274 on cores with the MT ASE and uses the available VPEs to implement
>> 2275 virtual processors which supports SMP. This is equivalent to the
>> 2276 Intel Hyperthreading feature. For further information go to
>> 2277 <http://www.imgtec.com/mips/mips-multithreading.asp>.
>> 2278
>> 2279 config MIPS_MT
>> 2280 bool
>> 2281
>> 2282 config SCHED_SMT
>> 2283 bool "SMT (multithreading) scheduler support"
>> 2284 depends on SYS_SUPPORTS_SCHED_SMT
>> 2285 default n
>> 2286 help
>> 2287 SMT scheduler support improves the CPU scheduler's decision making
>> 2288 when dealing with MIPS MT enabled cores at a cost of slightly
>> 2289 increased overhead in some places. If unsure say N here.
>> 2290
>> 2291 config SYS_SUPPORTS_SCHED_SMT
>> 2292 bool
>> 2293
>> 2294 config SYS_SUPPORTS_MULTITHREADING
>> 2295 bool
>> 2296
>> 2297 config MIPS_MT_FPAFF
>> 2298 bool "Dynamic FPU affinity for FP-intensive threads"
>> 2299 default y
>> 2300 depends on MIPS_MT_SMP
>> 2301
>> 2302 config MIPSR2_TO_R6_EMULATOR
>> 2303 bool "MIPS R2-to-R6 emulator"
>> 2304 depends on CPU_MIPSR6
>> 2305 depends on MIPS_FP_SUPPORT
>> 2306 default y
>> 2307 help
>> 2308 Choose this option if you want to run non-R6 MIPS userland code.
>> 2309 Even if you say 'Y' here, the emulator will still be disabled by
>> 2310 default. You can enable it using the 'mipsr2emu' kernel option.
>> 2311 The only reason this is a build-time option is to save ~14K from the
>> 2312 final kernel image.
>> 2313
>> 2314 config SYS_SUPPORTS_VPE_LOADER
>> 2315 bool
>> 2316 depends on SYS_SUPPORTS_MULTITHREADING
>> 2317 help
>> 2318 Indicates that the platform supports the VPE loader, and provides
>> 2319 physical_memsize.
>> 2320
>> 2321 config MIPS_VPE_LOADER
>> 2322 bool "VPE loader support."
>> 2323 depends on SYS_SUPPORTS_VPE_LOADER && MODULES
>> 2324 select CPU_MIPSR2_IRQ_VI
>> 2325 select CPU_MIPSR2_IRQ_EI
>> 2326 select MIPS_MT
>> 2327 help
>> 2328 Includes a loader for loading an elf relocatable object
>> 2329 onto another VPE and running it.
>> 2330
>> 2331 config MIPS_VPE_LOADER_CMP
>> 2332 bool
>> 2333 default "y"
>> 2334 depends on MIPS_VPE_LOADER && MIPS_CMP
>> 2335
>> 2336 config MIPS_VPE_LOADER_MT
>> 2337 bool
>> 2338 default "y"
>> 2339 depends on MIPS_VPE_LOADER && !MIPS_CMP
>> 2340
>> 2341 config MIPS_VPE_LOADER_TOM
>> 2342 bool "Load VPE program into memory hidden from linux"
>> 2343 depends on MIPS_VPE_LOADER
>> 2344 default y
>> 2345 help
>> 2346 The loader can use memory that is present but has been hidden from
>> 2347 Linux using the kernel command line option "mem=xxMB". It's up to
>> 2348 you to ensure the amount you put in the option and the space your
>> 2349 program requires is less or equal to the amount physically present.
>> 2350
>> 2351 config MIPS_VPE_APSP_API
>> 2352 bool "Enable support for AP/SP API (RTLX)"
>> 2353 depends on MIPS_VPE_LOADER
>> 2354
>> 2355 config MIPS_VPE_APSP_API_CMP
>> 2356 bool
>> 2357 default "y"
>> 2358 depends on MIPS_VPE_APSP_API && MIPS_CMP
>> 2359
>> 2360 config MIPS_VPE_APSP_API_MT
>> 2361 bool
>> 2362 default "y"
>> 2363 depends on MIPS_VPE_APSP_API && !MIPS_CMP
>> 2364
>> 2365 config MIPS_CMP
>> 2366 bool "MIPS CMP framework support (DEPRECATED)"
>> 2367 depends on SYS_SUPPORTS_MIPS_CMP && !CPU_MIPSR6
>> 2368 select SMP
>> 2369 select SYNC_R4K
>> 2370 select SYS_SUPPORTS_SMP
>> 2371 select WEAK_ORDERING
>> 2372 default n
>> 2373 help
>> 2374 Select this if you are using a bootloader which implements the "CMP
>> 2375 framework" protocol (ie. YAMON) and want your kernel to make use of
>> 2376 its ability to start secondary CPUs.
>> 2377
>> 2378 Unless you have a specific need, you should use CONFIG_MIPS_CPS
>> 2379 instead of this.
>> 2380
>> 2381 config MIPS_CPS
>> 2382 bool "MIPS Coherent Processing System support"
>> 2383 depends on SYS_SUPPORTS_MIPS_CPS
>> 2384 select MIPS_CM
>> 2385 select MIPS_CPS_PM if HOTPLUG_CPU
>> 2386 select SMP
>> 2387 select SYNC_R4K if (CEVT_R4K || CSRC_R4K)
>> 2388 select SYS_SUPPORTS_HOTPLUG_CPU
>> 2389 select SYS_SUPPORTS_SCHED_SMT if CPU_MIPSR6
>> 2390 select SYS_SUPPORTS_SMP
>> 2391 select WEAK_ORDERING
>> 2392 select GENERIC_IRQ_MIGRATION if HOTPLUG_CPU
>> 2393 help
>> 2394 Select this if you wish to run an SMP kernel across multiple cores
>> 2395 within a MIPS Coherent Processing System. When this option is
>> 2396 enabled the kernel will probe for other cores and boot them with
>> 2397 no external assistance. It is safe to enable this when hardware
>> 2398 support is unavailable.
>> 2399
>> 2400 config MIPS_CPS_PM
>> 2401 depends on MIPS_CPS
>> 2402 bool
>> 2403
>> 2404 config MIPS_CM
>> 2405 bool
>> 2406 select MIPS_CPC
>> 2407
>> 2408 config MIPS_CPC
>> 2409 bool
>> 2410
>> 2411 config SB1_PASS_2_WORKAROUNDS
>> 2412 bool
>> 2413 depends on CPU_SB1 && (CPU_SB1_PASS_2_2 || CPU_SB1_PASS_2)
>> 2414 default y
>> 2415
>> 2416 config SB1_PASS_2_1_WORKAROUNDS
>> 2417 bool
>> 2418 depends on CPU_SB1 && CPU_SB1_PASS_2
>> 2419 default y
>> 2420
251 choice 2421 choice
252 prompt "Power Manager Instruction (wai !! 2422 prompt "SmartMIPS or microMIPS ASE support"
253 default CPU_PM_NONE <<
254 2423
255 config CPU_PM_NONE !! 2424 config CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS
256 bool "None" 2425 bool "None"
>> 2426 help
>> 2427 Select this if you want neither microMIPS nor SmartMIPS support
257 2428
258 config CPU_PM_WAIT !! 2429 config CPU_HAS_SMARTMIPS
259 bool "wait" !! 2430 depends on SYS_SUPPORTS_SMARTMIPS
260 !! 2431 bool "SmartMIPS"
261 config CPU_PM_DOZE !! 2432 help
262 bool "doze" !! 2433 SmartMIPS is a extension of the MIPS32 architecture aimed at
>> 2434 increased security at both hardware and software level for
>> 2435 smartcards. Enabling this option will allow proper use of the
>> 2436 SmartMIPS instructions by Linux applications. However a kernel with
>> 2437 this option will not work on a MIPS core without SmartMIPS core. If
>> 2438 you don't know you probably don't have SmartMIPS and should say N
>> 2439 here.
>> 2440
>> 2441 config CPU_MICROMIPS
>> 2442 depends on 32BIT && SYS_SUPPORTS_MICROMIPS && !CPU_MIPSR6
>> 2443 bool "microMIPS"
>> 2444 help
>> 2445 When this option is enabled the kernel will be built using the
>> 2446 microMIPS ISA
263 2447
264 config CPU_PM_STOP <<
265 bool "stop" <<
266 endchoice 2448 endchoice
267 2449
268 menuconfig HAVE_TCM !! 2450 config CPU_HAS_MSA
269 bool "Tightly-Coupled/Sram Memory" !! 2451 bool "Support for the MIPS SIMD Architecture"
270 depends on !COMPILE_TEST !! 2452 depends on CPU_SUPPORTS_MSA
271 help !! 2453 depends on MIPS_FP_SUPPORT
272 The implementation are not only used !! 2454 depends on 64BIT || MIPS_O32_FP64_SUPPORT
273 but also used by sram on SOC bus. It !! 2455 help
274 software interface, so that old tcm !! 2456 MIPS SIMD Architecture (MSA) introduces 128 bit wide vector registers
275 re-used directly. !! 2457 and a set of SIMD instructions to operate on them. When this option
276 !! 2458 is enabled the kernel will support allocating & switching MSA
277 if HAVE_TCM !! 2459 vector register contexts. If you know that your kernel will only be
278 config ITCM_RAM_BASE !! 2460 running on CPUs which do not support MSA or that your userland will
279 hex "ITCM ram base" !! 2461 not be making use of it then you may wish to say N here to reduce
280 default 0xffffffff !! 2462 the size & complexity of your kernel.
281 <<
282 config ITCM_NR_PAGES <<
283 int "Page count of ITCM size: NR*4KB" <<
284 range 1 256 <<
285 default 32 <<
286 <<
287 config HAVE_DTCM <<
288 bool "DTCM Support" <<
289 <<
290 config DTCM_RAM_BASE <<
291 hex "DTCM ram base" <<
292 depends on HAVE_DTCM <<
293 default 0xffffffff <<
294 <<
295 config DTCM_NR_PAGES <<
296 int "Page count of DTCM size: NR*4KB" <<
297 depends on HAVE_DTCM <<
298 range 1 256 <<
299 default 32 <<
300 endif <<
301 <<
302 config CPU_HAS_VDSP <<
303 bool "CPU has VDSP coprocessor" <<
304 depends on CPU_HAS_FPU && CPU_HAS_FPUV <<
305 <<
306 config CPU_HAS_FPU <<
307 bool "CPU has FPU coprocessor" <<
308 depends on CPU_CK807 || CPU_CK810 || C <<
309 <<
310 config CPU_HAS_ICACHE_INS <<
311 bool "CPU has Icache invalidate instru <<
312 depends on CPU_HAS_CACHEV2 <<
313 <<
314 config CPU_HAS_TEE <<
315 bool "CPU has Trusted Execution Enviro <<
316 depends on CPU_CK810 <<
317 2463
318 config SMP !! 2464 If unsure, say Y.
319 bool "Symmetric Multi-Processing (SMP) <<
320 depends on CPU_CK860 <<
321 default n <<
322 2465
323 config NR_CPUS !! 2466 config CPU_HAS_WB
324 int "Maximum number of CPUs (2-32)" !! 2467 bool
325 range 2 32 !! 2468
326 depends on SMP !! 2469 config XKS01
327 default "4" !! 2470 bool
>> 2471
>> 2472 config CPU_HAS_DIEI
>> 2473 depends on !CPU_DIEI_BROKEN
>> 2474 bool
>> 2475
>> 2476 config CPU_DIEI_BROKEN
>> 2477 bool
>> 2478
>> 2479 config CPU_HAS_RIXI
>> 2480 bool
>> 2481
>> 2482 config CPU_NO_LOAD_STORE_LR
>> 2483 bool
>> 2484 help
>> 2485 CPU lacks support for unaligned load and store instructions:
>> 2486 LWL, LWR, SWL, SWR (Load/store word left/right).
>> 2487 LDL, LDR, SDL, SDR (Load/store doubleword left/right, for 64bit
>> 2488 systems).
>> 2489
>> 2490 #
>> 2491 # Vectored interrupt mode is an R2 feature
>> 2492 #
>> 2493 config CPU_MIPSR2_IRQ_VI
>> 2494 bool
>> 2495
>> 2496 #
>> 2497 # Extended interrupt mode is an R2 feature
>> 2498 #
>> 2499 config CPU_MIPSR2_IRQ_EI
>> 2500 bool
>> 2501
>> 2502 config CPU_HAS_SYNC
>> 2503 bool
>> 2504 depends on !CPU_R3000
>> 2505 default y
>> 2506
>> 2507 #
>> 2508 # CPU non-features
>> 2509 #
>> 2510
>> 2511 # Work around the "daddi" and "daddiu" CPU errata:
>> 2512 #
>> 2513 # - The `daddi' instruction fails to trap on overflow.
>> 2514 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
>> 2515 # erratum #23
>> 2516 #
>> 2517 # - The `daddiu' instruction can produce an incorrect result.
>> 2518 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
>> 2519 # erratum #41
>> 2520 # "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0", erratum
>> 2521 # #15
>> 2522 # "MIPS R4400PC/SC Errata, Processor Revision 1.0", erratum #7
>> 2523 # "MIPS R4400MC Errata, Processor Revision 1.0", erratum #5
>> 2524 config CPU_DADDI_WORKAROUNDS
>> 2525 bool
>> 2526
>> 2527 # Work around certain R4000 CPU errata (as implemented by GCC):
>> 2528 #
>> 2529 # - A double-word or a variable shift may give an incorrect result
>> 2530 # if executed immediately after starting an integer division:
>> 2531 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
>> 2532 # erratum #28
>> 2533 # "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0", erratum
>> 2534 # #19
>> 2535 #
>> 2536 # - A double-word or a variable shift may give an incorrect result
>> 2537 # if executed while an integer multiplication is in progress:
>> 2538 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
>> 2539 # errata #16 & #28
>> 2540 #
>> 2541 # - An integer division may give an incorrect result if started in
>> 2542 # a delay slot of a taken branch or a jump:
>> 2543 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
>> 2544 # erratum #52
>> 2545 config CPU_R4000_WORKAROUNDS
>> 2546 bool
>> 2547 select CPU_R4400_WORKAROUNDS
>> 2548
>> 2549 # Work around certain R4400 CPU errata (as implemented by GCC):
>> 2550 #
>> 2551 # - A double-word or a variable shift may give an incorrect result
>> 2552 # if executed immediately after starting an integer division:
>> 2553 # "MIPS R4400MC Errata, Processor Revision 1.0", erratum #10
>> 2554 # "MIPS R4400MC Errata, Processor Revision 2.0 & 3.0", erratum #4
>> 2555 config CPU_R4400_WORKAROUNDS
>> 2556 bool
>> 2557
>> 2558 config CPU_R4X00_BUGS64
>> 2559 bool
>> 2560 default y if SYS_HAS_CPU_R4X00 && 64BIT && (TARGET_ISA_REV < 1)
>> 2561
>> 2562 config MIPS_ASID_SHIFT
>> 2563 int
>> 2564 default 6 if CPU_R3000
>> 2565 default 0
>> 2566
>> 2567 config MIPS_ASID_BITS
>> 2568 int
>> 2569 default 0 if MIPS_ASID_BITS_VARIABLE
>> 2570 default 6 if CPU_R3000
>> 2571 default 8
>> 2572
>> 2573 config MIPS_ASID_BITS_VARIABLE
>> 2574 bool
>> 2575
>> 2576 config MIPS_CRC_SUPPORT
>> 2577 bool
>> 2578
>> 2579 # R4600 erratum. Due to the lack of errata information the exact
>> 2580 # technical details aren't known. I've experimentally found that disabling
>> 2581 # interrupts during indexed I-cache flushes seems to be sufficient to deal
>> 2582 # with the issue.
>> 2583 config WAR_R4600_V1_INDEX_ICACHEOP
>> 2584 bool
>> 2585
>> 2586 # Pleasures of the R4600 V1.x. Cite from the IDT R4600 V1.7 errata:
>> 2587 #
>> 2588 # 18. The CACHE instructions Hit_Writeback_Invalidate_D, Hit_Writeback_D,
>> 2589 # Hit_Invalidate_D and Create_Dirty_Excl_D should only be
>> 2590 # executed if there is no other dcache activity. If the dcache is
>> 2591 # accessed for another instruction immediately preceding when these
>> 2592 # cache instructions are executing, it is possible that the dcache
>> 2593 # tag match outputs used by these cache instructions will be
>> 2594 # incorrect. These cache instructions should be preceded by at least
>> 2595 # four instructions that are not any kind of load or store
>> 2596 # instruction.
>> 2597 #
>> 2598 # This is not allowed: lw
>> 2599 # nop
>> 2600 # nop
>> 2601 # nop
>> 2602 # cache Hit_Writeback_Invalidate_D
>> 2603 #
>> 2604 # This is allowed: lw
>> 2605 # nop
>> 2606 # nop
>> 2607 # nop
>> 2608 # nop
>> 2609 # cache Hit_Writeback_Invalidate_D
>> 2610 config WAR_R4600_V1_HIT_CACHEOP
>> 2611 bool
>> 2612
>> 2613 # Writeback and invalidate the primary cache dcache before DMA.
>> 2614 #
>> 2615 # R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D,
>> 2616 # Hit_Writeback_D, Hit_Invalidate_D and Create_Dirty_Exclusive_D will only
>> 2617 # operate correctly if the internal data cache refill buffer is empty. These
>> 2618 # CACHE instructions should be separated from any potential data cache miss
>> 2619 # by a load instruction to an uncached address to empty the response buffer."
>> 2620 # (Revision 2.0 device errata from IDT available on https://www.idt.com/
>> 2621 # in .pdf format.)
>> 2622 config WAR_R4600_V2_HIT_CACHEOP
>> 2623 bool
>> 2624
>> 2625 # From TX49/H2 manual: "If the instruction (i.e. CACHE) is issued for
>> 2626 # the line which this instruction itself exists, the following
>> 2627 # operation is not guaranteed."
>> 2628 #
>> 2629 # Workaround: do two phase flushing for Index_Invalidate_I
>> 2630 config WAR_TX49XX_ICACHE_INDEX_INV
>> 2631 bool
>> 2632
>> 2633 # The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra
>> 2634 # opposes it being called that) where invalid instructions in the same
>> 2635 # I-cache line worth of instructions being fetched may case spurious
>> 2636 # exceptions.
>> 2637 config WAR_ICACHE_REFILLS
>> 2638 bool
>> 2639
>> 2640 # On the R10000 up to version 2.6 (not sure about 2.7) there is a bug that
>> 2641 # may cause ll / sc and lld / scd sequences to execute non-atomically.
>> 2642 config WAR_R10000_LLSC
>> 2643 bool
>> 2644
>> 2645 # 34K core erratum: "Problems Executing the TLBR Instruction"
>> 2646 config WAR_MIPS34K_MISSED_ITLB
>> 2647 bool
328 2648
>> 2649 #
>> 2650 # - Highmem only makes sense for the 32-bit kernel.
>> 2651 # - The current highmem code will only work properly on physically indexed
>> 2652 # caches such as R3000, SB1, R7000 or those that look like they're virtually
>> 2653 # indexed such as R4000/R4400 SC and MC versions or R10000. So for the
>> 2654 # moment we protect the user and offer the highmem option only on machines
>> 2655 # where it's known to be safe. This will not offer highmem on a few systems
>> 2656 # such as MIPS32 and MIPS64 CPUs which may have virtual and physically
>> 2657 # indexed CPUs but we're playing safe.
>> 2658 # - We use SYS_SUPPORTS_HIGHMEM to offer highmem only for systems where we
>> 2659 # know they might have memory configurations that could make use of highmem
>> 2660 # support.
>> 2661 #
329 config HIGHMEM 2662 config HIGHMEM
330 bool "High Memory Support" 2663 bool "High Memory Support"
331 depends on !CPU_CK610 !! 2664 depends on 32BIT && CPU_SUPPORTS_HIGHMEM && SYS_SUPPORTS_HIGHMEM && !CPU_MIPS32_3_5_EVA
332 select KMAP_LOCAL 2665 select KMAP_LOCAL
>> 2666
>> 2667 config CPU_SUPPORTS_HIGHMEM
>> 2668 bool
>> 2669
>> 2670 config SYS_SUPPORTS_HIGHMEM
>> 2671 bool
>> 2672
>> 2673 config SYS_SUPPORTS_SMARTMIPS
>> 2674 bool
>> 2675
>> 2676 config SYS_SUPPORTS_MICROMIPS
>> 2677 bool
>> 2678
>> 2679 config SYS_SUPPORTS_MIPS16
>> 2680 bool
>> 2681 help
>> 2682 This option must be set if a kernel might be executed on a MIPS16-
>> 2683 enabled CPU even if MIPS16 is not actually being used. In other
>> 2684 words, it makes the kernel MIPS16-tolerant.
>> 2685
>> 2686 config CPU_SUPPORTS_MSA
>> 2687 bool
>> 2688
>> 2689 config ARCH_FLATMEM_ENABLE
>> 2690 def_bool y
>> 2691 depends on !NUMA && !CPU_LOONGSON2EF
>> 2692
>> 2693 config ARCH_SPARSEMEM_ENABLE
>> 2694 bool
>> 2695 select SPARSEMEM_STATIC if !SGI_IP27
>> 2696
>> 2697 config NUMA
>> 2698 bool "NUMA Support"
>> 2699 depends on SYS_SUPPORTS_NUMA
>> 2700 select SMP
>> 2701 select HAVE_SETUP_PER_CPU_AREA
>> 2702 select NEED_PER_CPU_EMBED_FIRST_CHUNK
>> 2703 help
>> 2704 Say Y to compile the kernel to support NUMA (Non-Uniform Memory
>> 2705 Access). This option improves performance on systems with more
>> 2706 than two nodes; on two node systems it is generally better to
>> 2707 leave it disabled; on single node systems leave this option
>> 2708 disabled.
>> 2709
>> 2710 config SYS_SUPPORTS_NUMA
>> 2711 bool
>> 2712
>> 2713 config HAVE_ARCH_NODEDATA_EXTENSION
>> 2714 bool
>> 2715
>> 2716 config RELOCATABLE
>> 2717 bool "Relocatable kernel"
>> 2718 depends on SYS_SUPPORTS_RELOCATABLE
>> 2719 depends on CPU_MIPS32_R2 || CPU_MIPS64_R2 || \
>> 2720 CPU_MIPS32_R5 || CPU_MIPS64_R5 || \
>> 2721 CPU_MIPS32_R6 || CPU_MIPS64_R6 || \
>> 2722 CPU_P5600 || CAVIUM_OCTEON_SOC || \
>> 2723 CPU_LOONGSON64
>> 2724 help
>> 2725 This builds a kernel image that retains relocation information
>> 2726 so it can be loaded someplace besides the default 1MB.
>> 2727 The relocations make the kernel binary about 15% larger,
>> 2728 but are discarded at runtime
>> 2729
>> 2730 config RELOCATION_TABLE_SIZE
>> 2731 hex "Relocation table size"
>> 2732 depends on RELOCATABLE
>> 2733 range 0x0 0x01000000
>> 2734 default "0x00200000" if CPU_LOONGSON64
>> 2735 default "0x00100000"
>> 2736 help
>> 2737 A table of relocation data will be appended to the kernel binary
>> 2738 and parsed at boot to fix up the relocated kernel.
>> 2739
>> 2740 This option allows the amount of space reserved for the table to be
>> 2741 adjusted, although the default of 1Mb should be ok in most cases.
>> 2742
>> 2743 The build will fail and a valid size suggested if this is too small.
>> 2744
>> 2745 If unsure, leave at the default value.
>> 2746
>> 2747 config RANDOMIZE_BASE
>> 2748 bool "Randomize the address of the kernel image"
>> 2749 depends on RELOCATABLE
>> 2750 help
>> 2751 Randomizes the physical and virtual address at which the
>> 2752 kernel image is loaded, as a security feature that
>> 2753 deters exploit attempts relying on knowledge of the location
>> 2754 of kernel internals.
>> 2755
>> 2756 Entropy is generated using any coprocessor 0 registers available.
>> 2757
>> 2758 The kernel will be offset by up to RANDOMIZE_BASE_MAX_OFFSET.
>> 2759
>> 2760 If unsure, say N.
>> 2761
>> 2762 config RANDOMIZE_BASE_MAX_OFFSET
>> 2763 hex "Maximum kASLR offset" if EXPERT
>> 2764 depends on RANDOMIZE_BASE
>> 2765 range 0x0 0x40000000 if EVA || 64BIT
>> 2766 range 0x0 0x08000000
>> 2767 default "0x01000000"
>> 2768 help
>> 2769 When kASLR is active, this provides the maximum offset that will
>> 2770 be applied to the kernel image. It should be set according to the
>> 2771 amount of physical RAM available in the target system minus
>> 2772 PHYSICAL_START and must be a power of 2.
>> 2773
>> 2774 This is limited by the size of KSEG0, 256Mb on 32-bit or 1Gb with
>> 2775 EVA or 64-bit. The default is 16Mb.
>> 2776
>> 2777 config NODES_SHIFT
>> 2778 int
>> 2779 default "6"
>> 2780 depends on NUMA
>> 2781
>> 2782 config HW_PERF_EVENTS
>> 2783 bool "Enable hardware performance counter support for perf events"
>> 2784 depends on PERF_EVENTS && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON || CPU_LOONGSON64)
>> 2785 default y
>> 2786 help
>> 2787 Enable hardware performance counter support for perf events. If
>> 2788 disabled, perf events will use software events only.
>> 2789
>> 2790 config DMI
>> 2791 bool "Enable DMI scanning"
>> 2792 depends on MACH_LOONGSON64
>> 2793 select DMI_SCAN_MACHINE_NON_EFI_FALLBACK
333 default y 2794 default y
>> 2795 help
>> 2796 Enabled scanning of DMI to identify machine quirks. Say Y
>> 2797 here unless you have verified that your setup is not
>> 2798 affected by entries in the DMI blacklist. Required by PNP
>> 2799 BIOS code.
334 2800
335 config DRAM_BASE !! 2801 config SMP
336 hex "DRAM start addr (the same with me !! 2802 bool "Multi-Processing support"
337 default 0x0 !! 2803 depends on SYS_SUPPORTS_SMP
>> 2804 help
>> 2805 This enables support for systems with more than one CPU. If you have
>> 2806 a system with only one CPU, say N. If you have a system with more
>> 2807 than one CPU, say Y.
>> 2808
>> 2809 If you say N here, the kernel will run on uni- and multiprocessor
>> 2810 machines, but will use only one CPU of a multiprocessor machine. If
>> 2811 you say Y here, the kernel will run on many, but not all,
>> 2812 uniprocessor machines. On a uniprocessor machine, the kernel
>> 2813 will run faster if you say N here.
>> 2814
>> 2815 People using multiprocessor machines who say Y here should also say
>> 2816 Y to "Enhanced Real Time Clock Support", below.
>> 2817
>> 2818 See also the SMP-HOWTO available at
>> 2819 <https://www.tldp.org/docs.html#howto>.
>> 2820
>> 2821 If you don't know what to do here, say N.
338 2822
339 config HOTPLUG_CPU 2823 config HOTPLUG_CPU
340 bool "Support for hot-pluggable CPUs" 2824 bool "Support for hot-pluggable CPUs"
341 select GENERIC_IRQ_MIGRATION !! 2825 depends on SMP && SYS_SUPPORTS_HOTPLUG_CPU
342 depends on SMP <<
343 help 2826 help
344 Say Y here to allow turning CPUs off 2827 Say Y here to allow turning CPUs off and on. CPUs can be
345 controlled through /sys/devices/syst !! 2828 controlled through /sys/devices/system/cpu.
346 !! 2829 (Note: power management support will enable this option
>> 2830 automatically on SMP systems. )
347 Say N if you want to disable CPU hot 2831 Say N if you want to disable CPU hotplug.
348 2832
349 config HAVE_EFFICIENT_UNALIGNED_STRING_OPS !! 2833 config SMP_UP
350 bool "Enable EFFICIENT_UNALIGNED_STRIN !! 2834 bool
351 depends on CPU_CK807 || CPU_CK810 || C !! 2835
>> 2836 config SYS_SUPPORTS_MIPS_CMP
>> 2837 bool
>> 2838
>> 2839 config SYS_SUPPORTS_MIPS_CPS
>> 2840 bool
>> 2841
>> 2842 config SYS_SUPPORTS_SMP
>> 2843 bool
>> 2844
>> 2845 config NR_CPUS_DEFAULT_4
>> 2846 bool
>> 2847
>> 2848 config NR_CPUS_DEFAULT_8
>> 2849 bool
>> 2850
>> 2851 config NR_CPUS_DEFAULT_16
>> 2852 bool
>> 2853
>> 2854 config NR_CPUS_DEFAULT_32
>> 2855 bool
>> 2856
>> 2857 config NR_CPUS_DEFAULT_64
>> 2858 bool
>> 2859
>> 2860 config NR_CPUS
>> 2861 int "Maximum number of CPUs (2-256)"
>> 2862 range 2 256
>> 2863 depends on SMP
>> 2864 default "4" if NR_CPUS_DEFAULT_4
>> 2865 default "8" if NR_CPUS_DEFAULT_8
>> 2866 default "16" if NR_CPUS_DEFAULT_16
>> 2867 default "32" if NR_CPUS_DEFAULT_32
>> 2868 default "64" if NR_CPUS_DEFAULT_64
>> 2869 help
>> 2870 This allows you to specify the maximum number of CPUs which this
>> 2871 kernel will support. The maximum supported value is 32 for 32-bit
>> 2872 kernel and 64 for 64-bit kernels; the minimum value which makes
>> 2873 sense is 1 for Qemu (useful only for kernel debugging purposes)
>> 2874 and 2 for all others.
>> 2875
>> 2876 This is purely to save memory - each supported CPU adds
>> 2877 approximately eight kilobytes to the kernel image. For best
>> 2878 performance should round up your number of processors to the next
>> 2879 power of two.
>> 2880
>> 2881 config MIPS_PERF_SHARED_TC_COUNTERS
>> 2882 bool
>> 2883
>> 2884 config MIPS_NR_CPU_NR_MAP_1024
>> 2885 bool
>> 2886
>> 2887 config MIPS_NR_CPU_NR_MAP
>> 2888 int
>> 2889 depends on SMP
>> 2890 default 1024 if MIPS_NR_CPU_NR_MAP_1024
>> 2891 default NR_CPUS if !MIPS_NR_CPU_NR_MAP_1024
>> 2892
>> 2893 #
>> 2894 # Timer Interrupt Frequency Configuration
>> 2895 #
>> 2896
>> 2897 choice
>> 2898 prompt "Timer frequency"
>> 2899 default HZ_250
352 help 2900 help
353 Say Y here to enable EFFICIENT_UNALI !! 2901 Allows the configuration of the timer frequency.
354 deal with unaligned access by hardwa !! 2902
>> 2903 config HZ_24
>> 2904 bool "24 HZ" if SYS_SUPPORTS_24HZ || SYS_SUPPORTS_ARBIT_HZ
>> 2905
>> 2906 config HZ_48
>> 2907 bool "48 HZ" if SYS_SUPPORTS_48HZ || SYS_SUPPORTS_ARBIT_HZ
>> 2908
>> 2909 config HZ_100
>> 2910 bool "100 HZ" if SYS_SUPPORTS_100HZ || SYS_SUPPORTS_ARBIT_HZ
>> 2911
>> 2912 config HZ_128
>> 2913 bool "128 HZ" if SYS_SUPPORTS_128HZ || SYS_SUPPORTS_ARBIT_HZ
>> 2914
>> 2915 config HZ_250
>> 2916 bool "250 HZ" if SYS_SUPPORTS_250HZ || SYS_SUPPORTS_ARBIT_HZ
>> 2917
>> 2918 config HZ_256
>> 2919 bool "256 HZ" if SYS_SUPPORTS_256HZ || SYS_SUPPORTS_ARBIT_HZ
>> 2920
>> 2921 config HZ_1000
>> 2922 bool "1000 HZ" if SYS_SUPPORTS_1000HZ || SYS_SUPPORTS_ARBIT_HZ
>> 2923
>> 2924 config HZ_1024
>> 2925 bool "1024 HZ" if SYS_SUPPORTS_1024HZ || SYS_SUPPORTS_ARBIT_HZ
>> 2926
>> 2927 endchoice
>> 2928
>> 2929 config SYS_SUPPORTS_24HZ
>> 2930 bool
>> 2931
>> 2932 config SYS_SUPPORTS_48HZ
>> 2933 bool
>> 2934
>> 2935 config SYS_SUPPORTS_100HZ
>> 2936 bool
>> 2937
>> 2938 config SYS_SUPPORTS_128HZ
>> 2939 bool
>> 2940
>> 2941 config SYS_SUPPORTS_250HZ
>> 2942 bool
>> 2943
>> 2944 config SYS_SUPPORTS_256HZ
>> 2945 bool
>> 2946
>> 2947 config SYS_SUPPORTS_1000HZ
>> 2948 bool
>> 2949
>> 2950 config SYS_SUPPORTS_1024HZ
>> 2951 bool
>> 2952
>> 2953 config SYS_SUPPORTS_ARBIT_HZ
>> 2954 bool
>> 2955 default y if !SYS_SUPPORTS_24HZ && \
>> 2956 !SYS_SUPPORTS_48HZ && \
>> 2957 !SYS_SUPPORTS_100HZ && \
>> 2958 !SYS_SUPPORTS_128HZ && \
>> 2959 !SYS_SUPPORTS_250HZ && \
>> 2960 !SYS_SUPPORTS_256HZ && \
>> 2961 !SYS_SUPPORTS_1000HZ && \
>> 2962 !SYS_SUPPORTS_1024HZ
>> 2963
>> 2964 config HZ
>> 2965 int
>> 2966 default 24 if HZ_24
>> 2967 default 48 if HZ_48
>> 2968 default 100 if HZ_100
>> 2969 default 128 if HZ_128
>> 2970 default 250 if HZ_250
>> 2971 default 256 if HZ_256
>> 2972 default 1000 if HZ_1000
>> 2973 default 1024 if HZ_1024
>> 2974
>> 2975 config SCHED_HRTICK
>> 2976 def_bool HIGH_RES_TIMERS
>> 2977
>> 2978 config KEXEC
>> 2979 bool "Kexec system call"
>> 2980 select KEXEC_CORE
>> 2981 help
>> 2982 kexec is a system call that implements the ability to shutdown your
>> 2983 current kernel, and to start another kernel. It is like a reboot
>> 2984 but it is independent of the system firmware. And like a reboot
>> 2985 you can start any kernel with it, not just Linux.
>> 2986
>> 2987 The name comes from the similarity to the exec system call.
>> 2988
>> 2989 It is an ongoing process to be certain the hardware in a machine
>> 2990 is properly shutdown, so do not be surprised if this code does not
>> 2991 initially work for you. As of this writing the exact hardware
>> 2992 interface is strongly in flux, so no good recommendation can be
>> 2993 made.
>> 2994
>> 2995 config CRASH_DUMP
>> 2996 bool "Kernel crash dumps"
>> 2997 help
>> 2998 Generate crash dump after being started by kexec.
>> 2999 This should be normally only set in special crash dump kernels
>> 3000 which are loaded in the main kernel with kexec-tools into
>> 3001 a specially reserved region and then later executed after
>> 3002 a crash by kdump/kexec. The crash dump kernel must be compiled
>> 3003 to a memory address not used by the main kernel or firmware using
>> 3004 PHYSICAL_START.
>> 3005
>> 3006 config PHYSICAL_START
>> 3007 hex "Physical address where the kernel is loaded"
>> 3008 default "0xffffffff84000000"
>> 3009 depends on CRASH_DUMP
>> 3010 help
>> 3011 This gives the CKSEG0 or KSEG0 address where the kernel is loaded.
>> 3012 If you plan to use kernel for capturing the crash dump change
>> 3013 this value to start of the reserved region (the "X" value as
>> 3014 specified in the "crashkernel=YM@XM" command line boot parameter
>> 3015 passed to the panic-ed kernel).
>> 3016
>> 3017 config MIPS_O32_FP64_SUPPORT
>> 3018 bool "Support for O32 binaries using 64-bit FP" if !CPU_MIPSR6
>> 3019 depends on 32BIT || MIPS32_O32
>> 3020 help
>> 3021 When this is enabled, the kernel will support use of 64-bit floating
>> 3022 point registers with binaries using the O32 ABI along with the
>> 3023 EF_MIPS_FP64 ELF header flag (typically built with -mfp64). On
>> 3024 32-bit MIPS systems this support is at the cost of increasing the
>> 3025 size and complexity of the compiled FPU emulator. Thus if you are
>> 3026 running a MIPS32 system and know that none of your userland binaries
>> 3027 will require 64-bit floating point, you may wish to reduce the size
>> 3028 of your kernel & potentially improve FP emulation performance by
>> 3029 saying N here.
>> 3030
>> 3031 Although binutils currently supports use of this flag the details
>> 3032 concerning its effect upon the O32 ABI in userland are still being
>> 3033 worked on. In order to avoid userland becoming dependent upon current
>> 3034 behaviour before the details have been finalised, this option should
>> 3035 be considered experimental and only enabled by those working upon
>> 3036 said details.
>> 3037
>> 3038 If unsure, say N.
>> 3039
>> 3040 config USE_OF
>> 3041 bool
>> 3042 select OF
>> 3043 select OF_EARLY_FLATTREE
>> 3044 select IRQ_DOMAIN
>> 3045
>> 3046 config UHI_BOOT
>> 3047 bool
>> 3048
>> 3049 config BUILTIN_DTB
>> 3050 bool
>> 3051
>> 3052 choice
>> 3053 prompt "Kernel appended dtb support" if USE_OF
>> 3054 default MIPS_NO_APPENDED_DTB
>> 3055
>> 3056 config MIPS_NO_APPENDED_DTB
>> 3057 bool "None"
>> 3058 help
>> 3059 Do not enable appended dtb support.
>> 3060
>> 3061 config MIPS_ELF_APPENDED_DTB
>> 3062 bool "vmlinux"
>> 3063 help
>> 3064 With this option, the boot code will look for a device tree binary
>> 3065 DTB) included in the vmlinux ELF section .appended_dtb. By default
>> 3066 it is empty and the DTB can be appended using binutils command
>> 3067 objcopy:
>> 3068
>> 3069 objcopy --update-section .appended_dtb=<filename>.dtb vmlinux
>> 3070
>> 3071 This is meant as a backward compatibility convenience for those
>> 3072 systems with a bootloader that can't be upgraded to accommodate
>> 3073 the documented boot protocol using a device tree.
>> 3074
>> 3075 config MIPS_RAW_APPENDED_DTB
>> 3076 bool "vmlinux.bin or vmlinuz.bin"
>> 3077 help
>> 3078 With this option, the boot code will look for a device tree binary
>> 3079 DTB) appended to raw vmlinux.bin or vmlinuz.bin.
>> 3080 (e.g. cat vmlinux.bin <filename>.dtb > vmlinux_w_dtb).
>> 3081
>> 3082 This is meant as a backward compatibility convenience for those
>> 3083 systems with a bootloader that can't be upgraded to accommodate
>> 3084 the documented boot protocol using a device tree.
>> 3085
>> 3086 Beware that there is very little in terms of protection against
>> 3087 this option being confused by leftover garbage in memory that might
>> 3088 look like a DTB header after a reboot if no actual DTB is appended
>> 3089 to vmlinux.bin. Do not leave this option active in a production kernel
>> 3090 if you don't intend to always append a DTB.
>> 3091 endchoice
>> 3092
>> 3093 choice
>> 3094 prompt "Kernel command line type" if !CMDLINE_OVERRIDE
>> 3095 default MIPS_CMDLINE_FROM_DTB if USE_OF && !ATH79 && !MACH_INGENIC && \
>> 3096 !MACH_LOONGSON64 && !MIPS_MALTA && \
>> 3097 !CAVIUM_OCTEON_SOC
>> 3098 default MIPS_CMDLINE_FROM_BOOTLOADER
>> 3099
>> 3100 config MIPS_CMDLINE_FROM_DTB
>> 3101 depends on USE_OF
>> 3102 bool "Dtb kernel arguments if available"
>> 3103
>> 3104 config MIPS_CMDLINE_DTB_EXTEND
>> 3105 depends on USE_OF
>> 3106 bool "Extend dtb kernel arguments with bootloader arguments"
>> 3107
>> 3108 config MIPS_CMDLINE_FROM_BOOTLOADER
>> 3109 bool "Bootloader kernel arguments if available"
>> 3110
>> 3111 config MIPS_CMDLINE_BUILTIN_EXTEND
>> 3112 depends on CMDLINE_BOOL
>> 3113 bool "Extend builtin kernel arguments with bootloader arguments"
>> 3114 endchoice
>> 3115
>> 3116 endmenu
>> 3117
>> 3118 config LOCKDEP_SUPPORT
>> 3119 bool
>> 3120 default y
>> 3121
>> 3122 config STACKTRACE_SUPPORT
>> 3123 bool
>> 3124 default y
>> 3125
>> 3126 config PGTABLE_LEVELS
>> 3127 int
>> 3128 default 4 if PAGE_SIZE_4KB && MIPS_VA_BITS_48
>> 3129 default 3 if 64BIT && (!PAGE_SIZE_64KB || MIPS_VA_BITS_48)
>> 3130 default 2
>> 3131
>> 3132 config MIPS_AUTO_PFN_OFFSET
>> 3133 bool
>> 3134
>> 3135 menu "Bus options (PCI, PCMCIA, EISA, ISA, TC)"
>> 3136
>> 3137 config PCI_DRIVERS_GENERIC
>> 3138 select PCI_DOMAINS_GENERIC if PCI
>> 3139 bool
>> 3140
>> 3141 config PCI_DRIVERS_LEGACY
>> 3142 def_bool !PCI_DRIVERS_GENERIC
>> 3143 select NO_GENERIC_PCI_IOPORT_MAP
>> 3144 select PCI_DOMAINS if PCI
>> 3145
>> 3146 #
>> 3147 # ISA support is now enabled via select. Too many systems still have the one
>> 3148 # or other ISA chip on the board that users don't know about so don't expect
>> 3149 # users to choose the right thing ...
>> 3150 #
>> 3151 config ISA
>> 3152 bool
>> 3153
>> 3154 config TC
>> 3155 bool "TURBOchannel support"
>> 3156 depends on MACH_DECSTATION
>> 3157 help
>> 3158 TURBOchannel is a DEC (now Compaq (now HP)) bus for Alpha and MIPS
>> 3159 processors. TURBOchannel programming specifications are available
>> 3160 at:
>> 3161 <ftp://ftp.hp.com/pub/alphaserver/archive/triadd/>
>> 3162 and:
>> 3163 <http://www.computer-refuge.org/classiccmp/ftp.digital.com/pub/DEC/TriAdd/>
>> 3164 Linux driver support status is documented at:
>> 3165 <http://www.linux-mips.org/wiki/DECstation>
>> 3166
>> 3167 config MMU
>> 3168 bool
>> 3169 default y
>> 3170
>> 3171 config ARCH_MMAP_RND_BITS_MIN
>> 3172 default 12 if 64BIT
>> 3173 default 8
>> 3174
>> 3175 config ARCH_MMAP_RND_BITS_MAX
>> 3176 default 18 if 64BIT
>> 3177 default 15
>> 3178
>> 3179 config ARCH_MMAP_RND_COMPAT_BITS_MIN
>> 3180 default 8
>> 3181
>> 3182 config ARCH_MMAP_RND_COMPAT_BITS_MAX
>> 3183 default 15
>> 3184
>> 3185 config I8253
>> 3186 bool
>> 3187 select CLKSRC_I8253
>> 3188 select CLKEVT_I8253
>> 3189 select MIPS_EXTERNAL_TIMER
>> 3190 endmenu
>> 3191
>> 3192 config TRAD_SIGNALS
>> 3193 bool
>> 3194
>> 3195 config MIPS32_COMPAT
>> 3196 bool
>> 3197
>> 3198 config COMPAT
>> 3199 bool
>> 3200
>> 3201 config MIPS32_O32
>> 3202 bool "Kernel support for o32 binaries"
>> 3203 depends on 64BIT
>> 3204 select ARCH_WANT_OLD_COMPAT_IPC
>> 3205 select COMPAT
>> 3206 select MIPS32_COMPAT
>> 3207 help
>> 3208 Select this option if you want to run o32 binaries. These are pure
>> 3209 32-bit binaries as used by the 32-bit Linux/MIPS port. Most of
>> 3210 existing binaries are in this format.
>> 3211
>> 3212 If unsure, say Y.
>> 3213
>> 3214 config MIPS32_N32
>> 3215 bool "Kernel support for n32 binaries"
>> 3216 depends on 64BIT
>> 3217 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
>> 3218 select COMPAT
>> 3219 select MIPS32_COMPAT
>> 3220 help
>> 3221 Select this option if you want to run n32 binaries. These are
>> 3222 64-bit binaries using 32-bit quantities for addressing and certain
>> 3223 data that would normally be 64-bit. They are used in special
>> 3224 cases.
>> 3225
>> 3226 If unsure, say N.
>> 3227
>> 3228 config CC_HAS_MNO_BRANCH_LIKELY
>> 3229 def_bool y
>> 3230 depends on $(cc-option,-mno-branch-likely)
>> 3231
>> 3232 menu "Power management options"
>> 3233
>> 3234 config ARCH_HIBERNATION_POSSIBLE
>> 3235 def_bool y
>> 3236 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
>> 3237
>> 3238 config ARCH_SUSPEND_POSSIBLE
>> 3239 def_bool y
>> 3240 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
>> 3241
>> 3242 source "kernel/power/Kconfig"
>> 3243
>> 3244 endmenu
>> 3245
>> 3246 config MIPS_EXTERNAL_TIMER
>> 3247 bool
>> 3248
>> 3249 menu "CPU Power Management"
>> 3250
>> 3251 if CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
>> 3252 source "drivers/cpufreq/Kconfig"
>> 3253 endif # CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
>> 3254
>> 3255 source "drivers/cpuidle/Kconfig"
355 3256
356 endmenu 3257 endmenu
357 3258
358 source "arch/csky/Kconfig.platforms" !! 3259 source "arch/mips/kvm/Kconfig"
359 3260
360 source "kernel/Kconfig.hz" !! 3261 source "arch/mips/vdso/Kconfig"
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