1 # SPDX-License-Identifier: GPL-2.0-only !! 1 # SPDX-License-Identifier: GPL-2.0
2 config CSKY !! 2 config MIPS
3 def_bool y !! 3 bool
4 select ARCH_32BIT_OFF_T !! 4 default y
5 select ARCH_HAS_CPU_CACHE_ALIASING !! 5 select ARCH_32BIT_OFF_T if !64BIT
6 select ARCH_HAS_DMA_PREP_COHERENT !! 6 select ARCH_BINFMT_ELF_STATE if MIPS_FP_SUPPORT
>> 7 select ARCH_HAS_CPU_FINALIZE_INIT
>> 8 select ARCH_HAS_CURRENT_STACK_POINTER if !CC_IS_CLANG || CLANG_VERSION >= 140000
>> 9 select ARCH_HAS_DEBUG_VIRTUAL if !64BIT
>> 10 select ARCH_HAS_FORTIFY_SOURCE
>> 11 select ARCH_HAS_KCOV
>> 12 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE if !EVA
>> 13 select ARCH_HAS_PTE_SPECIAL if !(32BIT && CPU_HAS_RIXI)
>> 14 select ARCH_HAS_STRNCPY_FROM_USER
>> 15 select ARCH_HAS_STRNLEN_USER
>> 16 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
>> 17 select ARCH_HAS_UBSAN_SANITIZE_ALL
7 select ARCH_HAS_GCOV_PROFILE_ALL 18 select ARCH_HAS_GCOV_PROFILE_ALL
8 select ARCH_HAS_SYNC_DMA_FOR_CPU !! 19 select ARCH_KEEP_MEMBLOCK
9 select ARCH_HAS_SYNC_DMA_FOR_DEVICE <<
10 select ARCH_USE_BUILTIN_BSWAP 20 select ARCH_USE_BUILTIN_BSWAP
>> 21 select ARCH_USE_CMPXCHG_LOCKREF if 64BIT
>> 22 select ARCH_USE_MEMTEST
11 select ARCH_USE_QUEUED_RWLOCKS 23 select ARCH_USE_QUEUED_RWLOCKS
12 select ARCH_USE_QUEUED_SPINLOCKS 24 select ARCH_USE_QUEUED_SPINLOCKS
13 select ARCH_HAS_CURRENT_STACK_POINTER !! 25 select ARCH_SUPPORTS_HUGETLBFS if CPU_SUPPORTS_HUGEPAGES
14 select ARCH_INLINE_READ_LOCK if !PREEM !! 26 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
15 select ARCH_INLINE_READ_LOCK_BH if !PR !! 27 select ARCH_WANT_IPC_PARSE_VERSION
16 select ARCH_INLINE_READ_LOCK_IRQ if !P !! 28 select ARCH_WANT_LD_ORPHAN_WARN
17 select ARCH_INLINE_READ_LOCK_IRQSAVE i !! 29 select BUILDTIME_TABLE_SORT
18 select ARCH_INLINE_READ_UNLOCK if !PRE !! 30 select CLONE_BACKWARDS
19 select ARCH_INLINE_READ_UNLOCK_BH if ! !! 31 select CPU_NO_EFFICIENT_FFS if (TARGET_ISA_REV < 1)
20 select ARCH_INLINE_READ_UNLOCK_IRQ if !! 32 select CPU_PM if CPU_IDLE
21 select ARCH_INLINE_READ_UNLOCK_IRQREST !! 33 select GENERIC_ATOMIC64 if !64BIT
22 select ARCH_INLINE_WRITE_LOCK if !PREE !! 34 select GENERIC_CMOS_UPDATE
23 select ARCH_INLINE_WRITE_LOCK_BH if !P !! 35 select GENERIC_CPU_AUTOPROBE
24 select ARCH_INLINE_WRITE_LOCK_IRQ if ! !! 36 select GENERIC_GETTIMEOFDAY
25 select ARCH_INLINE_WRITE_LOCK_IRQSAVE !! 37 select GENERIC_IOMAP
26 select ARCH_INLINE_WRITE_UNLOCK if !PR !! 38 select GENERIC_IRQ_PROBE
27 select ARCH_INLINE_WRITE_UNLOCK_BH if !! 39 select GENERIC_IRQ_SHOW
28 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !! 40 select GENERIC_ISA_DMA if EISA
29 select ARCH_INLINE_WRITE_UNLOCK_IRQRES <<
30 select ARCH_INLINE_SPIN_TRYLOCK if !PR <<
31 select ARCH_INLINE_SPIN_TRYLOCK_BH if <<
32 select ARCH_INLINE_SPIN_LOCK if !PREEM <<
33 select ARCH_INLINE_SPIN_LOCK_BH if !PR <<
34 select ARCH_INLINE_SPIN_LOCK_IRQ if !P <<
35 select ARCH_INLINE_SPIN_LOCK_IRQSAVE i <<
36 select ARCH_INLINE_SPIN_UNLOCK if !PRE <<
37 select ARCH_INLINE_SPIN_UNLOCK_BH if ! <<
38 select ARCH_INLINE_SPIN_UNLOCK_IRQ if <<
39 select ARCH_INLINE_SPIN_UNLOCK_IRQREST <<
40 select ARCH_NEED_CMPXCHG_1_EMU <<
41 select ARCH_WANT_FRAME_POINTERS if !CP <<
42 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_ <<
43 select COMMON_CLK <<
44 select CLKSRC_MMIO <<
45 select CSKY_MPINTC if CPU_CK860 <<
46 select CSKY_MP_TIMER if CPU_CK860 <<
47 select CSKY_APB_INTC <<
48 select DMA_DIRECT_REMAP <<
49 select IRQ_DOMAIN <<
50 select DW_APB_TIMER_OF <<
51 select GENERIC_IOREMAP <<
52 select GENERIC_LIB_ASHLDI3 41 select GENERIC_LIB_ASHLDI3
53 select GENERIC_LIB_ASHRDI3 42 select GENERIC_LIB_ASHRDI3
54 select GENERIC_LIB_LSHRDI3 <<
55 select GENERIC_LIB_MULDI3 <<
56 select GENERIC_LIB_CMPDI2 43 select GENERIC_LIB_CMPDI2
>> 44 select GENERIC_LIB_LSHRDI3
57 select GENERIC_LIB_UCMPDI2 45 select GENERIC_LIB_UCMPDI2
58 select GENERIC_ALLOCATOR !! 46 select GENERIC_SCHED_CLOCK if !CAVIUM_OCTEON_SOC
59 select GENERIC_ATOMIC64 <<
60 select GENERIC_CPU_DEVICES <<
61 select GENERIC_IRQ_CHIP <<
62 select GENERIC_IRQ_PROBE <<
63 select GENERIC_IRQ_SHOW <<
64 select GENERIC_IRQ_MULTI_HANDLER <<
65 select GENERIC_SCHED_CLOCK <<
66 select GENERIC_SMP_IDLE_THREAD 47 select GENERIC_SMP_IDLE_THREAD
>> 48 select GENERIC_IDLE_POLL_SETUP
67 select GENERIC_TIME_VSYSCALL 49 select GENERIC_TIME_VSYSCALL
68 select GENERIC_VDSO_32 !! 50 select GUP_GET_PXX_LOW_HIGH if CPU_MIPS32 && PHYS_ADDR_T_64BIT
69 select GENERIC_GETTIMEOFDAY !! 51 select HAS_IOPORT if !NO_IOPORT_MAP || ISA
70 select GX6605S_TIMER if CPU_CK610 !! 52 select HAVE_ARCH_COMPILER_H
71 select HAVE_ARCH_TRACEHOOK !! 53 select HAVE_ARCH_JUMP_LABEL
72 select HAVE_ARCH_AUDITSYSCALL !! 54 select HAVE_ARCH_KGDB if MIPS_FP_SUPPORT
73 select HAVE_ARCH_JUMP_LABEL if !CPU_CK !! 55 select HAVE_ARCH_MMAP_RND_BITS if MMU
74 select HAVE_ARCH_JUMP_LABEL_RELATIVE !! 56 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if MMU && COMPAT
75 select HAVE_ARCH_MMAP_RND_BITS <<
76 select HAVE_ARCH_SECCOMP_FILTER 57 select HAVE_ARCH_SECCOMP_FILTER
>> 58 select HAVE_ARCH_TRACEHOOK
>> 59 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES
>> 60 select HAVE_ASM_MODVERSIONS
77 select HAVE_CONTEXT_TRACKING_USER 61 select HAVE_CONTEXT_TRACKING_USER
78 select HAVE_VIRT_CPU_ACCOUNTING_GEN !! 62 select HAVE_TIF_NOHZ
79 select HAVE_DEBUG_BUGVERBOSE !! 63 select HAVE_C_RECORDMCOUNT
80 select HAVE_DEBUG_KMEMLEAK 64 select HAVE_DEBUG_KMEMLEAK
>> 65 select HAVE_DEBUG_STACKOVERFLOW
>> 66 select HAVE_DMA_CONTIGUOUS
81 select HAVE_DYNAMIC_FTRACE 67 select HAVE_DYNAMIC_FTRACE
82 select HAVE_DYNAMIC_FTRACE_WITH_REGS !! 68 select HAVE_EBPF_JIT if !CPU_MICROMIPS
83 select HAVE_GENERIC_VDSO !! 69 select HAVE_EXIT_THREAD
84 select HAVE_FUNCTION_TRACER !! 70 select HAVE_FAST_GUP
85 select HAVE_FUNCTION_GRAPH_TRACER <<
86 select HAVE_FUNCTION_ERROR_INJECTION <<
87 select HAVE_FTRACE_MCOUNT_RECORD 71 select HAVE_FTRACE_MCOUNT_RECORD
88 select HAVE_KERNEL_GZIP !! 72 select HAVE_FUNCTION_GRAPH_TRACER
89 select HAVE_KERNEL_LZO !! 73 select HAVE_FUNCTION_TRACER
90 select HAVE_KERNEL_LZMA !! 74 select HAVE_GCC_PLUGINS
91 select HAVE_KPROBES if !CPU_CK610 !! 75 select HAVE_GENERIC_VDSO
92 select HAVE_KPROBES_ON_FTRACE if !CPU_ !! 76 select HAVE_IOREMAP_PROT
93 select HAVE_KRETPROBES if !CPU_CK610 !! 77 select HAVE_IRQ_EXIT_ON_IRQ_STACK
94 select HAVE_PAGE_SIZE_4KB !! 78 select HAVE_IRQ_TIME_ACCOUNTING
>> 79 select HAVE_KPROBES
>> 80 select HAVE_KRETPROBES
>> 81 select HAVE_LD_DEAD_CODE_DATA_ELIMINATION
>> 82 select HAVE_MOD_ARCH_SPECIFIC
>> 83 select HAVE_NMI
95 select HAVE_PERF_EVENTS 84 select HAVE_PERF_EVENTS
96 select HAVE_PERF_REGS 85 select HAVE_PERF_REGS
97 select HAVE_PERF_USER_STACK_DUMP 86 select HAVE_PERF_USER_STACK_DUMP
98 select HAVE_DMA_CONTIGUOUS <<
99 select HAVE_REGS_AND_STACK_ACCESS_API 87 select HAVE_REGS_AND_STACK_ACCESS_API
>> 88 select HAVE_RSEQ
>> 89 select HAVE_SPARSE_SYSCALL_NR
100 select HAVE_STACKPROTECTOR 90 select HAVE_STACKPROTECTOR
101 select HAVE_SYSCALL_TRACEPOINTS 91 select HAVE_SYSCALL_TRACEPOINTS
102 select HOTPLUG_CORE_SYNC_DEAD if HOTPL !! 92 select HAVE_VIRT_CPU_ACCOUNTING_GEN if 64BIT || !SMP
>> 93 select IRQ_FORCED_THREADING
>> 94 select ISA if EISA
103 select LOCK_MM_AND_FIND_VMA 95 select LOCK_MM_AND_FIND_VMA
104 select MAY_HAVE_SPARSE_IRQ !! 96 select MODULES_USE_ELF_REL if MODULES
105 select MODULES_USE_ELF_RELA if MODULES !! 97 select MODULES_USE_ELF_RELA if MODULES && 64BIT
106 select OF !! 98 select PERF_USE_VMALLOC
107 select OF_EARLY_FLATTREE !! 99 select PCI_MSI_ARCH_FALLBACKS if PCI_MSI
108 select PERF_USE_VMALLOC if CPU_CK610 <<
109 select RTC_LIB 100 select RTC_LIB
110 select TIMER_OF !! 101 select SYSCTL_EXCEPTION_TRACE
111 select GENERIC_PCI_IOMAP <<
112 select HAVE_PCI <<
113 select PCI_DOMAINS_GENERIC if PCI <<
114 select PCI_SYSCALL if PCI <<
115 select PCI_MSI if PCI <<
116 select TRACE_IRQFLAGS_SUPPORT 102 select TRACE_IRQFLAGS_SUPPORT
>> 103 select ARCH_HAS_ELFCORE_COMPAT
>> 104 select HAVE_ARCH_KCSAN if 64BIT
117 105
118 config LOCKDEP_SUPPORT !! 106 config MIPS_FIXUP_BIGPHYS_ADDR
119 def_bool y !! 107 bool
120 108
121 config ARCH_SUPPORTS_UPROBES !! 109 config MIPS_GENERIC
122 def_bool y if !CPU_CK610 !! 110 bool
>> 111
>> 112 config MACH_INGENIC
>> 113 bool
>> 114 select SYS_SUPPORTS_32BIT_KERNEL
>> 115 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 116 select SYS_SUPPORTS_ZBOOT
>> 117 select DMA_NONCOHERENT
>> 118 select IRQ_MIPS_CPU
>> 119 select PINCTRL
>> 120 select GPIOLIB
>> 121 select COMMON_CLK
>> 122 select GENERIC_IRQ_CHIP
>> 123 select BUILTIN_DTB if MIPS_NO_APPENDED_DTB
>> 124 select USE_OF
>> 125 select CPU_SUPPORTS_CPUFREQ
>> 126 select MIPS_EXTERNAL_TIMER
>> 127
>> 128 menu "Machine selection"
>> 129
>> 130 choice
>> 131 prompt "System type"
>> 132 default MIPS_GENERIC_KERNEL
>> 133
>> 134 config MIPS_GENERIC_KERNEL
>> 135 bool "Generic board-agnostic MIPS kernel"
>> 136 select MIPS_GENERIC
>> 137 select BOOT_RAW
>> 138 select BUILTIN_DTB
>> 139 select CEVT_R4K
>> 140 select CLKSRC_MIPS_GIC
>> 141 select COMMON_CLK
>> 142 select CPU_MIPSR2_IRQ_EI
>> 143 select CPU_MIPSR2_IRQ_VI
>> 144 select CSRC_R4K
>> 145 select DMA_NONCOHERENT
>> 146 select HAVE_PCI
>> 147 select IRQ_MIPS_CPU
>> 148 select MIPS_AUTO_PFN_OFFSET
>> 149 select MIPS_CPU_SCACHE
>> 150 select MIPS_GIC
>> 151 select MIPS_L1_CACHE_SHIFT_7
>> 152 select NO_EXCEPT_FILL
>> 153 select PCI_DRIVERS_GENERIC
>> 154 select SMP_UP if SMP
>> 155 select SWAP_IO_SPACE
>> 156 select SYS_HAS_CPU_MIPS32_R1
>> 157 select SYS_HAS_CPU_MIPS32_R2
>> 158 select SYS_HAS_CPU_MIPS32_R5
>> 159 select SYS_HAS_CPU_MIPS32_R6
>> 160 select SYS_HAS_CPU_MIPS64_R1
>> 161 select SYS_HAS_CPU_MIPS64_R2
>> 162 select SYS_HAS_CPU_MIPS64_R5
>> 163 select SYS_HAS_CPU_MIPS64_R6
>> 164 select SYS_SUPPORTS_32BIT_KERNEL
>> 165 select SYS_SUPPORTS_64BIT_KERNEL
>> 166 select SYS_SUPPORTS_BIG_ENDIAN
>> 167 select SYS_SUPPORTS_HIGHMEM
>> 168 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 169 select SYS_SUPPORTS_MICROMIPS
>> 170 select SYS_SUPPORTS_MIPS16
>> 171 select SYS_SUPPORTS_MIPS_CPS
>> 172 select SYS_SUPPORTS_MULTITHREADING
>> 173 select SYS_SUPPORTS_RELOCATABLE
>> 174 select SYS_SUPPORTS_SMARTMIPS
>> 175 select SYS_SUPPORTS_ZBOOT
>> 176 select UHI_BOOT
>> 177 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 178 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 179 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 180 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 181 select USB_UHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 182 select USB_UHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 183 select USE_OF
>> 184 help
>> 185 Select this to build a kernel which aims to support multiple boards,
>> 186 generally using a flattened device tree passed from the bootloader
>> 187 using the boot protocol defined in the UHI (Unified Hosting
>> 188 Interface) specification.
>> 189
>> 190 config MIPS_ALCHEMY
>> 191 bool "Alchemy processor based machines"
>> 192 select PHYS_ADDR_T_64BIT
>> 193 select CEVT_R4K
>> 194 select CSRC_R4K
>> 195 select IRQ_MIPS_CPU
>> 196 select DMA_NONCOHERENT # Au1000,1500,1100 aren't, rest is
>> 197 select MIPS_FIXUP_BIGPHYS_ADDR if PCI
>> 198 select SYS_HAS_CPU_MIPS32_R1
>> 199 select SYS_SUPPORTS_32BIT_KERNEL
>> 200 select SYS_SUPPORTS_APM_EMULATION
>> 201 select GPIOLIB
>> 202 select SYS_SUPPORTS_ZBOOT
>> 203 select COMMON_CLK
>> 204
>> 205 config AR7
>> 206 bool "Texas Instruments AR7"
>> 207 select BOOT_ELF32
>> 208 select COMMON_CLK
>> 209 select DMA_NONCOHERENT
>> 210 select CEVT_R4K
>> 211 select CSRC_R4K
>> 212 select IRQ_MIPS_CPU
>> 213 select NO_EXCEPT_FILL
>> 214 select SWAP_IO_SPACE
>> 215 select SYS_HAS_CPU_MIPS32_R1
>> 216 select SYS_HAS_EARLY_PRINTK
>> 217 select SYS_SUPPORTS_32BIT_KERNEL
>> 218 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 219 select SYS_SUPPORTS_MIPS16
>> 220 select SYS_SUPPORTS_ZBOOT_UART16550
>> 221 select GPIOLIB
>> 222 select VLYNQ
>> 223 help
>> 224 Support for the Texas Instruments AR7 System-on-a-Chip
>> 225 family: TNETD7100, 7200 and 7300.
>> 226
>> 227 config ATH25
>> 228 bool "Atheros AR231x/AR531x SoC support"
>> 229 select CEVT_R4K
>> 230 select CSRC_R4K
>> 231 select DMA_NONCOHERENT
>> 232 select IRQ_MIPS_CPU
>> 233 select IRQ_DOMAIN
>> 234 select SYS_HAS_CPU_MIPS32_R1
>> 235 select SYS_SUPPORTS_BIG_ENDIAN
>> 236 select SYS_SUPPORTS_32BIT_KERNEL
>> 237 select SYS_HAS_EARLY_PRINTK
>> 238 help
>> 239 Support for Atheros AR231x and Atheros AR531x based boards
>> 240
>> 241 config ATH79
>> 242 bool "Atheros AR71XX/AR724X/AR913X based boards"
>> 243 select ARCH_HAS_RESET_CONTROLLER
>> 244 select BOOT_RAW
>> 245 select CEVT_R4K
>> 246 select CSRC_R4K
>> 247 select DMA_NONCOHERENT
>> 248 select GPIOLIB
>> 249 select PINCTRL
>> 250 select COMMON_CLK
>> 251 select IRQ_MIPS_CPU
>> 252 select SYS_HAS_CPU_MIPS32_R2
>> 253 select SYS_HAS_EARLY_PRINTK
>> 254 select SYS_SUPPORTS_32BIT_KERNEL
>> 255 select SYS_SUPPORTS_BIG_ENDIAN
>> 256 select SYS_SUPPORTS_MIPS16
>> 257 select SYS_SUPPORTS_ZBOOT_UART_PROM
>> 258 select USE_OF
>> 259 select USB_EHCI_ROOT_HUB_TT if USB_EHCI_HCD_PLATFORM
>> 260 help
>> 261 Support for the Atheros AR71XX/AR724X/AR913X SoCs.
>> 262
>> 263 config BMIPS_GENERIC
>> 264 bool "Broadcom Generic BMIPS kernel"
>> 265 select ARCH_HAS_RESET_CONTROLLER
>> 266 select ARCH_HAS_SYNC_DMA_FOR_CPU_ALL
>> 267 select BOOT_RAW
>> 268 select NO_EXCEPT_FILL
>> 269 select USE_OF
>> 270 select CEVT_R4K
>> 271 select CSRC_R4K
>> 272 select SYNC_R4K
>> 273 select COMMON_CLK
>> 274 select BCM6345_L1_IRQ
>> 275 select BCM7038_L1_IRQ
>> 276 select BCM7120_L2_IRQ
>> 277 select BRCMSTB_L2_IRQ
>> 278 select IRQ_MIPS_CPU
>> 279 select DMA_NONCOHERENT
>> 280 select SYS_SUPPORTS_32BIT_KERNEL
>> 281 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 282 select SYS_SUPPORTS_BIG_ENDIAN
>> 283 select SYS_SUPPORTS_HIGHMEM
>> 284 select SYS_HAS_CPU_BMIPS32_3300
>> 285 select SYS_HAS_CPU_BMIPS4350
>> 286 select SYS_HAS_CPU_BMIPS4380
>> 287 select SYS_HAS_CPU_BMIPS5000
>> 288 select SWAP_IO_SPACE
>> 289 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 290 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 291 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 292 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 293 select HARDIRQS_SW_RESEND
>> 294 select HAVE_PCI
>> 295 select PCI_DRIVERS_GENERIC
>> 296 select FW_CFE
>> 297 help
>> 298 Build a generic DT-based kernel image that boots on select
>> 299 BCM33xx cable modem chips, BCM63xx DSL chips, and BCM7xxx set-top
>> 300 box chips. Note that CONFIG_CPU_BIG_ENDIAN/CONFIG_CPU_LITTLE_ENDIAN
>> 301 must be set appropriately for your board.
>> 302
>> 303 config BCM47XX
>> 304 bool "Broadcom BCM47XX based boards"
>> 305 select BOOT_RAW
>> 306 select CEVT_R4K
>> 307 select CSRC_R4K
>> 308 select DMA_NONCOHERENT
>> 309 select HAVE_PCI
>> 310 select IRQ_MIPS_CPU
>> 311 select SYS_HAS_CPU_MIPS32_R1
>> 312 select NO_EXCEPT_FILL
>> 313 select SYS_SUPPORTS_32BIT_KERNEL
>> 314 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 315 select SYS_SUPPORTS_MIPS16
>> 316 select SYS_SUPPORTS_ZBOOT
>> 317 select SYS_HAS_EARLY_PRINTK
>> 318 select USE_GENERIC_EARLY_PRINTK_8250
>> 319 select GPIOLIB
>> 320 select LEDS_GPIO_REGISTER
>> 321 select BCM47XX_NVRAM
>> 322 select BCM47XX_SPROM
>> 323 select BCM47XX_SSB if !BCM47XX_BCMA
>> 324 help
>> 325 Support for BCM47XX based boards
>> 326
>> 327 config BCM63XX
>> 328 bool "Broadcom BCM63XX based boards"
>> 329 select BOOT_RAW
>> 330 select CEVT_R4K
>> 331 select CSRC_R4K
>> 332 select SYNC_R4K
>> 333 select DMA_NONCOHERENT
>> 334 select IRQ_MIPS_CPU
>> 335 select SYS_SUPPORTS_32BIT_KERNEL
>> 336 select SYS_SUPPORTS_BIG_ENDIAN
>> 337 select SYS_HAS_EARLY_PRINTK
>> 338 select SYS_HAS_CPU_BMIPS32_3300
>> 339 select SYS_HAS_CPU_BMIPS4350
>> 340 select SYS_HAS_CPU_BMIPS4380
>> 341 select SWAP_IO_SPACE
>> 342 select GPIOLIB
>> 343 select MIPS_L1_CACHE_SHIFT_4
>> 344 select HAVE_LEGACY_CLK
>> 345 help
>> 346 Support for BCM63XX based boards
>> 347
>> 348 config MIPS_COBALT
>> 349 bool "Cobalt Server"
>> 350 select CEVT_R4K
>> 351 select CSRC_R4K
>> 352 select CEVT_GT641XX
>> 353 select DMA_NONCOHERENT
>> 354 select FORCE_PCI
>> 355 select I8253
>> 356 select I8259
>> 357 select IRQ_MIPS_CPU
>> 358 select IRQ_GT641XX
>> 359 select PCI_GT64XXX_PCI0
>> 360 select SYS_HAS_CPU_NEVADA
>> 361 select SYS_HAS_EARLY_PRINTK
>> 362 select SYS_SUPPORTS_32BIT_KERNEL
>> 363 select SYS_SUPPORTS_64BIT_KERNEL
>> 364 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 365 select USE_GENERIC_EARLY_PRINTK_8250
>> 366
>> 367 config MACH_DECSTATION
>> 368 bool "DECstations"
>> 369 select BOOT_ELF32
>> 370 select CEVT_DS1287
>> 371 select CEVT_R4K if CPU_R4X00
>> 372 select CSRC_IOASIC
>> 373 select CSRC_R4K if CPU_R4X00
>> 374 select CPU_DADDI_WORKAROUNDS if 64BIT
>> 375 select CPU_R4000_WORKAROUNDS if 64BIT
>> 376 select CPU_R4400_WORKAROUNDS if 64BIT
>> 377 select DMA_NONCOHERENT
>> 378 select NO_IOPORT_MAP
>> 379 select IRQ_MIPS_CPU
>> 380 select SYS_HAS_CPU_R3000
>> 381 select SYS_HAS_CPU_R4X00
>> 382 select SYS_SUPPORTS_32BIT_KERNEL
>> 383 select SYS_SUPPORTS_64BIT_KERNEL
>> 384 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 385 select SYS_SUPPORTS_128HZ
>> 386 select SYS_SUPPORTS_256HZ
>> 387 select SYS_SUPPORTS_1024HZ
>> 388 select MIPS_L1_CACHE_SHIFT_4
>> 389 help
>> 390 This enables support for DEC's MIPS based workstations. For details
>> 391 see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the
>> 392 DECstation porting pages on <http://decstation.unix-ag.org/>.
>> 393
>> 394 If you have one of the following DECstation Models you definitely
>> 395 want to choose R4xx0 for the CPU Type:
>> 396
>> 397 DECstation 5000/50
>> 398 DECstation 5000/150
>> 399 DECstation 5000/260
>> 400 DECsystem 5900/260
>> 401
>> 402 otherwise choose R3000.
>> 403
>> 404 config MACH_JAZZ
>> 405 bool "Jazz family of machines"
>> 406 select ARC_MEMORY
>> 407 select ARC_PROMLIB
>> 408 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 409 select ARCH_MIGHT_HAVE_PC_SERIO
>> 410 select DMA_OPS
>> 411 select FW_ARC
>> 412 select FW_ARC32
>> 413 select ARCH_MAY_HAVE_PC_FDC
>> 414 select CEVT_R4K
>> 415 select CSRC_R4K
>> 416 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 417 select GENERIC_ISA_DMA
>> 418 select HAVE_PCSPKR_PLATFORM
>> 419 select IRQ_MIPS_CPU
>> 420 select I8253
>> 421 select I8259
>> 422 select ISA
>> 423 select SYS_HAS_CPU_R4X00
>> 424 select SYS_SUPPORTS_32BIT_KERNEL
>> 425 select SYS_SUPPORTS_64BIT_KERNEL
>> 426 select SYS_SUPPORTS_100HZ
>> 427 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 428 help
>> 429 This a family of machines based on the MIPS R4030 chipset which was
>> 430 used by several vendors to build RISC/os and Windows NT workstations.
>> 431 Members include the Acer PICA, MIPS Magnum 4000, MIPS Millennium and
>> 432 Olivetti M700-10 workstations.
>> 433
>> 434 config MACH_INGENIC_SOC
>> 435 bool "Ingenic SoC based machines"
>> 436 select MIPS_GENERIC
>> 437 select MACH_INGENIC
>> 438 select SYS_SUPPORTS_ZBOOT_UART16550
>> 439 select CPU_SUPPORTS_CPUFREQ
>> 440 select MIPS_EXTERNAL_TIMER
>> 441
>> 442 config LANTIQ
>> 443 bool "Lantiq based platforms"
>> 444 select DMA_NONCOHERENT
>> 445 select IRQ_MIPS_CPU
>> 446 select CEVT_R4K
>> 447 select CSRC_R4K
>> 448 select NO_EXCEPT_FILL
>> 449 select SYS_HAS_CPU_MIPS32_R1
>> 450 select SYS_HAS_CPU_MIPS32_R2
>> 451 select SYS_SUPPORTS_BIG_ENDIAN
>> 452 select SYS_SUPPORTS_32BIT_KERNEL
>> 453 select SYS_SUPPORTS_MIPS16
>> 454 select SYS_SUPPORTS_MULTITHREADING
>> 455 select SYS_SUPPORTS_VPE_LOADER
>> 456 select SYS_HAS_EARLY_PRINTK
>> 457 select GPIOLIB
>> 458 select SWAP_IO_SPACE
>> 459 select BOOT_RAW
>> 460 select HAVE_LEGACY_CLK
>> 461 select USE_OF
>> 462 select PINCTRL
>> 463 select PINCTRL_LANTIQ
>> 464 select ARCH_HAS_RESET_CONTROLLER
>> 465 select RESET_CONTROLLER
>> 466
>> 467 config MACH_LOONGSON32
>> 468 bool "Loongson 32-bit family of machines"
>> 469 select SYS_SUPPORTS_ZBOOT
>> 470 help
>> 471 This enables support for the Loongson-1 family of machines.
>> 472
>> 473 Loongson-1 is a family of 32-bit MIPS-compatible SoCs developed by
>> 474 the Institute of Computing Technology (ICT), Chinese Academy of
>> 475 Sciences (CAS).
>> 476
>> 477 config MACH_LOONGSON2EF
>> 478 bool "Loongson-2E/F family of machines"
>> 479 select SYS_SUPPORTS_ZBOOT
>> 480 help
>> 481 This enables the support of early Loongson-2E/F family of machines.
>> 482
>> 483 config MACH_LOONGSON64
>> 484 bool "Loongson 64-bit family of machines"
>> 485 select ARCH_SPARSEMEM_ENABLE
>> 486 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 487 select ARCH_MIGHT_HAVE_PC_SERIO
>> 488 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 489 select BOOT_ELF32
>> 490 select BOARD_SCACHE
>> 491 select CSRC_R4K
>> 492 select CEVT_R4K
>> 493 select FORCE_PCI
>> 494 select ISA
>> 495 select I8259
>> 496 select IRQ_MIPS_CPU
>> 497 select NO_EXCEPT_FILL
>> 498 select NR_CPUS_DEFAULT_64
>> 499 select USE_GENERIC_EARLY_PRINTK_8250
>> 500 select PCI_DRIVERS_GENERIC
>> 501 select SYS_HAS_CPU_LOONGSON64
>> 502 select SYS_HAS_EARLY_PRINTK
>> 503 select SYS_SUPPORTS_SMP
>> 504 select SYS_SUPPORTS_HOTPLUG_CPU
>> 505 select SYS_SUPPORTS_NUMA
>> 506 select SYS_SUPPORTS_64BIT_KERNEL
>> 507 select SYS_SUPPORTS_HIGHMEM
>> 508 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 509 select SYS_SUPPORTS_ZBOOT
>> 510 select SYS_SUPPORTS_RELOCATABLE
>> 511 select ZONE_DMA32
>> 512 select COMMON_CLK
>> 513 select USE_OF
>> 514 select BUILTIN_DTB
>> 515 select PCI_HOST_GENERIC
>> 516 select HAVE_ARCH_NODEDATA_EXTENSION if NUMA
>> 517 help
>> 518 This enables the support of Loongson-2/3 family of machines.
>> 519
>> 520 Loongson-2 and Loongson-3 are 64-bit general-purpose processors with
>> 521 GS264/GS464/GS464E/GS464V microarchitecture (except old Loongson-2E
>> 522 and Loongson-2F which will be removed), developed by the Institute
>> 523 of Computing Technology (ICT), Chinese Academy of Sciences (CAS).
>> 524
>> 525 config MIPS_MALTA
>> 526 bool "MIPS Malta board"
>> 527 select ARCH_MAY_HAVE_PC_FDC
>> 528 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 529 select ARCH_MIGHT_HAVE_PC_SERIO
>> 530 select BOOT_ELF32
>> 531 select BOOT_RAW
>> 532 select BUILTIN_DTB
>> 533 select CEVT_R4K
>> 534 select CLKSRC_MIPS_GIC
>> 535 select COMMON_CLK
>> 536 select CSRC_R4K
>> 537 select DMA_NONCOHERENT
>> 538 select GENERIC_ISA_DMA
>> 539 select HAVE_PCSPKR_PLATFORM
>> 540 select HAVE_PCI
>> 541 select I8253
>> 542 select I8259
>> 543 select IRQ_MIPS_CPU
>> 544 select MIPS_BONITO64
>> 545 select MIPS_CPU_SCACHE
>> 546 select MIPS_GIC
>> 547 select MIPS_L1_CACHE_SHIFT_6
>> 548 select MIPS_MSC
>> 549 select PCI_GT64XXX_PCI0
>> 550 select SMP_UP if SMP
>> 551 select SWAP_IO_SPACE
>> 552 select SYS_HAS_CPU_MIPS32_R1
>> 553 select SYS_HAS_CPU_MIPS32_R2
>> 554 select SYS_HAS_CPU_MIPS32_R3_5
>> 555 select SYS_HAS_CPU_MIPS32_R5
>> 556 select SYS_HAS_CPU_MIPS32_R6
>> 557 select SYS_HAS_CPU_MIPS64_R1
>> 558 select SYS_HAS_CPU_MIPS64_R2
>> 559 select SYS_HAS_CPU_MIPS64_R6
>> 560 select SYS_HAS_CPU_NEVADA
>> 561 select SYS_HAS_CPU_RM7000
>> 562 select SYS_SUPPORTS_32BIT_KERNEL
>> 563 select SYS_SUPPORTS_64BIT_KERNEL
>> 564 select SYS_SUPPORTS_BIG_ENDIAN
>> 565 select SYS_SUPPORTS_HIGHMEM
>> 566 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 567 select SYS_SUPPORTS_MICROMIPS
>> 568 select SYS_SUPPORTS_MIPS16
>> 569 select SYS_SUPPORTS_MIPS_CPS
>> 570 select SYS_SUPPORTS_MULTITHREADING
>> 571 select SYS_SUPPORTS_RELOCATABLE
>> 572 select SYS_SUPPORTS_SMARTMIPS
>> 573 select SYS_SUPPORTS_VPE_LOADER
>> 574 select SYS_SUPPORTS_ZBOOT
>> 575 select USE_OF
>> 576 select WAR_ICACHE_REFILLS
>> 577 select ZONE_DMA32 if 64BIT
>> 578 help
>> 579 This enables support for the MIPS Technologies Malta evaluation
>> 580 board.
>> 581
>> 582 config MACH_PIC32
>> 583 bool "Microchip PIC32 Family"
>> 584 help
>> 585 This enables support for the Microchip PIC32 family of platforms.
>> 586
>> 587 Microchip PIC32 is a family of general-purpose 32 bit MIPS core
>> 588 microcontrollers.
>> 589
>> 590 config MACH_NINTENDO64
>> 591 bool "Nintendo 64 console"
>> 592 select CEVT_R4K
>> 593 select CSRC_R4K
>> 594 select SYS_HAS_CPU_R4300
>> 595 select SYS_SUPPORTS_BIG_ENDIAN
>> 596 select SYS_SUPPORTS_ZBOOT
>> 597 select SYS_SUPPORTS_32BIT_KERNEL
>> 598 select SYS_SUPPORTS_64BIT_KERNEL
>> 599 select DMA_NONCOHERENT
>> 600 select IRQ_MIPS_CPU
>> 601
>> 602 config RALINK
>> 603 bool "Ralink based machines"
>> 604 select CEVT_R4K
>> 605 select COMMON_CLK
>> 606 select CSRC_R4K
>> 607 select BOOT_RAW
>> 608 select DMA_NONCOHERENT
>> 609 select IRQ_MIPS_CPU
>> 610 select USE_OF
>> 611 select SYS_HAS_CPU_MIPS32_R2
>> 612 select SYS_SUPPORTS_32BIT_KERNEL
>> 613 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 614 select SYS_SUPPORTS_MIPS16
>> 615 select SYS_SUPPORTS_ZBOOT
>> 616 select SYS_HAS_EARLY_PRINTK
>> 617 select ARCH_HAS_RESET_CONTROLLER
>> 618 select RESET_CONTROLLER
>> 619
>> 620 config MACH_REALTEK_RTL
>> 621 bool "Realtek RTL838x/RTL839x based machines"
>> 622 select MIPS_GENERIC
>> 623 select DMA_NONCOHERENT
>> 624 select IRQ_MIPS_CPU
>> 625 select CSRC_R4K
>> 626 select CEVT_R4K
>> 627 select SYS_HAS_CPU_MIPS32_R1
>> 628 select SYS_HAS_CPU_MIPS32_R2
>> 629 select SYS_SUPPORTS_BIG_ENDIAN
>> 630 select SYS_SUPPORTS_32BIT_KERNEL
>> 631 select SYS_SUPPORTS_MIPS16
>> 632 select SYS_SUPPORTS_MULTITHREADING
>> 633 select SYS_SUPPORTS_VPE_LOADER
>> 634 select BOOT_RAW
>> 635 select PINCTRL
>> 636 select USE_OF
>> 637
>> 638 config SGI_IP22
>> 639 bool "SGI IP22 (Indy/Indigo2)"
>> 640 select ARC_MEMORY
>> 641 select ARC_PROMLIB
>> 642 select FW_ARC
>> 643 select FW_ARC32
>> 644 select ARCH_MIGHT_HAVE_PC_SERIO
>> 645 select BOOT_ELF32
>> 646 select CEVT_R4K
>> 647 select CSRC_R4K
>> 648 select DEFAULT_SGI_PARTITION
>> 649 select DMA_NONCOHERENT
>> 650 select HAVE_EISA
>> 651 select I8253
>> 652 select I8259
>> 653 select IP22_CPU_SCACHE
>> 654 select IRQ_MIPS_CPU
>> 655 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 656 select SGI_HAS_I8042
>> 657 select SGI_HAS_INDYDOG
>> 658 select SGI_HAS_HAL2
>> 659 select SGI_HAS_SEEQ
>> 660 select SGI_HAS_WD93
>> 661 select SGI_HAS_ZILOG
>> 662 select SWAP_IO_SPACE
>> 663 select SYS_HAS_CPU_R4X00
>> 664 select SYS_HAS_CPU_R5000
>> 665 select SYS_HAS_EARLY_PRINTK
>> 666 select SYS_SUPPORTS_32BIT_KERNEL
>> 667 select SYS_SUPPORTS_64BIT_KERNEL
>> 668 select SYS_SUPPORTS_BIG_ENDIAN
>> 669 select WAR_R4600_V1_INDEX_ICACHEOP
>> 670 select WAR_R4600_V1_HIT_CACHEOP
>> 671 select WAR_R4600_V2_HIT_CACHEOP
>> 672 select MIPS_L1_CACHE_SHIFT_7
>> 673 help
>> 674 This are the SGI Indy, Challenge S and Indigo2, as well as certain
>> 675 OEM variants like the Tandem CMN B006S. To compile a Linux kernel
>> 676 that runs on these, say Y here.
>> 677
>> 678 config SGI_IP27
>> 679 bool "SGI IP27 (Origin200/2000)"
>> 680 select ARCH_HAS_PHYS_TO_DMA
>> 681 select ARCH_SPARSEMEM_ENABLE
>> 682 select FW_ARC
>> 683 select FW_ARC64
>> 684 select ARC_CMDLINE_ONLY
>> 685 select BOOT_ELF64
>> 686 select DEFAULT_SGI_PARTITION
>> 687 select FORCE_PCI
>> 688 select SYS_HAS_EARLY_PRINTK
>> 689 select HAVE_PCI
>> 690 select IRQ_MIPS_CPU
>> 691 select IRQ_DOMAIN_HIERARCHY
>> 692 select NR_CPUS_DEFAULT_64
>> 693 select PCI_DRIVERS_GENERIC
>> 694 select PCI_XTALK_BRIDGE
>> 695 select SYS_HAS_CPU_R10000
>> 696 select SYS_SUPPORTS_64BIT_KERNEL
>> 697 select SYS_SUPPORTS_BIG_ENDIAN
>> 698 select SYS_SUPPORTS_NUMA
>> 699 select SYS_SUPPORTS_SMP
>> 700 select WAR_R10000_LLSC
>> 701 select MIPS_L1_CACHE_SHIFT_7
>> 702 select NUMA
>> 703 select HAVE_ARCH_NODEDATA_EXTENSION
>> 704 help
>> 705 This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics
>> 706 workstations. To compile a Linux kernel that runs on these, say Y
>> 707 here.
>> 708
>> 709 config SGI_IP28
>> 710 bool "SGI IP28 (Indigo2 R10k)"
>> 711 select ARC_MEMORY
>> 712 select ARC_PROMLIB
>> 713 select FW_ARC
>> 714 select FW_ARC64
>> 715 select ARCH_MIGHT_HAVE_PC_SERIO
>> 716 select BOOT_ELF64
>> 717 select CEVT_R4K
>> 718 select CSRC_R4K
>> 719 select DEFAULT_SGI_PARTITION
>> 720 select DMA_NONCOHERENT
>> 721 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 722 select IRQ_MIPS_CPU
>> 723 select HAVE_EISA
>> 724 select I8253
>> 725 select I8259
>> 726 select SGI_HAS_I8042
>> 727 select SGI_HAS_INDYDOG
>> 728 select SGI_HAS_HAL2
>> 729 select SGI_HAS_SEEQ
>> 730 select SGI_HAS_WD93
>> 731 select SGI_HAS_ZILOG
>> 732 select SWAP_IO_SPACE
>> 733 select SYS_HAS_CPU_R10000
>> 734 select SYS_HAS_EARLY_PRINTK
>> 735 select SYS_SUPPORTS_64BIT_KERNEL
>> 736 select SYS_SUPPORTS_BIG_ENDIAN
>> 737 select WAR_R10000_LLSC
>> 738 select MIPS_L1_CACHE_SHIFT_7
>> 739 help
>> 740 This is the SGI Indigo2 with R10000 processor. To compile a Linux
>> 741 kernel that runs on these, say Y here.
>> 742
>> 743 config SGI_IP30
>> 744 bool "SGI IP30 (Octane/Octane2)"
>> 745 select ARCH_HAS_PHYS_TO_DMA
>> 746 select FW_ARC
>> 747 select FW_ARC64
>> 748 select BOOT_ELF64
>> 749 select CEVT_R4K
>> 750 select CSRC_R4K
>> 751 select FORCE_PCI
>> 752 select SYNC_R4K if SMP
>> 753 select ZONE_DMA32
>> 754 select HAVE_PCI
>> 755 select IRQ_MIPS_CPU
>> 756 select IRQ_DOMAIN_HIERARCHY
>> 757 select PCI_DRIVERS_GENERIC
>> 758 select PCI_XTALK_BRIDGE
>> 759 select SYS_HAS_EARLY_PRINTK
>> 760 select SYS_HAS_CPU_R10000
>> 761 select SYS_SUPPORTS_64BIT_KERNEL
>> 762 select SYS_SUPPORTS_BIG_ENDIAN
>> 763 select SYS_SUPPORTS_SMP
>> 764 select WAR_R10000_LLSC
>> 765 select MIPS_L1_CACHE_SHIFT_7
>> 766 select ARC_MEMORY
>> 767 help
>> 768 These are the SGI Octane and Octane2 graphics workstations. To
>> 769 compile a Linux kernel that runs on these, say Y here.
>> 770
>> 771 config SGI_IP32
>> 772 bool "SGI IP32 (O2)"
>> 773 select ARC_MEMORY
>> 774 select ARC_PROMLIB
>> 775 select ARCH_HAS_PHYS_TO_DMA
>> 776 select FW_ARC
>> 777 select FW_ARC32
>> 778 select BOOT_ELF32
>> 779 select CEVT_R4K
>> 780 select CSRC_R4K
>> 781 select DMA_NONCOHERENT
>> 782 select HAVE_PCI
>> 783 select IRQ_MIPS_CPU
>> 784 select R5000_CPU_SCACHE
>> 785 select RM7000_CPU_SCACHE
>> 786 select SYS_HAS_CPU_R5000
>> 787 select SYS_HAS_CPU_R10000 if BROKEN
>> 788 select SYS_HAS_CPU_RM7000
>> 789 select SYS_HAS_CPU_NEVADA
>> 790 select SYS_SUPPORTS_64BIT_KERNEL
>> 791 select SYS_SUPPORTS_BIG_ENDIAN
>> 792 select WAR_ICACHE_REFILLS
>> 793 help
>> 794 If you want this kernel to run on SGI O2 workstation, say Y here.
>> 795
>> 796 config SIBYTE_CRHONE
>> 797 bool "Sibyte BCM91125C-CRhone"
>> 798 select BOOT_ELF32
>> 799 select SIBYTE_BCM1125
>> 800 select SWAP_IO_SPACE
>> 801 select SYS_HAS_CPU_SB1
>> 802 select SYS_SUPPORTS_BIG_ENDIAN
>> 803 select SYS_SUPPORTS_HIGHMEM
>> 804 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 805
>> 806 config SIBYTE_RHONE
>> 807 bool "Sibyte BCM91125E-Rhone"
>> 808 select BOOT_ELF32
>> 809 select SIBYTE_SB1250
>> 810 select SWAP_IO_SPACE
>> 811 select SYS_HAS_CPU_SB1
>> 812 select SYS_SUPPORTS_BIG_ENDIAN
>> 813 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 814
>> 815 config SIBYTE_SWARM
>> 816 bool "Sibyte BCM91250A-SWARM"
>> 817 select BOOT_ELF32
>> 818 select HAVE_PATA_PLATFORM
>> 819 select SIBYTE_SB1250
>> 820 select SWAP_IO_SPACE
>> 821 select SYS_HAS_CPU_SB1
>> 822 select SYS_SUPPORTS_BIG_ENDIAN
>> 823 select SYS_SUPPORTS_HIGHMEM
>> 824 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 825 select ZONE_DMA32 if 64BIT
>> 826 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 827
>> 828 config SIBYTE_LITTLESUR
>> 829 bool "Sibyte BCM91250C2-LittleSur"
>> 830 select BOOT_ELF32
>> 831 select HAVE_PATA_PLATFORM
>> 832 select SIBYTE_SB1250
>> 833 select SWAP_IO_SPACE
>> 834 select SYS_HAS_CPU_SB1
>> 835 select SYS_SUPPORTS_BIG_ENDIAN
>> 836 select SYS_SUPPORTS_HIGHMEM
>> 837 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 838 select ZONE_DMA32 if 64BIT
>> 839
>> 840 config SIBYTE_SENTOSA
>> 841 bool "Sibyte BCM91250E-Sentosa"
>> 842 select BOOT_ELF32
>> 843 select SIBYTE_SB1250
>> 844 select SWAP_IO_SPACE
>> 845 select SYS_HAS_CPU_SB1
>> 846 select SYS_SUPPORTS_BIG_ENDIAN
>> 847 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 848 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 849
>> 850 config SIBYTE_BIGSUR
>> 851 bool "Sibyte BCM91480B-BigSur"
>> 852 select BOOT_ELF32
>> 853 select NR_CPUS_DEFAULT_4
>> 854 select SIBYTE_BCM1x80
>> 855 select SWAP_IO_SPACE
>> 856 select SYS_HAS_CPU_SB1
>> 857 select SYS_SUPPORTS_BIG_ENDIAN
>> 858 select SYS_SUPPORTS_HIGHMEM
>> 859 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 860 select ZONE_DMA32 if 64BIT
>> 861 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 862
>> 863 config SNI_RM
>> 864 bool "SNI RM200/300/400"
>> 865 select ARC_MEMORY
>> 866 select ARC_PROMLIB
>> 867 select FW_ARC if CPU_LITTLE_ENDIAN
>> 868 select FW_ARC32 if CPU_LITTLE_ENDIAN
>> 869 select FW_SNIPROM if CPU_BIG_ENDIAN
>> 870 select ARCH_MAY_HAVE_PC_FDC
>> 871 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 872 select ARCH_MIGHT_HAVE_PC_SERIO
>> 873 select BOOT_ELF32
>> 874 select CEVT_R4K
>> 875 select CSRC_R4K
>> 876 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 877 select DMA_NONCOHERENT
>> 878 select GENERIC_ISA_DMA
>> 879 select HAVE_EISA
>> 880 select HAVE_PCSPKR_PLATFORM
>> 881 select HAVE_PCI
>> 882 select IRQ_MIPS_CPU
>> 883 select I8253
>> 884 select I8259
>> 885 select ISA
>> 886 select MIPS_L1_CACHE_SHIFT_6
>> 887 select SWAP_IO_SPACE if CPU_BIG_ENDIAN
>> 888 select SYS_HAS_CPU_R4X00
>> 889 select SYS_HAS_CPU_R5000
>> 890 select SYS_HAS_CPU_R10000
>> 891 select R5000_CPU_SCACHE
>> 892 select SYS_HAS_EARLY_PRINTK
>> 893 select SYS_SUPPORTS_32BIT_KERNEL
>> 894 select SYS_SUPPORTS_64BIT_KERNEL
>> 895 select SYS_SUPPORTS_BIG_ENDIAN
>> 896 select SYS_SUPPORTS_HIGHMEM
>> 897 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 898 select WAR_R4600_V2_HIT_CACHEOP
>> 899 help
>> 900 The SNI RM200/300/400 are MIPS-based machines manufactured by
>> 901 Siemens Nixdorf Informationssysteme (SNI), parent company of Pyramid
>> 902 Technology and now in turn merged with Fujitsu. Say Y here to
>> 903 support this machine type.
>> 904
>> 905 config MACH_TX49XX
>> 906 bool "Toshiba TX49 series based machines"
>> 907 select WAR_TX49XX_ICACHE_INDEX_INV
>> 908
>> 909 config MIKROTIK_RB532
>> 910 bool "Mikrotik RB532 boards"
>> 911 select CEVT_R4K
>> 912 select CSRC_R4K
>> 913 select DMA_NONCOHERENT
>> 914 select HAVE_PCI
>> 915 select IRQ_MIPS_CPU
>> 916 select SYS_HAS_CPU_MIPS32_R1
>> 917 select SYS_SUPPORTS_32BIT_KERNEL
>> 918 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 919 select SWAP_IO_SPACE
>> 920 select BOOT_RAW
>> 921 select GPIOLIB
>> 922 select MIPS_L1_CACHE_SHIFT_4
>> 923 help
>> 924 Support the Mikrotik(tm) RouterBoard 532 series,
>> 925 based on the IDT RC32434 SoC.
>> 926
>> 927 config CAVIUM_OCTEON_SOC
>> 928 bool "Cavium Networks Octeon SoC based boards"
>> 929 select CEVT_R4K
>> 930 select ARCH_HAS_PHYS_TO_DMA
>> 931 select HAVE_RAPIDIO
>> 932 select PHYS_ADDR_T_64BIT
>> 933 select SYS_SUPPORTS_64BIT_KERNEL
>> 934 select SYS_SUPPORTS_BIG_ENDIAN
>> 935 select EDAC_SUPPORT
>> 936 select EDAC_ATOMIC_SCRUB
>> 937 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 938 select SYS_SUPPORTS_HOTPLUG_CPU if CPU_BIG_ENDIAN
>> 939 select SYS_HAS_EARLY_PRINTK
>> 940 select SYS_HAS_CPU_CAVIUM_OCTEON
>> 941 select HAVE_PCI
>> 942 select HAVE_PLAT_DELAY
>> 943 select HAVE_PLAT_FW_INIT_CMDLINE
>> 944 select HAVE_PLAT_MEMCPY
>> 945 select ZONE_DMA32
>> 946 select GPIOLIB
>> 947 select USE_OF
>> 948 select ARCH_SPARSEMEM_ENABLE
>> 949 select SYS_SUPPORTS_SMP
>> 950 select NR_CPUS_DEFAULT_64
>> 951 select MIPS_NR_CPU_NR_MAP_1024
>> 952 select BUILTIN_DTB
>> 953 select MTD
>> 954 select MTD_COMPLEX_MAPPINGS
>> 955 select SWIOTLB
>> 956 select SYS_SUPPORTS_RELOCATABLE
>> 957 help
>> 958 This option supports all of the Octeon reference boards from Cavium
>> 959 Networks. It builds a kernel that dynamically determines the Octeon
>> 960 CPU type and supports all known board reference implementations.
>> 961 Some of the supported boards are:
>> 962 EBT3000
>> 963 EBH3000
>> 964 EBH3100
>> 965 Thunder
>> 966 Kodama
>> 967 Hikari
>> 968 Say Y here for most Octeon reference boards.
>> 969
>> 970 endchoice
123 971
124 config CPU_HAS_CACHEV2 !! 972 source "arch/mips/alchemy/Kconfig"
>> 973 source "arch/mips/ath25/Kconfig"
>> 974 source "arch/mips/ath79/Kconfig"
>> 975 source "arch/mips/bcm47xx/Kconfig"
>> 976 source "arch/mips/bcm63xx/Kconfig"
>> 977 source "arch/mips/bmips/Kconfig"
>> 978 source "arch/mips/generic/Kconfig"
>> 979 source "arch/mips/ingenic/Kconfig"
>> 980 source "arch/mips/jazz/Kconfig"
>> 981 source "arch/mips/lantiq/Kconfig"
>> 982 source "arch/mips/pic32/Kconfig"
>> 983 source "arch/mips/ralink/Kconfig"
>> 984 source "arch/mips/sgi-ip27/Kconfig"
>> 985 source "arch/mips/sibyte/Kconfig"
>> 986 source "arch/mips/txx9/Kconfig"
>> 987 source "arch/mips/cavium-octeon/Kconfig"
>> 988 source "arch/mips/loongson2ef/Kconfig"
>> 989 source "arch/mips/loongson32/Kconfig"
>> 990 source "arch/mips/loongson64/Kconfig"
>> 991
>> 992 endmenu
>> 993
>> 994 config GENERIC_HWEIGHT
125 bool 995 bool
>> 996 default y
126 997
127 config CPU_HAS_FPUV2 !! 998 config GENERIC_CALIBRATE_DELAY
128 bool 999 bool
>> 1000 default y
129 1001
130 config CPU_HAS_HILO !! 1002 config SCHED_OMIT_FRAME_POINTER
131 bool 1003 bool
>> 1004 default y
132 1005
133 config CPU_HAS_TLBI !! 1006 #
>> 1007 # Select some configuration options automatically based on user selections.
>> 1008 #
>> 1009 config FW_ARC
134 bool 1010 bool
135 1011
136 config CPU_HAS_LDSTEX !! 1012 config ARCH_MAY_HAVE_PC_FDC
137 bool 1013 bool
138 help <<
139 For SMP, CPU needs "ldex&stex" instr <<
140 1014
141 config CPU_NEED_TLBSYNC !! 1015 config BOOT_RAW
142 bool 1016 bool
143 1017
144 config CPU_NEED_SOFTALIGN !! 1018 config CEVT_BCM1480
145 bool 1019 bool
146 1020
147 config CPU_NO_USER_BKPT !! 1021 config CEVT_DS1287
148 bool 1022 bool
149 help <<
150 For abiv2 we couldn't use "trap 1" a <<
151 abiv2 is 16/32bit instruction set an <<
152 So we need a 16bit instruction as us <<
153 instruction exception. <<
154 In kernel we parse the *regs->pc to <<
155 1023
156 config GENERIC_CALIBRATE_DELAY !! 1024 config CEVT_GT641XX
>> 1025 bool
>> 1026
>> 1027 config CEVT_R4K
>> 1028 bool
>> 1029
>> 1030 config CEVT_SB1250
>> 1031 bool
>> 1032
>> 1033 config CEVT_TXX9
>> 1034 bool
>> 1035
>> 1036 config CSRC_BCM1480
>> 1037 bool
>> 1038
>> 1039 config CSRC_IOASIC
>> 1040 bool
>> 1041
>> 1042 config CSRC_R4K
>> 1043 select CLOCKSOURCE_WATCHDOG if CPU_FREQ
>> 1044 bool
>> 1045
>> 1046 config CSRC_SB1250
>> 1047 bool
>> 1048
>> 1049 config MIPS_CLOCK_VSYSCALL
>> 1050 def_bool CSRC_R4K || CLKSRC_MIPS_GIC
>> 1051
>> 1052 config GPIO_TXX9
>> 1053 select GPIOLIB
>> 1054 bool
>> 1055
>> 1056 config FW_CFE
>> 1057 bool
>> 1058
>> 1059 config ARCH_SUPPORTS_UPROBES
157 def_bool y 1060 def_bool y
158 1061
>> 1062 config DMA_NONCOHERENT
>> 1063 bool
>> 1064 #
>> 1065 # MIPS allows mixing "slightly different" Cacheability and Coherency
>> 1066 # Attribute bits. It is believed that the uncached access through
>> 1067 # KSEG1 and the implementation specific "uncached accelerated" used
>> 1068 # by pgprot_writcombine can be mixed, and the latter sometimes provides
>> 1069 # significant advantages.
>> 1070 #
>> 1071 select ARCH_HAS_SETUP_DMA_OPS
>> 1072 select ARCH_HAS_DMA_WRITE_COMBINE
>> 1073 select ARCH_HAS_DMA_PREP_COHERENT
>> 1074 select ARCH_HAS_SYNC_DMA_FOR_CPU
>> 1075 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
>> 1076 select ARCH_HAS_DMA_SET_UNCACHED
>> 1077 select DMA_NONCOHERENT_MMAP
>> 1078 select NEED_DMA_MAP_STATE
>> 1079
>> 1080 config SYS_HAS_EARLY_PRINTK
>> 1081 bool
>> 1082
>> 1083 config SYS_SUPPORTS_HOTPLUG_CPU
>> 1084 bool
>> 1085
>> 1086 config MIPS_BONITO64
>> 1087 bool
>> 1088
>> 1089 config MIPS_MSC
>> 1090 bool
>> 1091
>> 1092 config SYNC_R4K
>> 1093 bool
>> 1094
>> 1095 config NO_IOPORT_MAP
>> 1096 def_bool n
>> 1097
159 config GENERIC_CSUM 1098 config GENERIC_CSUM
160 def_bool y !! 1099 def_bool CPU_NO_LOAD_STORE_LR
161 1100
162 config GENERIC_HWEIGHT !! 1101 config GENERIC_ISA_DMA
163 def_bool y !! 1102 bool
>> 1103 select ZONE_DMA if GENERIC_ISA_DMA_SUPPORT_BROKEN=n
>> 1104 select ISA_DMA_API
164 1105
165 config MMU !! 1106 config GENERIC_ISA_DMA_SUPPORT_BROKEN
166 def_bool y !! 1107 bool
>> 1108 select GENERIC_ISA_DMA
167 1109
168 config STACKTRACE_SUPPORT !! 1110 config HAVE_PLAT_DELAY
169 def_bool y !! 1111 bool
170 1112
171 config TIME_LOW_RES !! 1113 config HAVE_PLAT_FW_INIT_CMDLINE
172 def_bool y !! 1114 bool
173 1115
174 config CPU_ASID_BITS !! 1116 config HAVE_PLAT_MEMCPY
175 int !! 1117 bool
176 default "8" if (CPU_CK610 || CPU_C !! 1118
177 default "12" if (CPU_CK860) !! 1119 config ISA_DMA_API
>> 1120 bool
>> 1121
>> 1122 config SYS_SUPPORTS_RELOCATABLE
>> 1123 bool
>> 1124 help
>> 1125 Selected if the platform supports relocating the kernel.
>> 1126 The platform must provide plat_get_fdt() if it selects CONFIG_USE_OF
>> 1127 to allow access to command line and entropy sources.
>> 1128
>> 1129 #
>> 1130 # Endianness selection. Sufficiently obscure so many users don't know what to
>> 1131 # answer,so we try hard to limit the available choices. Also the use of a
>> 1132 # choice statement should be more obvious to the user.
>> 1133 #
>> 1134 choice
>> 1135 prompt "Endianness selection"
>> 1136 help
>> 1137 Some MIPS machines can be configured for either little or big endian
>> 1138 byte order. These modes require different kernels and a different
>> 1139 Linux distribution. In general there is one preferred byteorder for a
>> 1140 particular system but some systems are just as commonly used in the
>> 1141 one or the other endianness.
>> 1142
>> 1143 config CPU_BIG_ENDIAN
>> 1144 bool "Big endian"
>> 1145 depends on SYS_SUPPORTS_BIG_ENDIAN
>> 1146
>> 1147 config CPU_LITTLE_ENDIAN
>> 1148 bool "Little endian"
>> 1149 depends on SYS_SUPPORTS_LITTLE_ENDIAN
>> 1150
>> 1151 endchoice
>> 1152
>> 1153 config EXPORT_UASM
>> 1154 bool
>> 1155
>> 1156 config SYS_SUPPORTS_APM_EMULATION
>> 1157 bool
>> 1158
>> 1159 config SYS_SUPPORTS_BIG_ENDIAN
>> 1160 bool
>> 1161
>> 1162 config SYS_SUPPORTS_LITTLE_ENDIAN
>> 1163 bool
>> 1164
>> 1165 config MIPS_HUGE_TLB_SUPPORT
>> 1166 def_bool HUGETLB_PAGE || TRANSPARENT_HUGEPAGE
>> 1167
>> 1168 config IRQ_TXX9
>> 1169 bool
178 1170
179 config L1_CACHE_SHIFT !! 1171 config IRQ_GT641XX
>> 1172 bool
>> 1173
>> 1174 config PCI_GT64XXX_PCI0
>> 1175 bool
>> 1176
>> 1177 config PCI_XTALK_BRIDGE
>> 1178 bool
>> 1179
>> 1180 config NO_EXCEPT_FILL
>> 1181 bool
>> 1182
>> 1183 config MIPS_SPRAM
>> 1184 bool
>> 1185
>> 1186 config SWAP_IO_SPACE
>> 1187 bool
>> 1188
>> 1189 config SGI_HAS_INDYDOG
>> 1190 bool
>> 1191
>> 1192 config SGI_HAS_HAL2
>> 1193 bool
>> 1194
>> 1195 config SGI_HAS_SEEQ
>> 1196 bool
>> 1197
>> 1198 config SGI_HAS_WD93
>> 1199 bool
>> 1200
>> 1201 config SGI_HAS_ZILOG
>> 1202 bool
>> 1203
>> 1204 config SGI_HAS_I8042
>> 1205 bool
>> 1206
>> 1207 config DEFAULT_SGI_PARTITION
>> 1208 bool
>> 1209
>> 1210 config FW_ARC32
>> 1211 bool
>> 1212
>> 1213 config FW_SNIPROM
>> 1214 bool
>> 1215
>> 1216 config BOOT_ELF32
>> 1217 bool
>> 1218
>> 1219 config MIPS_L1_CACHE_SHIFT_4
>> 1220 bool
>> 1221
>> 1222 config MIPS_L1_CACHE_SHIFT_5
>> 1223 bool
>> 1224
>> 1225 config MIPS_L1_CACHE_SHIFT_6
>> 1226 bool
>> 1227
>> 1228 config MIPS_L1_CACHE_SHIFT_7
>> 1229 bool
>> 1230
>> 1231 config MIPS_L1_CACHE_SHIFT
180 int 1232 int
181 default "4" if (CPU_CK610) !! 1233 default "7" if MIPS_L1_CACHE_SHIFT_7
182 default "5" if (CPU_CK807 || CPU_C !! 1234 default "6" if MIPS_L1_CACHE_SHIFT_6
183 default "6" if (CPU_CK860) !! 1235 default "5" if MIPS_L1_CACHE_SHIFT_5
>> 1236 default "4" if MIPS_L1_CACHE_SHIFT_4
>> 1237 default "5"
184 1238
185 config ARCH_MMAP_RND_BITS_MIN !! 1239 config ARC_CMDLINE_ONLY
186 default 8 !! 1240 bool
187 1241
188 # max bits determined by the following formula !! 1242 config ARC_CONSOLE
189 # VA_BITS - PAGE_SHIFT - 3 !! 1243 bool "ARC console support"
190 config ARCH_MMAP_RND_BITS_MAX !! 1244 depends on SGI_IP22 || SGI_IP28 || (SNI_RM && CPU_LITTLE_ENDIAN)
191 default 17 !! 1245
>> 1246 config ARC_MEMORY
>> 1247 bool
192 1248
193 menu "Processor type and features" !! 1249 config ARC_PROMLIB
>> 1250 bool
>> 1251
>> 1252 config FW_ARC64
>> 1253 bool
>> 1254
>> 1255 config BOOT_ELF64
>> 1256 bool
>> 1257
>> 1258 menu "CPU selection"
194 1259
195 choice 1260 choice
196 prompt "CPU MODEL" !! 1261 prompt "CPU type"
197 default CPU_CK807 !! 1262 default CPU_R4X00
>> 1263
>> 1264 config CPU_LOONGSON64
>> 1265 bool "Loongson 64-bit CPU"
>> 1266 depends on SYS_HAS_CPU_LOONGSON64
>> 1267 select ARCH_HAS_PHYS_TO_DMA
>> 1268 select CPU_MIPSR2
>> 1269 select CPU_HAS_PREFETCH
>> 1270 select CPU_SUPPORTS_64BIT_KERNEL
>> 1271 select CPU_SUPPORTS_HIGHMEM
>> 1272 select CPU_SUPPORTS_HUGEPAGES
>> 1273 select CPU_SUPPORTS_MSA
>> 1274 select CPU_DIEI_BROKEN if !LOONGSON3_ENHANCEMENT
>> 1275 select CPU_MIPSR2_IRQ_VI
>> 1276 select WEAK_ORDERING
>> 1277 select WEAK_REORDERING_BEYOND_LLSC
>> 1278 select MIPS_ASID_BITS_VARIABLE
>> 1279 select MIPS_PGD_C0_CONTEXT
>> 1280 select MIPS_L1_CACHE_SHIFT_6
>> 1281 select MIPS_FP_SUPPORT
>> 1282 select GPIOLIB
>> 1283 select SWIOTLB
>> 1284 select HAVE_KVM
>> 1285 help
>> 1286 The Loongson GSx64(GS264/GS464/GS464E/GS464V) series of processor
>> 1287 cores implements the MIPS64R2 instruction set with many extensions,
>> 1288 including most 64-bit Loongson-2 (2H, 2K) and Loongson-3 (3A1000,
>> 1289 3B1000, 3B1500, 3A2000, 3A3000 and 3A4000) processors. However, old
>> 1290 Loongson-2E/2F is not covered here and will be removed in future.
>> 1291
>> 1292 config LOONGSON3_ENHANCEMENT
>> 1293 bool "New Loongson-3 CPU Enhancements"
>> 1294 default n
>> 1295 depends on CPU_LOONGSON64
>> 1296 help
>> 1297 New Loongson-3 cores (since Loongson-3A R2, as opposed to Loongson-3A
>> 1298 R1, Loongson-3B R1 and Loongson-3B R2) has many enhancements, such as
>> 1299 FTLB, L1-VCache, EI/DI/Wait/Prefetch instruction, DSP/DSPr2 ASE, User
>> 1300 Local register, Read-Inhibit/Execute-Inhibit, SFB (Store Fill Buffer),
>> 1301 Fast TLB refill support, etc.
>> 1302
>> 1303 This option enable those enhancements which are not probed at run
>> 1304 time. If you want a generic kernel to run on all Loongson 3 machines,
>> 1305 please say 'N' here. If you want a high-performance kernel to run on
>> 1306 new Loongson-3 machines only, please say 'Y' here.
>> 1307
>> 1308 config CPU_LOONGSON3_WORKAROUNDS
>> 1309 bool "Loongson-3 LLSC Workarounds"
>> 1310 default y if SMP
>> 1311 depends on CPU_LOONGSON64
>> 1312 help
>> 1313 Loongson-3 processors have the llsc issues which require workarounds.
>> 1314 Without workarounds the system may hang unexpectedly.
>> 1315
>> 1316 Say Y, unless you know what you are doing.
>> 1317
>> 1318 config CPU_LOONGSON3_CPUCFG_EMULATION
>> 1319 bool "Emulate the CPUCFG instruction on older Loongson cores"
>> 1320 default y
>> 1321 depends on CPU_LOONGSON64
>> 1322 help
>> 1323 Loongson-3A R4 and newer have the CPUCFG instruction available for
>> 1324 userland to query CPU capabilities, much like CPUID on x86. This
>> 1325 option provides emulation of the instruction on older Loongson
>> 1326 cores, back to Loongson-3A1000.
>> 1327
>> 1328 If unsure, please say Y.
>> 1329
>> 1330 config CPU_LOONGSON2E
>> 1331 bool "Loongson 2E"
>> 1332 depends on SYS_HAS_CPU_LOONGSON2E
>> 1333 select CPU_LOONGSON2EF
>> 1334 help
>> 1335 The Loongson 2E processor implements the MIPS III instruction set
>> 1336 with many extensions.
>> 1337
>> 1338 It has an internal FPGA northbridge, which is compatible to
>> 1339 bonito64.
>> 1340
>> 1341 config CPU_LOONGSON2F
>> 1342 bool "Loongson 2F"
>> 1343 depends on SYS_HAS_CPU_LOONGSON2F
>> 1344 select CPU_LOONGSON2EF
>> 1345 help
>> 1346 The Loongson 2F processor implements the MIPS III instruction set
>> 1347 with many extensions.
>> 1348
>> 1349 Loongson2F have built-in DDR2 and PCIX controller. The PCIX controller
>> 1350 have a similar programming interface with FPGA northbridge used in
>> 1351 Loongson2E.
>> 1352
>> 1353 config CPU_LOONGSON1B
>> 1354 bool "Loongson 1B"
>> 1355 depends on SYS_HAS_CPU_LOONGSON1B
>> 1356 select CPU_LOONGSON32
>> 1357 select LEDS_GPIO_REGISTER
>> 1358 help
>> 1359 The Loongson 1B is a 32-bit SoC, which implements the MIPS32
>> 1360 Release 1 instruction set and part of the MIPS32 Release 2
>> 1361 instruction set.
>> 1362
>> 1363 config CPU_LOONGSON1C
>> 1364 bool "Loongson 1C"
>> 1365 depends on SYS_HAS_CPU_LOONGSON1C
>> 1366 select CPU_LOONGSON32
>> 1367 select LEDS_GPIO_REGISTER
>> 1368 help
>> 1369 The Loongson 1C is a 32-bit SoC, which implements the MIPS32
>> 1370 Release 1 instruction set and part of the MIPS32 Release 2
>> 1371 instruction set.
>> 1372
>> 1373 config CPU_MIPS32_R1
>> 1374 bool "MIPS32 Release 1"
>> 1375 depends on SYS_HAS_CPU_MIPS32_R1
>> 1376 select CPU_HAS_PREFETCH
>> 1377 select CPU_SUPPORTS_32BIT_KERNEL
>> 1378 select CPU_SUPPORTS_HIGHMEM
>> 1379 help
>> 1380 Choose this option to build a kernel for release 1 or later of the
>> 1381 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1382 MIPS processor are based on a MIPS32 processor. If you know the
>> 1383 specific type of processor in your system, choose those that one
>> 1384 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1385 Release 2 of the MIPS32 architecture is available since several
>> 1386 years so chances are you even have a MIPS32 Release 2 processor
>> 1387 in which case you should choose CPU_MIPS32_R2 instead for better
>> 1388 performance.
>> 1389
>> 1390 config CPU_MIPS32_R2
>> 1391 bool "MIPS32 Release 2"
>> 1392 depends on SYS_HAS_CPU_MIPS32_R2
>> 1393 select CPU_HAS_PREFETCH
>> 1394 select CPU_SUPPORTS_32BIT_KERNEL
>> 1395 select CPU_SUPPORTS_HIGHMEM
>> 1396 select CPU_SUPPORTS_MSA
>> 1397 select HAVE_KVM
>> 1398 help
>> 1399 Choose this option to build a kernel for release 2 or later of the
>> 1400 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1401 MIPS processor are based on a MIPS32 processor. If you know the
>> 1402 specific type of processor in your system, choose those that one
>> 1403 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1404
>> 1405 config CPU_MIPS32_R5
>> 1406 bool "MIPS32 Release 5"
>> 1407 depends on SYS_HAS_CPU_MIPS32_R5
>> 1408 select CPU_HAS_PREFETCH
>> 1409 select CPU_SUPPORTS_32BIT_KERNEL
>> 1410 select CPU_SUPPORTS_HIGHMEM
>> 1411 select CPU_SUPPORTS_MSA
>> 1412 select HAVE_KVM
>> 1413 select MIPS_O32_FP64_SUPPORT
>> 1414 help
>> 1415 Choose this option to build a kernel for release 5 or later of the
>> 1416 MIPS32 architecture. New MIPS processors, starting with the Warrior
>> 1417 family, are based on a MIPS32r5 processor. If you own an older
>> 1418 processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
>> 1419
>> 1420 config CPU_MIPS32_R6
>> 1421 bool "MIPS32 Release 6"
>> 1422 depends on SYS_HAS_CPU_MIPS32_R6
>> 1423 select CPU_HAS_PREFETCH
>> 1424 select CPU_NO_LOAD_STORE_LR
>> 1425 select CPU_SUPPORTS_32BIT_KERNEL
>> 1426 select CPU_SUPPORTS_HIGHMEM
>> 1427 select CPU_SUPPORTS_MSA
>> 1428 select HAVE_KVM
>> 1429 select MIPS_O32_FP64_SUPPORT
>> 1430 help
>> 1431 Choose this option to build a kernel for release 6 or later of the
>> 1432 MIPS32 architecture. New MIPS processors, starting with the Warrior
>> 1433 family, are based on a MIPS32r6 processor. If you own an older
>> 1434 processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
>> 1435
>> 1436 config CPU_MIPS64_R1
>> 1437 bool "MIPS64 Release 1"
>> 1438 depends on SYS_HAS_CPU_MIPS64_R1
>> 1439 select CPU_HAS_PREFETCH
>> 1440 select CPU_SUPPORTS_32BIT_KERNEL
>> 1441 select CPU_SUPPORTS_64BIT_KERNEL
>> 1442 select CPU_SUPPORTS_HIGHMEM
>> 1443 select CPU_SUPPORTS_HUGEPAGES
>> 1444 help
>> 1445 Choose this option to build a kernel for release 1 or later of the
>> 1446 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1447 MIPS processor are based on a MIPS64 processor. If you know the
>> 1448 specific type of processor in your system, choose those that one
>> 1449 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1450 Release 2 of the MIPS64 architecture is available since several
>> 1451 years so chances are you even have a MIPS64 Release 2 processor
>> 1452 in which case you should choose CPU_MIPS64_R2 instead for better
>> 1453 performance.
>> 1454
>> 1455 config CPU_MIPS64_R2
>> 1456 bool "MIPS64 Release 2"
>> 1457 depends on SYS_HAS_CPU_MIPS64_R2
>> 1458 select CPU_HAS_PREFETCH
>> 1459 select CPU_SUPPORTS_32BIT_KERNEL
>> 1460 select CPU_SUPPORTS_64BIT_KERNEL
>> 1461 select CPU_SUPPORTS_HIGHMEM
>> 1462 select CPU_SUPPORTS_HUGEPAGES
>> 1463 select CPU_SUPPORTS_MSA
>> 1464 select HAVE_KVM
>> 1465 help
>> 1466 Choose this option to build a kernel for release 2 or later of the
>> 1467 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1468 MIPS processor are based on a MIPS64 processor. If you know the
>> 1469 specific type of processor in your system, choose those that one
>> 1470 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1471
>> 1472 config CPU_MIPS64_R5
>> 1473 bool "MIPS64 Release 5"
>> 1474 depends on SYS_HAS_CPU_MIPS64_R5
>> 1475 select CPU_HAS_PREFETCH
>> 1476 select CPU_SUPPORTS_32BIT_KERNEL
>> 1477 select CPU_SUPPORTS_64BIT_KERNEL
>> 1478 select CPU_SUPPORTS_HIGHMEM
>> 1479 select CPU_SUPPORTS_HUGEPAGES
>> 1480 select CPU_SUPPORTS_MSA
>> 1481 select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
>> 1482 select HAVE_KVM
>> 1483 help
>> 1484 Choose this option to build a kernel for release 5 or later of the
>> 1485 MIPS64 architecture. This is a intermediate MIPS architecture
>> 1486 release partly implementing release 6 features. Though there is no
>> 1487 any hardware known to be based on this release.
>> 1488
>> 1489 config CPU_MIPS64_R6
>> 1490 bool "MIPS64 Release 6"
>> 1491 depends on SYS_HAS_CPU_MIPS64_R6
>> 1492 select CPU_HAS_PREFETCH
>> 1493 select CPU_NO_LOAD_STORE_LR
>> 1494 select CPU_SUPPORTS_32BIT_KERNEL
>> 1495 select CPU_SUPPORTS_64BIT_KERNEL
>> 1496 select CPU_SUPPORTS_HIGHMEM
>> 1497 select CPU_SUPPORTS_HUGEPAGES
>> 1498 select CPU_SUPPORTS_MSA
>> 1499 select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
>> 1500 select HAVE_KVM
>> 1501 help
>> 1502 Choose this option to build a kernel for release 6 or later of the
>> 1503 MIPS64 architecture. New MIPS processors, starting with the Warrior
>> 1504 family, are based on a MIPS64r6 processor. If you own an older
>> 1505 processor, you probably need to select MIPS64r1 or MIPS64r2 instead.
>> 1506
>> 1507 config CPU_P5600
>> 1508 bool "MIPS Warrior P5600"
>> 1509 depends on SYS_HAS_CPU_P5600
>> 1510 select CPU_HAS_PREFETCH
>> 1511 select CPU_SUPPORTS_32BIT_KERNEL
>> 1512 select CPU_SUPPORTS_HIGHMEM
>> 1513 select CPU_SUPPORTS_MSA
>> 1514 select CPU_SUPPORTS_CPUFREQ
>> 1515 select CPU_MIPSR2_IRQ_VI
>> 1516 select CPU_MIPSR2_IRQ_EI
>> 1517 select HAVE_KVM
>> 1518 select MIPS_O32_FP64_SUPPORT
>> 1519 help
>> 1520 Choose this option to build a kernel for MIPS Warrior P5600 CPU.
>> 1521 It's based on MIPS32r5 ISA with XPA, EVA, dual/quad issue exec pipes,
>> 1522 MMU with two-levels TLB, UCA, MSA, MDU core level features and system
>> 1523 level features like up to six P5600 calculation cores, CM2 with L2
>> 1524 cache, IOCU/IOMMU (though might be unused depending on the system-
>> 1525 specific IP core configuration), GIC, CPC, virtualisation module,
>> 1526 eJTAG and PDtrace.
>> 1527
>> 1528 config CPU_R3000
>> 1529 bool "R3000"
>> 1530 depends on SYS_HAS_CPU_R3000
>> 1531 select CPU_HAS_WB
>> 1532 select CPU_R3K_TLB
>> 1533 select CPU_SUPPORTS_32BIT_KERNEL
>> 1534 select CPU_SUPPORTS_HIGHMEM
>> 1535 help
>> 1536 Please make sure to pick the right CPU type. Linux/MIPS is not
>> 1537 designed to be generic, i.e. Kernels compiled for R3000 CPUs will
>> 1538 *not* work on R4000 machines and vice versa. However, since most
>> 1539 of the supported machines have an R4000 (or similar) CPU, R4x00
>> 1540 might be a safe bet. If the resulting kernel does not work,
>> 1541 try to recompile with R3000.
>> 1542
>> 1543 config CPU_R4300
>> 1544 bool "R4300"
>> 1545 depends on SYS_HAS_CPU_R4300
>> 1546 select CPU_SUPPORTS_32BIT_KERNEL
>> 1547 select CPU_SUPPORTS_64BIT_KERNEL
>> 1548 help
>> 1549 MIPS Technologies R4300-series processors.
>> 1550
>> 1551 config CPU_R4X00
>> 1552 bool "R4x00"
>> 1553 depends on SYS_HAS_CPU_R4X00
>> 1554 select CPU_SUPPORTS_32BIT_KERNEL
>> 1555 select CPU_SUPPORTS_64BIT_KERNEL
>> 1556 select CPU_SUPPORTS_HUGEPAGES
>> 1557 help
>> 1558 MIPS Technologies R4000-series processors other than 4300, including
>> 1559 the R4000, R4400, R4600, and 4700.
>> 1560
>> 1561 config CPU_TX49XX
>> 1562 bool "R49XX"
>> 1563 depends on SYS_HAS_CPU_TX49XX
>> 1564 select CPU_HAS_PREFETCH
>> 1565 select CPU_SUPPORTS_32BIT_KERNEL
>> 1566 select CPU_SUPPORTS_64BIT_KERNEL
>> 1567 select CPU_SUPPORTS_HUGEPAGES
>> 1568
>> 1569 config CPU_R5000
>> 1570 bool "R5000"
>> 1571 depends on SYS_HAS_CPU_R5000
>> 1572 select CPU_SUPPORTS_32BIT_KERNEL
>> 1573 select CPU_SUPPORTS_64BIT_KERNEL
>> 1574 select CPU_SUPPORTS_HUGEPAGES
>> 1575 help
>> 1576 MIPS Technologies R5000-series processors other than the Nevada.
>> 1577
>> 1578 config CPU_R5500
>> 1579 bool "R5500"
>> 1580 depends on SYS_HAS_CPU_R5500
>> 1581 select CPU_SUPPORTS_32BIT_KERNEL
>> 1582 select CPU_SUPPORTS_64BIT_KERNEL
>> 1583 select CPU_SUPPORTS_HUGEPAGES
>> 1584 help
>> 1585 NEC VR5500 and VR5500A series processors implement 64-bit MIPS IV
>> 1586 instruction set.
>> 1587
>> 1588 config CPU_NEVADA
>> 1589 bool "RM52xx"
>> 1590 depends on SYS_HAS_CPU_NEVADA
>> 1591 select CPU_SUPPORTS_32BIT_KERNEL
>> 1592 select CPU_SUPPORTS_64BIT_KERNEL
>> 1593 select CPU_SUPPORTS_HUGEPAGES
>> 1594 help
>> 1595 QED / PMC-Sierra RM52xx-series ("Nevada") processors.
>> 1596
>> 1597 config CPU_R10000
>> 1598 bool "R10000"
>> 1599 depends on SYS_HAS_CPU_R10000
>> 1600 select CPU_HAS_PREFETCH
>> 1601 select CPU_SUPPORTS_32BIT_KERNEL
>> 1602 select CPU_SUPPORTS_64BIT_KERNEL
>> 1603 select CPU_SUPPORTS_HIGHMEM
>> 1604 select CPU_SUPPORTS_HUGEPAGES
>> 1605 help
>> 1606 MIPS Technologies R10000-series processors.
>> 1607
>> 1608 config CPU_RM7000
>> 1609 bool "RM7000"
>> 1610 depends on SYS_HAS_CPU_RM7000
>> 1611 select CPU_HAS_PREFETCH
>> 1612 select CPU_SUPPORTS_32BIT_KERNEL
>> 1613 select CPU_SUPPORTS_64BIT_KERNEL
>> 1614 select CPU_SUPPORTS_HIGHMEM
>> 1615 select CPU_SUPPORTS_HUGEPAGES
>> 1616
>> 1617 config CPU_SB1
>> 1618 bool "SB1"
>> 1619 depends on SYS_HAS_CPU_SB1
>> 1620 select CPU_SUPPORTS_32BIT_KERNEL
>> 1621 select CPU_SUPPORTS_64BIT_KERNEL
>> 1622 select CPU_SUPPORTS_HIGHMEM
>> 1623 select CPU_SUPPORTS_HUGEPAGES
>> 1624 select WEAK_ORDERING
>> 1625
>> 1626 config CPU_CAVIUM_OCTEON
>> 1627 bool "Cavium Octeon processor"
>> 1628 depends on SYS_HAS_CPU_CAVIUM_OCTEON
>> 1629 select CPU_HAS_PREFETCH
>> 1630 select CPU_SUPPORTS_64BIT_KERNEL
>> 1631 select WEAK_ORDERING
>> 1632 select CPU_SUPPORTS_HIGHMEM
>> 1633 select CPU_SUPPORTS_HUGEPAGES
>> 1634 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1635 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1636 select MIPS_L1_CACHE_SHIFT_7
>> 1637 select HAVE_KVM
>> 1638 help
>> 1639 The Cavium Octeon processor is a highly integrated chip containing
>> 1640 many ethernet hardware widgets for networking tasks. The processor
>> 1641 can have up to 16 Mips64v2 cores and 8 integrated gigabit ethernets.
>> 1642 Full details can be found at http://www.caviumnetworks.com.
>> 1643
>> 1644 config CPU_BMIPS
>> 1645 bool "Broadcom BMIPS"
>> 1646 depends on SYS_HAS_CPU_BMIPS
>> 1647 select CPU_MIPS32
>> 1648 select CPU_BMIPS32_3300 if SYS_HAS_CPU_BMIPS32_3300
>> 1649 select CPU_BMIPS4350 if SYS_HAS_CPU_BMIPS4350
>> 1650 select CPU_BMIPS4380 if SYS_HAS_CPU_BMIPS4380
>> 1651 select CPU_BMIPS5000 if SYS_HAS_CPU_BMIPS5000
>> 1652 select CPU_SUPPORTS_32BIT_KERNEL
>> 1653 select DMA_NONCOHERENT
>> 1654 select IRQ_MIPS_CPU
>> 1655 select SWAP_IO_SPACE
>> 1656 select WEAK_ORDERING
>> 1657 select CPU_SUPPORTS_HIGHMEM
>> 1658 select CPU_HAS_PREFETCH
>> 1659 select CPU_SUPPORTS_CPUFREQ
>> 1660 select MIPS_EXTERNAL_TIMER
>> 1661 select GENERIC_IRQ_MIGRATION if HOTPLUG_CPU
>> 1662 help
>> 1663 Support for BMIPS32/3300/4350/4380 and BMIPS5000 processors.
198 1664
199 config CPU_CK610 <<
200 bool "CSKY CPU ck610" <<
201 select CPU_NEED_TLBSYNC <<
202 select CPU_NEED_SOFTALIGN <<
203 select CPU_NO_USER_BKPT <<
204 <<
205 config CPU_CK810 <<
206 bool "CSKY CPU ck810" <<
207 select CPU_HAS_HILO <<
208 select CPU_NEED_TLBSYNC <<
209 <<
210 config CPU_CK807 <<
211 bool "CSKY CPU ck807" <<
212 select CPU_HAS_HILO <<
213 <<
214 config CPU_CK860 <<
215 bool "CSKY CPU ck860" <<
216 select CPU_HAS_TLBI <<
217 select CPU_HAS_CACHEV2 <<
218 select CPU_HAS_LDSTEX <<
219 select CPU_HAS_FPUV2 <<
220 endchoice 1665 endchoice
221 1666
>> 1667 config CPU_MIPS32_3_5_FEATURES
>> 1668 bool "MIPS32 Release 3.5 Features"
>> 1669 depends on SYS_HAS_CPU_MIPS32_R3_5
>> 1670 depends on CPU_MIPS32_R2 || CPU_MIPS32_R5 || CPU_MIPS32_R6 || \
>> 1671 CPU_P5600
>> 1672 help
>> 1673 Choose this option to build a kernel for release 2 or later of the
>> 1674 MIPS32 architecture including features from the 3.5 release such as
>> 1675 support for Enhanced Virtual Addressing (EVA).
>> 1676
>> 1677 config CPU_MIPS32_3_5_EVA
>> 1678 bool "Enhanced Virtual Addressing (EVA)"
>> 1679 depends on CPU_MIPS32_3_5_FEATURES
>> 1680 select EVA
>> 1681 default y
>> 1682 help
>> 1683 Choose this option if you want to enable the Enhanced Virtual
>> 1684 Addressing (EVA) on your MIPS32 core (such as proAptiv).
>> 1685 One of its primary benefits is an increase in the maximum size
>> 1686 of lowmem (up to 3GB). If unsure, say 'N' here.
>> 1687
>> 1688 config CPU_MIPS32_R5_FEATURES
>> 1689 bool "MIPS32 Release 5 Features"
>> 1690 depends on SYS_HAS_CPU_MIPS32_R5
>> 1691 depends on CPU_MIPS32_R2 || CPU_MIPS32_R5 || CPU_P5600
>> 1692 help
>> 1693 Choose this option to build a kernel for release 2 or later of the
>> 1694 MIPS32 architecture including features from release 5 such as
>> 1695 support for Extended Physical Addressing (XPA).
>> 1696
>> 1697 config CPU_MIPS32_R5_XPA
>> 1698 bool "Extended Physical Addressing (XPA)"
>> 1699 depends on CPU_MIPS32_R5_FEATURES
>> 1700 depends on !EVA
>> 1701 depends on !PAGE_SIZE_4KB
>> 1702 depends on SYS_SUPPORTS_HIGHMEM
>> 1703 select XPA
>> 1704 select HIGHMEM
>> 1705 select PHYS_ADDR_T_64BIT
>> 1706 default n
>> 1707 help
>> 1708 Choose this option if you want to enable the Extended Physical
>> 1709 Addressing (XPA) on your MIPS32 core (such as P5600 series). The
>> 1710 benefit is to increase physical addressing equal to or greater
>> 1711 than 40 bits. Note that this has the side effect of turning on
>> 1712 64-bit addressing which in turn makes the PTEs 64-bit in size.
>> 1713 If unsure, say 'N' here.
>> 1714
>> 1715 if CPU_LOONGSON2F
>> 1716 config CPU_NOP_WORKAROUNDS
>> 1717 bool
>> 1718
>> 1719 config CPU_JUMP_WORKAROUNDS
>> 1720 bool
>> 1721
>> 1722 config CPU_LOONGSON2F_WORKAROUNDS
>> 1723 bool "Loongson 2F Workarounds"
>> 1724 default y
>> 1725 select CPU_NOP_WORKAROUNDS
>> 1726 select CPU_JUMP_WORKAROUNDS
>> 1727 help
>> 1728 Loongson 2F01 / 2F02 processors have the NOP & JUMP issues which
>> 1729 require workarounds. Without workarounds the system may hang
>> 1730 unexpectedly. For more information please refer to the gas
>> 1731 -mfix-loongson2f-nop and -mfix-loongson2f-jump options.
>> 1732
>> 1733 Loongson 2F03 and later have fixed these issues and no workarounds
>> 1734 are needed. The workarounds have no significant side effect on them
>> 1735 but may decrease the performance of the system so this option should
>> 1736 be disabled unless the kernel is intended to be run on 2F01 or 2F02
>> 1737 systems.
>> 1738
>> 1739 If unsure, please say Y.
>> 1740 endif # CPU_LOONGSON2F
>> 1741
>> 1742 config SYS_SUPPORTS_ZBOOT
>> 1743 bool
>> 1744 select HAVE_KERNEL_GZIP
>> 1745 select HAVE_KERNEL_BZIP2
>> 1746 select HAVE_KERNEL_LZ4
>> 1747 select HAVE_KERNEL_LZMA
>> 1748 select HAVE_KERNEL_LZO
>> 1749 select HAVE_KERNEL_XZ
>> 1750 select HAVE_KERNEL_ZSTD
>> 1751
>> 1752 config SYS_SUPPORTS_ZBOOT_UART16550
>> 1753 bool
>> 1754 select SYS_SUPPORTS_ZBOOT
>> 1755
>> 1756 config SYS_SUPPORTS_ZBOOT_UART_PROM
>> 1757 bool
>> 1758 select SYS_SUPPORTS_ZBOOT
>> 1759
>> 1760 config CPU_LOONGSON2EF
>> 1761 bool
>> 1762 select CPU_SUPPORTS_32BIT_KERNEL
>> 1763 select CPU_SUPPORTS_64BIT_KERNEL
>> 1764 select CPU_SUPPORTS_HIGHMEM
>> 1765 select CPU_SUPPORTS_HUGEPAGES
>> 1766
>> 1767 config CPU_LOONGSON32
>> 1768 bool
>> 1769 select CPU_MIPS32
>> 1770 select CPU_MIPSR2
>> 1771 select CPU_HAS_PREFETCH
>> 1772 select CPU_SUPPORTS_32BIT_KERNEL
>> 1773 select CPU_SUPPORTS_HIGHMEM
>> 1774 select CPU_SUPPORTS_CPUFREQ
>> 1775
>> 1776 config CPU_BMIPS32_3300
>> 1777 select SMP_UP if SMP
>> 1778 bool
>> 1779
>> 1780 config CPU_BMIPS4350
>> 1781 bool
>> 1782 select SYS_SUPPORTS_SMP
>> 1783 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1784
>> 1785 config CPU_BMIPS4380
>> 1786 bool
>> 1787 select MIPS_L1_CACHE_SHIFT_6
>> 1788 select SYS_SUPPORTS_SMP
>> 1789 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1790 select CPU_HAS_RIXI
>> 1791
>> 1792 config CPU_BMIPS5000
>> 1793 bool
>> 1794 select MIPS_CPU_SCACHE
>> 1795 select MIPS_L1_CACHE_SHIFT_7
>> 1796 select SYS_SUPPORTS_SMP
>> 1797 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1798 select CPU_HAS_RIXI
>> 1799
>> 1800 config SYS_HAS_CPU_LOONGSON64
>> 1801 bool
>> 1802 select CPU_SUPPORTS_CPUFREQ
>> 1803 select CPU_HAS_RIXI
>> 1804
>> 1805 config SYS_HAS_CPU_LOONGSON2E
>> 1806 bool
>> 1807
>> 1808 config SYS_HAS_CPU_LOONGSON2F
>> 1809 bool
>> 1810 select CPU_SUPPORTS_CPUFREQ
>> 1811 select CPU_SUPPORTS_ADDRWINCFG if 64BIT
>> 1812
>> 1813 config SYS_HAS_CPU_LOONGSON1B
>> 1814 bool
>> 1815
>> 1816 config SYS_HAS_CPU_LOONGSON1C
>> 1817 bool
>> 1818
>> 1819 config SYS_HAS_CPU_MIPS32_R1
>> 1820 bool
>> 1821
>> 1822 config SYS_HAS_CPU_MIPS32_R2
>> 1823 bool
>> 1824
>> 1825 config SYS_HAS_CPU_MIPS32_R3_5
>> 1826 bool
>> 1827
>> 1828 config SYS_HAS_CPU_MIPS32_R5
>> 1829 bool
>> 1830
>> 1831 config SYS_HAS_CPU_MIPS32_R6
>> 1832 bool
>> 1833
>> 1834 config SYS_HAS_CPU_MIPS64_R1
>> 1835 bool
>> 1836
>> 1837 config SYS_HAS_CPU_MIPS64_R2
>> 1838 bool
>> 1839
>> 1840 config SYS_HAS_CPU_MIPS64_R5
>> 1841 bool
>> 1842
>> 1843 config SYS_HAS_CPU_MIPS64_R6
>> 1844 bool
>> 1845
>> 1846 config SYS_HAS_CPU_P5600
>> 1847 bool
>> 1848
>> 1849 config SYS_HAS_CPU_R3000
>> 1850 bool
>> 1851
>> 1852 config SYS_HAS_CPU_R4300
>> 1853 bool
>> 1854
>> 1855 config SYS_HAS_CPU_R4X00
>> 1856 bool
>> 1857
>> 1858 config SYS_HAS_CPU_TX49XX
>> 1859 bool
>> 1860
>> 1861 config SYS_HAS_CPU_R5000
>> 1862 bool
>> 1863
>> 1864 config SYS_HAS_CPU_R5500
>> 1865 bool
>> 1866
>> 1867 config SYS_HAS_CPU_NEVADA
>> 1868 bool
>> 1869
>> 1870 config SYS_HAS_CPU_R10000
>> 1871 bool
>> 1872
>> 1873 config SYS_HAS_CPU_RM7000
>> 1874 bool
>> 1875
>> 1876 config SYS_HAS_CPU_SB1
>> 1877 bool
>> 1878
>> 1879 config SYS_HAS_CPU_CAVIUM_OCTEON
>> 1880 bool
>> 1881
>> 1882 config SYS_HAS_CPU_BMIPS
>> 1883 bool
>> 1884
>> 1885 config SYS_HAS_CPU_BMIPS32_3300
>> 1886 bool
>> 1887 select SYS_HAS_CPU_BMIPS
>> 1888
>> 1889 config SYS_HAS_CPU_BMIPS4350
>> 1890 bool
>> 1891 select SYS_HAS_CPU_BMIPS
>> 1892
>> 1893 config SYS_HAS_CPU_BMIPS4380
>> 1894 bool
>> 1895 select SYS_HAS_CPU_BMIPS
>> 1896
>> 1897 config SYS_HAS_CPU_BMIPS5000
>> 1898 bool
>> 1899 select SYS_HAS_CPU_BMIPS
>> 1900
>> 1901 #
>> 1902 # CPU may reorder R->R, R->W, W->R, W->W
>> 1903 # Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC
>> 1904 #
>> 1905 config WEAK_ORDERING
>> 1906 bool
>> 1907
>> 1908 #
>> 1909 # CPU may reorder reads and writes beyond LL/SC
>> 1910 # CPU may reorder R->LL, R->LL, W->LL, W->LL, R->SC, R->SC, W->SC, W->SC
>> 1911 #
>> 1912 config WEAK_REORDERING_BEYOND_LLSC
>> 1913 bool
>> 1914 endmenu
>> 1915
>> 1916 #
>> 1917 # These two indicate any level of the MIPS32 and MIPS64 architecture
>> 1918 #
>> 1919 config CPU_MIPS32
>> 1920 bool
>> 1921 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R5 || \
>> 1922 CPU_MIPS32_R6 || CPU_P5600
>> 1923
>> 1924 config CPU_MIPS64
>> 1925 bool
>> 1926 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R5 || \
>> 1927 CPU_MIPS64_R6 || CPU_LOONGSON64 || CPU_CAVIUM_OCTEON
>> 1928
>> 1929 #
>> 1930 # These indicate the revision of the architecture
>> 1931 #
>> 1932 config CPU_MIPSR1
>> 1933 bool
>> 1934 default y if CPU_MIPS32_R1 || CPU_MIPS64_R1
>> 1935
>> 1936 config CPU_MIPSR2
>> 1937 bool
>> 1938 default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_CAVIUM_OCTEON
>> 1939 select CPU_HAS_RIXI
>> 1940 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
>> 1941 select MIPS_SPRAM
>> 1942
>> 1943 config CPU_MIPSR5
>> 1944 bool
>> 1945 default y if CPU_MIPS32_R5 || CPU_MIPS64_R5 || CPU_P5600
>> 1946 select CPU_HAS_RIXI
>> 1947 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
>> 1948 select MIPS_SPRAM
>> 1949
>> 1950 config CPU_MIPSR6
>> 1951 bool
>> 1952 default y if CPU_MIPS32_R6 || CPU_MIPS64_R6
>> 1953 select CPU_HAS_RIXI
>> 1954 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
>> 1955 select HAVE_ARCH_BITREVERSE
>> 1956 select MIPS_ASID_BITS_VARIABLE
>> 1957 select MIPS_CRC_SUPPORT
>> 1958 select MIPS_SPRAM
>> 1959
>> 1960 config TARGET_ISA_REV
>> 1961 int
>> 1962 default 1 if CPU_MIPSR1
>> 1963 default 2 if CPU_MIPSR2
>> 1964 default 5 if CPU_MIPSR5
>> 1965 default 6 if CPU_MIPSR6
>> 1966 default 0
>> 1967 help
>> 1968 Reflects the ISA revision being targeted by the kernel build. This
>> 1969 is effectively the Kconfig equivalent of MIPS_ISA_REV.
>> 1970
>> 1971 config EVA
>> 1972 bool
>> 1973
>> 1974 config XPA
>> 1975 bool
>> 1976
>> 1977 config SYS_SUPPORTS_32BIT_KERNEL
>> 1978 bool
>> 1979 config SYS_SUPPORTS_64BIT_KERNEL
>> 1980 bool
>> 1981 config CPU_SUPPORTS_32BIT_KERNEL
>> 1982 bool
>> 1983 config CPU_SUPPORTS_64BIT_KERNEL
>> 1984 bool
>> 1985 config CPU_SUPPORTS_CPUFREQ
>> 1986 bool
>> 1987 config CPU_SUPPORTS_ADDRWINCFG
>> 1988 bool
>> 1989 config CPU_SUPPORTS_HUGEPAGES
>> 1990 bool
>> 1991 depends on !(32BIT && (PHYS_ADDR_T_64BIT || EVA))
>> 1992 config MIPS_PGD_C0_CONTEXT
>> 1993 bool
>> 1994 depends on 64BIT
>> 1995 default y if (CPU_MIPSR2 || CPU_MIPSR6)
>> 1996
>> 1997 #
>> 1998 # Set to y for ptrace access to watch registers.
>> 1999 #
>> 2000 config HARDWARE_WATCHPOINTS
>> 2001 bool
>> 2002 default y if CPU_MIPSR1 || CPU_MIPSR2 || CPU_MIPSR6
>> 2003
>> 2004 menu "Kernel type"
>> 2005
222 choice 2006 choice
223 prompt "PAGE OFFSET" !! 2007 prompt "Kernel code model"
224 default PAGE_OFFSET_80000000 !! 2008 help
>> 2009 You should only select this option if you have a workload that
>> 2010 actually benefits from 64-bit processing or if your machine has
>> 2011 large memory. You will only be presented a single option in this
>> 2012 menu if your system does not support both 32-bit and 64-bit kernels.
>> 2013
>> 2014 config 32BIT
>> 2015 bool "32-bit kernel"
>> 2016 depends on CPU_SUPPORTS_32BIT_KERNEL && SYS_SUPPORTS_32BIT_KERNEL
>> 2017 select TRAD_SIGNALS
>> 2018 help
>> 2019 Select this option if you want to build a 32-bit kernel.
225 2020
226 config PAGE_OFFSET_80000000 !! 2021 config 64BIT
227 bool "PAGE OFFSET 2G (user:kernel = 2: !! 2022 bool "64-bit kernel"
>> 2023 depends on CPU_SUPPORTS_64BIT_KERNEL && SYS_SUPPORTS_64BIT_KERNEL
>> 2024 help
>> 2025 Select this option if you want to build a 64-bit kernel.
228 2026
229 config PAGE_OFFSET_A0000000 <<
230 bool "PAGE OFFSET 2.5G (user:kernel = <<
231 endchoice 2027 endchoice
232 2028
233 config PAGE_OFFSET !! 2029 config MIPS_VA_BITS_48
234 hex !! 2030 bool "48 bits virtual memory"
235 default 0x80000000 if PAGE_OFFSET_8000 !! 2031 depends on 64BIT
236 default 0xa0000000 if PAGE_OFFSET_A000 !! 2032 help
237 choice !! 2033 Support a maximum at least 48 bits of application virtual
>> 2034 memory. Default is 40 bits or less, depending on the CPU.
>> 2035 For page sizes 16k and above, this option results in a small
>> 2036 memory overhead for page tables. For 4k page size, a fourth
>> 2037 level of page tables is added which imposes both a memory
>> 2038 overhead as well as slower TLB fault handling.
>> 2039
>> 2040 If unsure, say N.
>> 2041
>> 2042 config ZBOOT_LOAD_ADDRESS
>> 2043 hex "Compressed kernel load address"
>> 2044 default 0xffffffff80400000 if BCM47XX
>> 2045 default 0x0
>> 2046 depends on SYS_SUPPORTS_ZBOOT
>> 2047 help
>> 2048 The address to load compressed kernel, aka vmlinuz.
238 2049
239 prompt "C-SKY PMU type" !! 2050 This is only used if non-zero.
240 depends on PERF_EVENTS <<
241 depends on CPU_CK807 || CPU_CK810 || C <<
242 2051
243 config CPU_PMU_NONE !! 2052 choice
244 bool "None" !! 2053 prompt "Kernel page size"
>> 2054 default PAGE_SIZE_4KB
245 2055
246 config CSKY_PMU_V1 !! 2056 config PAGE_SIZE_4KB
247 bool "Performance Monitoring Unit Ver. !! 2057 bool "4kB"
>> 2058 depends on !CPU_LOONGSON2EF && !CPU_LOONGSON64
>> 2059 help
>> 2060 This option select the standard 4kB Linux page size. On some
>> 2061 R3000-family processors this is the only available page size. Using
>> 2062 4kB page size will minimize memory consumption and is therefore
>> 2063 recommended for low memory systems.
>> 2064
>> 2065 config PAGE_SIZE_8KB
>> 2066 bool "8kB"
>> 2067 depends on CPU_CAVIUM_OCTEON
>> 2068 depends on !MIPS_VA_BITS_48
>> 2069 help
>> 2070 Using 8kB page size will result in higher performance kernel at
>> 2071 the price of higher memory consumption. This option is available
>> 2072 only on cnMIPS processors. Note that you will need a suitable Linux
>> 2073 distribution to support this.
>> 2074
>> 2075 config PAGE_SIZE_16KB
>> 2076 bool "16kB"
>> 2077 depends on !CPU_R3000
>> 2078 help
>> 2079 Using 16kB page size will result in higher performance kernel at
>> 2080 the price of higher memory consumption. This option is available on
>> 2081 all non-R3000 family processors. Note that you will need a suitable
>> 2082 Linux distribution to support this.
>> 2083
>> 2084 config PAGE_SIZE_32KB
>> 2085 bool "32kB"
>> 2086 depends on CPU_CAVIUM_OCTEON
>> 2087 depends on !MIPS_VA_BITS_48
>> 2088 help
>> 2089 Using 32kB page size will result in higher performance kernel at
>> 2090 the price of higher memory consumption. This option is available
>> 2091 only on cnMIPS cores. Note that you will need a suitable Linux
>> 2092 distribution to support this.
>> 2093
>> 2094 config PAGE_SIZE_64KB
>> 2095 bool "64kB"
>> 2096 depends on !CPU_R3000
>> 2097 help
>> 2098 Using 64kB page size will result in higher performance kernel at
>> 2099 the price of higher memory consumption. This option is available on
>> 2100 all non-R3000 family processor. Not that at the time of this
>> 2101 writing this option is still high experimental.
248 2102
249 endchoice 2103 endchoice
250 2104
>> 2105 config ARCH_FORCE_MAX_ORDER
>> 2106 int "Maximum zone order"
>> 2107 default "13" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
>> 2108 default "12" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
>> 2109 default "11" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
>> 2110 default "10"
>> 2111 help
>> 2112 The kernel memory allocator divides physically contiguous memory
>> 2113 blocks into "zones", where each zone is a power of two number of
>> 2114 pages. This option selects the largest power of two that the kernel
>> 2115 keeps in the memory allocator. If you need to allocate very large
>> 2116 blocks of physically contiguous memory, then you may need to
>> 2117 increase this value.
>> 2118
>> 2119 The page size is not necessarily 4KB. Keep this in mind
>> 2120 when choosing a value for this option.
>> 2121
>> 2122 config BOARD_SCACHE
>> 2123 bool
>> 2124
>> 2125 config IP22_CPU_SCACHE
>> 2126 bool
>> 2127 select BOARD_SCACHE
>> 2128
>> 2129 #
>> 2130 # Support for a MIPS32 / MIPS64 style S-caches
>> 2131 #
>> 2132 config MIPS_CPU_SCACHE
>> 2133 bool
>> 2134 select BOARD_SCACHE
>> 2135
>> 2136 config R5000_CPU_SCACHE
>> 2137 bool
>> 2138 select BOARD_SCACHE
>> 2139
>> 2140 config RM7000_CPU_SCACHE
>> 2141 bool
>> 2142 select BOARD_SCACHE
>> 2143
>> 2144 config SIBYTE_DMA_PAGEOPS
>> 2145 bool "Use DMA to clear/copy pages"
>> 2146 depends on CPU_SB1
>> 2147 help
>> 2148 Instead of using the CPU to zero and copy pages, use a Data Mover
>> 2149 channel. These DMA channels are otherwise unused by the standard
>> 2150 SiByte Linux port. Seems to give a small performance benefit.
>> 2151
>> 2152 config CPU_HAS_PREFETCH
>> 2153 bool
>> 2154
>> 2155 config CPU_GENERIC_DUMP_TLB
>> 2156 bool
>> 2157 default y if !CPU_R3000
>> 2158
>> 2159 config MIPS_FP_SUPPORT
>> 2160 bool "Floating Point support" if EXPERT
>> 2161 default y
>> 2162 help
>> 2163 Select y to include support for floating point in the kernel
>> 2164 including initialization of FPU hardware, FP context save & restore
>> 2165 and emulation of an FPU where necessary. Without this support any
>> 2166 userland program attempting to use floating point instructions will
>> 2167 receive a SIGILL.
>> 2168
>> 2169 If you know that your userland will not attempt to use floating point
>> 2170 instructions then you can say n here to shrink the kernel a little.
>> 2171
>> 2172 If unsure, say y.
>> 2173
>> 2174 config CPU_R2300_FPU
>> 2175 bool
>> 2176 depends on MIPS_FP_SUPPORT
>> 2177 default y if CPU_R3000
>> 2178
>> 2179 config CPU_R3K_TLB
>> 2180 bool
>> 2181
>> 2182 config CPU_R4K_FPU
>> 2183 bool
>> 2184 depends on MIPS_FP_SUPPORT
>> 2185 default y if !CPU_R2300_FPU
>> 2186
>> 2187 config CPU_R4K_CACHE_TLB
>> 2188 bool
>> 2189 default y if !(CPU_R3K_TLB || CPU_SB1 || CPU_CAVIUM_OCTEON)
>> 2190
>> 2191 config MIPS_MT_SMP
>> 2192 bool "MIPS MT SMP support (1 TC on each available VPE)"
>> 2193 default y
>> 2194 depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MIPSR6 && !CPU_MICROMIPS
>> 2195 select CPU_MIPSR2_IRQ_VI
>> 2196 select CPU_MIPSR2_IRQ_EI
>> 2197 select SYNC_R4K
>> 2198 select MIPS_MT
>> 2199 select SMP
>> 2200 select SMP_UP
>> 2201 select SYS_SUPPORTS_SMP
>> 2202 select SYS_SUPPORTS_SCHED_SMT
>> 2203 select MIPS_PERF_SHARED_TC_COUNTERS
>> 2204 help
>> 2205 This is a kernel model which is known as SMVP. This is supported
>> 2206 on cores with the MT ASE and uses the available VPEs to implement
>> 2207 virtual processors which supports SMP. This is equivalent to the
>> 2208 Intel Hyperthreading feature. For further information go to
>> 2209 <http://www.imgtec.com/mips/mips-multithreading.asp>.
>> 2210
>> 2211 config MIPS_MT
>> 2212 bool
>> 2213
>> 2214 config SCHED_SMT
>> 2215 bool "SMT (multithreading) scheduler support"
>> 2216 depends on SYS_SUPPORTS_SCHED_SMT
>> 2217 default n
>> 2218 help
>> 2219 SMT scheduler support improves the CPU scheduler's decision making
>> 2220 when dealing with MIPS MT enabled cores at a cost of slightly
>> 2221 increased overhead in some places. If unsure say N here.
>> 2222
>> 2223 config SYS_SUPPORTS_SCHED_SMT
>> 2224 bool
>> 2225
>> 2226 config SYS_SUPPORTS_MULTITHREADING
>> 2227 bool
>> 2228
>> 2229 config MIPS_MT_FPAFF
>> 2230 bool "Dynamic FPU affinity for FP-intensive threads"
>> 2231 default y
>> 2232 depends on MIPS_MT_SMP
>> 2233
>> 2234 config MIPSR2_TO_R6_EMULATOR
>> 2235 bool "MIPS R2-to-R6 emulator"
>> 2236 depends on CPU_MIPSR6
>> 2237 depends on MIPS_FP_SUPPORT
>> 2238 default y
>> 2239 help
>> 2240 Choose this option if you want to run non-R6 MIPS userland code.
>> 2241 Even if you say 'Y' here, the emulator will still be disabled by
>> 2242 default. You can enable it using the 'mipsr2emu' kernel option.
>> 2243 The only reason this is a build-time option is to save ~14K from the
>> 2244 final kernel image.
>> 2245
>> 2246 config SYS_SUPPORTS_VPE_LOADER
>> 2247 bool
>> 2248 depends on SYS_SUPPORTS_MULTITHREADING
>> 2249 help
>> 2250 Indicates that the platform supports the VPE loader, and provides
>> 2251 physical_memsize.
>> 2252
>> 2253 config MIPS_VPE_LOADER
>> 2254 bool "VPE loader support."
>> 2255 depends on SYS_SUPPORTS_VPE_LOADER && MODULES
>> 2256 select CPU_MIPSR2_IRQ_VI
>> 2257 select CPU_MIPSR2_IRQ_EI
>> 2258 select MIPS_MT
>> 2259 help
>> 2260 Includes a loader for loading an elf relocatable object
>> 2261 onto another VPE and running it.
>> 2262
>> 2263 config MIPS_VPE_LOADER_MT
>> 2264 bool
>> 2265 default "y"
>> 2266 depends on MIPS_VPE_LOADER
>> 2267
>> 2268 config MIPS_VPE_LOADER_TOM
>> 2269 bool "Load VPE program into memory hidden from linux"
>> 2270 depends on MIPS_VPE_LOADER
>> 2271 default y
>> 2272 help
>> 2273 The loader can use memory that is present but has been hidden from
>> 2274 Linux using the kernel command line option "mem=xxMB". It's up to
>> 2275 you to ensure the amount you put in the option and the space your
>> 2276 program requires is less or equal to the amount physically present.
>> 2277
>> 2278 config MIPS_VPE_APSP_API
>> 2279 bool "Enable support for AP/SP API (RTLX)"
>> 2280 depends on MIPS_VPE_LOADER
>> 2281
>> 2282 config MIPS_VPE_APSP_API_MT
>> 2283 bool
>> 2284 default "y"
>> 2285 depends on MIPS_VPE_APSP_API
>> 2286
>> 2287 config MIPS_CPS
>> 2288 bool "MIPS Coherent Processing System support"
>> 2289 depends on SYS_SUPPORTS_MIPS_CPS
>> 2290 select MIPS_CM
>> 2291 select MIPS_CPS_PM if HOTPLUG_CPU
>> 2292 select SMP
>> 2293 select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU
>> 2294 select SYNC_R4K if (CEVT_R4K || CSRC_R4K)
>> 2295 select SYS_SUPPORTS_HOTPLUG_CPU
>> 2296 select SYS_SUPPORTS_SCHED_SMT if CPU_MIPSR6
>> 2297 select SYS_SUPPORTS_SMP
>> 2298 select WEAK_ORDERING
>> 2299 select GENERIC_IRQ_MIGRATION if HOTPLUG_CPU
>> 2300 help
>> 2301 Select this if you wish to run an SMP kernel across multiple cores
>> 2302 within a MIPS Coherent Processing System. When this option is
>> 2303 enabled the kernel will probe for other cores and boot them with
>> 2304 no external assistance. It is safe to enable this when hardware
>> 2305 support is unavailable.
>> 2306
>> 2307 config MIPS_CPS_PM
>> 2308 depends on MIPS_CPS
>> 2309 bool
>> 2310
>> 2311 config MIPS_CM
>> 2312 bool
>> 2313 select MIPS_CPC
>> 2314
>> 2315 config MIPS_CPC
>> 2316 bool
>> 2317
>> 2318 config SB1_PASS_2_WORKAROUNDS
>> 2319 bool
>> 2320 depends on CPU_SB1 && (CPU_SB1_PASS_2_2 || CPU_SB1_PASS_2)
>> 2321 default y
>> 2322
>> 2323 config SB1_PASS_2_1_WORKAROUNDS
>> 2324 bool
>> 2325 depends on CPU_SB1 && CPU_SB1_PASS_2
>> 2326 default y
>> 2327
251 choice 2328 choice
252 prompt "Power Manager Instruction (wai !! 2329 prompt "SmartMIPS or microMIPS ASE support"
253 default CPU_PM_NONE <<
254 2330
255 config CPU_PM_NONE !! 2331 config CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS
256 bool "None" 2332 bool "None"
>> 2333 help
>> 2334 Select this if you want neither microMIPS nor SmartMIPS support
257 2335
258 config CPU_PM_WAIT !! 2336 config CPU_HAS_SMARTMIPS
259 bool "wait" !! 2337 depends on SYS_SUPPORTS_SMARTMIPS
260 !! 2338 bool "SmartMIPS"
261 config CPU_PM_DOZE !! 2339 help
262 bool "doze" !! 2340 SmartMIPS is a extension of the MIPS32 architecture aimed at
>> 2341 increased security at both hardware and software level for
>> 2342 smartcards. Enabling this option will allow proper use of the
>> 2343 SmartMIPS instructions by Linux applications. However a kernel with
>> 2344 this option will not work on a MIPS core without SmartMIPS core. If
>> 2345 you don't know you probably don't have SmartMIPS and should say N
>> 2346 here.
>> 2347
>> 2348 config CPU_MICROMIPS
>> 2349 depends on 32BIT && SYS_SUPPORTS_MICROMIPS && !CPU_MIPSR6
>> 2350 bool "microMIPS"
>> 2351 help
>> 2352 When this option is enabled the kernel will be built using the
>> 2353 microMIPS ISA
263 2354
264 config CPU_PM_STOP <<
265 bool "stop" <<
266 endchoice 2355 endchoice
267 2356
268 menuconfig HAVE_TCM !! 2357 config CPU_HAS_MSA
269 bool "Tightly-Coupled/Sram Memory" !! 2358 bool "Support for the MIPS SIMD Architecture"
270 depends on !COMPILE_TEST !! 2359 depends on CPU_SUPPORTS_MSA
271 help !! 2360 depends on MIPS_FP_SUPPORT
272 The implementation are not only used !! 2361 depends on 64BIT || MIPS_O32_FP64_SUPPORT
273 but also used by sram on SOC bus. It !! 2362 help
274 software interface, so that old tcm !! 2363 MIPS SIMD Architecture (MSA) introduces 128 bit wide vector registers
275 re-used directly. !! 2364 and a set of SIMD instructions to operate on them. When this option
276 !! 2365 is enabled the kernel will support allocating & switching MSA
277 if HAVE_TCM !! 2366 vector register contexts. If you know that your kernel will only be
278 config ITCM_RAM_BASE !! 2367 running on CPUs which do not support MSA or that your userland will
279 hex "ITCM ram base" !! 2368 not be making use of it then you may wish to say N here to reduce
280 default 0xffffffff !! 2369 the size & complexity of your kernel.
281 <<
282 config ITCM_NR_PAGES <<
283 int "Page count of ITCM size: NR*4KB" <<
284 range 1 256 <<
285 default 32 <<
286 <<
287 config HAVE_DTCM <<
288 bool "DTCM Support" <<
289 <<
290 config DTCM_RAM_BASE <<
291 hex "DTCM ram base" <<
292 depends on HAVE_DTCM <<
293 default 0xffffffff <<
294 <<
295 config DTCM_NR_PAGES <<
296 int "Page count of DTCM size: NR*4KB" <<
297 depends on HAVE_DTCM <<
298 range 1 256 <<
299 default 32 <<
300 endif <<
301 <<
302 config CPU_HAS_VDSP <<
303 bool "CPU has VDSP coprocessor" <<
304 depends on CPU_HAS_FPU && CPU_HAS_FPUV <<
305 <<
306 config CPU_HAS_FPU <<
307 bool "CPU has FPU coprocessor" <<
308 depends on CPU_CK807 || CPU_CK810 || C <<
309 <<
310 config CPU_HAS_ICACHE_INS <<
311 bool "CPU has Icache invalidate instru <<
312 depends on CPU_HAS_CACHEV2 <<
313 <<
314 config CPU_HAS_TEE <<
315 bool "CPU has Trusted Execution Enviro <<
316 depends on CPU_CK810 <<
317 2370
318 config SMP !! 2371 If unsure, say Y.
319 bool "Symmetric Multi-Processing (SMP) <<
320 depends on CPU_CK860 <<
321 default n <<
322 2372
323 config NR_CPUS !! 2373 config CPU_HAS_WB
324 int "Maximum number of CPUs (2-32)" !! 2374 bool
325 range 2 32 !! 2375
326 depends on SMP !! 2376 config XKS01
327 default "4" !! 2377 bool
>> 2378
>> 2379 config CPU_HAS_DIEI
>> 2380 depends on !CPU_DIEI_BROKEN
>> 2381 bool
328 2382
>> 2383 config CPU_DIEI_BROKEN
>> 2384 bool
>> 2385
>> 2386 config CPU_HAS_RIXI
>> 2387 bool
>> 2388
>> 2389 config CPU_NO_LOAD_STORE_LR
>> 2390 bool
>> 2391 help
>> 2392 CPU lacks support for unaligned load and store instructions:
>> 2393 LWL, LWR, SWL, SWR (Load/store word left/right).
>> 2394 LDL, LDR, SDL, SDR (Load/store doubleword left/right, for 64bit
>> 2395 systems).
>> 2396
>> 2397 #
>> 2398 # Vectored interrupt mode is an R2 feature
>> 2399 #
>> 2400 config CPU_MIPSR2_IRQ_VI
>> 2401 bool
>> 2402
>> 2403 #
>> 2404 # Extended interrupt mode is an R2 feature
>> 2405 #
>> 2406 config CPU_MIPSR2_IRQ_EI
>> 2407 bool
>> 2408
>> 2409 config CPU_HAS_SYNC
>> 2410 bool
>> 2411 depends on !CPU_R3000
>> 2412 default y
>> 2413
>> 2414 #
>> 2415 # CPU non-features
>> 2416 #
>> 2417
>> 2418 # Work around the "daddi" and "daddiu" CPU errata:
>> 2419 #
>> 2420 # - The `daddi' instruction fails to trap on overflow.
>> 2421 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
>> 2422 # erratum #23
>> 2423 #
>> 2424 # - The `daddiu' instruction can produce an incorrect result.
>> 2425 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
>> 2426 # erratum #41
>> 2427 # "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0", erratum
>> 2428 # #15
>> 2429 # "MIPS R4400PC/SC Errata, Processor Revision 1.0", erratum #7
>> 2430 # "MIPS R4400MC Errata, Processor Revision 1.0", erratum #5
>> 2431 config CPU_DADDI_WORKAROUNDS
>> 2432 bool
>> 2433
>> 2434 # Work around certain R4000 CPU errata (as implemented by GCC):
>> 2435 #
>> 2436 # - A double-word or a variable shift may give an incorrect result
>> 2437 # if executed immediately after starting an integer division:
>> 2438 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
>> 2439 # erratum #28
>> 2440 # "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0", erratum
>> 2441 # #19
>> 2442 #
>> 2443 # - A double-word or a variable shift may give an incorrect result
>> 2444 # if executed while an integer multiplication is in progress:
>> 2445 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
>> 2446 # errata #16 & #28
>> 2447 #
>> 2448 # - An integer division may give an incorrect result if started in
>> 2449 # a delay slot of a taken branch or a jump:
>> 2450 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
>> 2451 # erratum #52
>> 2452 config CPU_R4000_WORKAROUNDS
>> 2453 bool
>> 2454 select CPU_R4400_WORKAROUNDS
>> 2455
>> 2456 # Work around certain R4400 CPU errata (as implemented by GCC):
>> 2457 #
>> 2458 # - A double-word or a variable shift may give an incorrect result
>> 2459 # if executed immediately after starting an integer division:
>> 2460 # "MIPS R4400MC Errata, Processor Revision 1.0", erratum #10
>> 2461 # "MIPS R4400MC Errata, Processor Revision 2.0 & 3.0", erratum #4
>> 2462 config CPU_R4400_WORKAROUNDS
>> 2463 bool
>> 2464
>> 2465 config CPU_R4X00_BUGS64
>> 2466 bool
>> 2467 default y if SYS_HAS_CPU_R4X00 && 64BIT && (TARGET_ISA_REV < 1)
>> 2468
>> 2469 config MIPS_ASID_SHIFT
>> 2470 int
>> 2471 default 6 if CPU_R3000
>> 2472 default 0
>> 2473
>> 2474 config MIPS_ASID_BITS
>> 2475 int
>> 2476 default 0 if MIPS_ASID_BITS_VARIABLE
>> 2477 default 6 if CPU_R3000
>> 2478 default 8
>> 2479
>> 2480 config MIPS_ASID_BITS_VARIABLE
>> 2481 bool
>> 2482
>> 2483 config MIPS_CRC_SUPPORT
>> 2484 bool
>> 2485
>> 2486 # R4600 erratum. Due to the lack of errata information the exact
>> 2487 # technical details aren't known. I've experimentally found that disabling
>> 2488 # interrupts during indexed I-cache flushes seems to be sufficient to deal
>> 2489 # with the issue.
>> 2490 config WAR_R4600_V1_INDEX_ICACHEOP
>> 2491 bool
>> 2492
>> 2493 # Pleasures of the R4600 V1.x. Cite from the IDT R4600 V1.7 errata:
>> 2494 #
>> 2495 # 18. The CACHE instructions Hit_Writeback_Invalidate_D, Hit_Writeback_D,
>> 2496 # Hit_Invalidate_D and Create_Dirty_Excl_D should only be
>> 2497 # executed if there is no other dcache activity. If the dcache is
>> 2498 # accessed for another instruction immediately preceding when these
>> 2499 # cache instructions are executing, it is possible that the dcache
>> 2500 # tag match outputs used by these cache instructions will be
>> 2501 # incorrect. These cache instructions should be preceded by at least
>> 2502 # four instructions that are not any kind of load or store
>> 2503 # instruction.
>> 2504 #
>> 2505 # This is not allowed: lw
>> 2506 # nop
>> 2507 # nop
>> 2508 # nop
>> 2509 # cache Hit_Writeback_Invalidate_D
>> 2510 #
>> 2511 # This is allowed: lw
>> 2512 # nop
>> 2513 # nop
>> 2514 # nop
>> 2515 # nop
>> 2516 # cache Hit_Writeback_Invalidate_D
>> 2517 config WAR_R4600_V1_HIT_CACHEOP
>> 2518 bool
>> 2519
>> 2520 # Writeback and invalidate the primary cache dcache before DMA.
>> 2521 #
>> 2522 # R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D,
>> 2523 # Hit_Writeback_D, Hit_Invalidate_D and Create_Dirty_Exclusive_D will only
>> 2524 # operate correctly if the internal data cache refill buffer is empty. These
>> 2525 # CACHE instructions should be separated from any potential data cache miss
>> 2526 # by a load instruction to an uncached address to empty the response buffer."
>> 2527 # (Revision 2.0 device errata from IDT available on https://www.idt.com/
>> 2528 # in .pdf format.)
>> 2529 config WAR_R4600_V2_HIT_CACHEOP
>> 2530 bool
>> 2531
>> 2532 # From TX49/H2 manual: "If the instruction (i.e. CACHE) is issued for
>> 2533 # the line which this instruction itself exists, the following
>> 2534 # operation is not guaranteed."
>> 2535 #
>> 2536 # Workaround: do two phase flushing for Index_Invalidate_I
>> 2537 config WAR_TX49XX_ICACHE_INDEX_INV
>> 2538 bool
>> 2539
>> 2540 # The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra
>> 2541 # opposes it being called that) where invalid instructions in the same
>> 2542 # I-cache line worth of instructions being fetched may case spurious
>> 2543 # exceptions.
>> 2544 config WAR_ICACHE_REFILLS
>> 2545 bool
>> 2546
>> 2547 # On the R10000 up to version 2.6 (not sure about 2.7) there is a bug that
>> 2548 # may cause ll / sc and lld / scd sequences to execute non-atomically.
>> 2549 config WAR_R10000_LLSC
>> 2550 bool
>> 2551
>> 2552 # 34K core erratum: "Problems Executing the TLBR Instruction"
>> 2553 config WAR_MIPS34K_MISSED_ITLB
>> 2554 bool
>> 2555
>> 2556 #
>> 2557 # - Highmem only makes sense for the 32-bit kernel.
>> 2558 # - The current highmem code will only work properly on physically indexed
>> 2559 # caches such as R3000, SB1, R7000 or those that look like they're virtually
>> 2560 # indexed such as R4000/R4400 SC and MC versions or R10000. So for the
>> 2561 # moment we protect the user and offer the highmem option only on machines
>> 2562 # where it's known to be safe. This will not offer highmem on a few systems
>> 2563 # such as MIPS32 and MIPS64 CPUs which may have virtual and physically
>> 2564 # indexed CPUs but we're playing safe.
>> 2565 # - We use SYS_SUPPORTS_HIGHMEM to offer highmem only for systems where we
>> 2566 # know they might have memory configurations that could make use of highmem
>> 2567 # support.
>> 2568 #
329 config HIGHMEM 2569 config HIGHMEM
330 bool "High Memory Support" 2570 bool "High Memory Support"
331 depends on !CPU_CK610 !! 2571 depends on 32BIT && CPU_SUPPORTS_HIGHMEM && SYS_SUPPORTS_HIGHMEM && !CPU_MIPS32_3_5_EVA
332 select KMAP_LOCAL 2572 select KMAP_LOCAL
>> 2573
>> 2574 config CPU_SUPPORTS_HIGHMEM
>> 2575 bool
>> 2576
>> 2577 config SYS_SUPPORTS_HIGHMEM
>> 2578 bool
>> 2579
>> 2580 config SYS_SUPPORTS_SMARTMIPS
>> 2581 bool
>> 2582
>> 2583 config SYS_SUPPORTS_MICROMIPS
>> 2584 bool
>> 2585
>> 2586 config SYS_SUPPORTS_MIPS16
>> 2587 bool
>> 2588 help
>> 2589 This option must be set if a kernel might be executed on a MIPS16-
>> 2590 enabled CPU even if MIPS16 is not actually being used. In other
>> 2591 words, it makes the kernel MIPS16-tolerant.
>> 2592
>> 2593 config CPU_SUPPORTS_MSA
>> 2594 bool
>> 2595
>> 2596 config ARCH_FLATMEM_ENABLE
>> 2597 def_bool y
>> 2598 depends on !NUMA && !CPU_LOONGSON2EF
>> 2599
>> 2600 config ARCH_SPARSEMEM_ENABLE
>> 2601 bool
>> 2602
>> 2603 config NUMA
>> 2604 bool "NUMA Support"
>> 2605 depends on SYS_SUPPORTS_NUMA
>> 2606 select SMP
>> 2607 select HAVE_SETUP_PER_CPU_AREA
>> 2608 select NEED_PER_CPU_EMBED_FIRST_CHUNK
>> 2609 help
>> 2610 Say Y to compile the kernel to support NUMA (Non-Uniform Memory
>> 2611 Access). This option improves performance on systems with more
>> 2612 than two nodes; on two node systems it is generally better to
>> 2613 leave it disabled; on single node systems leave this option
>> 2614 disabled.
>> 2615
>> 2616 config SYS_SUPPORTS_NUMA
>> 2617 bool
>> 2618
>> 2619 config HAVE_ARCH_NODEDATA_EXTENSION
>> 2620 bool
>> 2621
>> 2622 config RELOCATABLE
>> 2623 bool "Relocatable kernel"
>> 2624 depends on SYS_SUPPORTS_RELOCATABLE
>> 2625 depends on CPU_MIPS32_R2 || CPU_MIPS64_R2 || \
>> 2626 CPU_MIPS32_R5 || CPU_MIPS64_R5 || \
>> 2627 CPU_MIPS32_R6 || CPU_MIPS64_R6 || \
>> 2628 CPU_P5600 || CAVIUM_OCTEON_SOC || \
>> 2629 CPU_LOONGSON64
>> 2630 help
>> 2631 This builds a kernel image that retains relocation information
>> 2632 so it can be loaded someplace besides the default 1MB.
>> 2633 The relocations make the kernel binary about 15% larger,
>> 2634 but are discarded at runtime
>> 2635
>> 2636 config RELOCATION_TABLE_SIZE
>> 2637 hex "Relocation table size"
>> 2638 depends on RELOCATABLE
>> 2639 range 0x0 0x01000000
>> 2640 default "0x00200000" if CPU_LOONGSON64
>> 2641 default "0x00100000"
>> 2642 help
>> 2643 A table of relocation data will be appended to the kernel binary
>> 2644 and parsed at boot to fix up the relocated kernel.
>> 2645
>> 2646 This option allows the amount of space reserved for the table to be
>> 2647 adjusted, although the default of 1Mb should be ok in most cases.
>> 2648
>> 2649 The build will fail and a valid size suggested if this is too small.
>> 2650
>> 2651 If unsure, leave at the default value.
>> 2652
>> 2653 config RANDOMIZE_BASE
>> 2654 bool "Randomize the address of the kernel image"
>> 2655 depends on RELOCATABLE
>> 2656 help
>> 2657 Randomizes the physical and virtual address at which the
>> 2658 kernel image is loaded, as a security feature that
>> 2659 deters exploit attempts relying on knowledge of the location
>> 2660 of kernel internals.
>> 2661
>> 2662 Entropy is generated using any coprocessor 0 registers available.
>> 2663
>> 2664 The kernel will be offset by up to RANDOMIZE_BASE_MAX_OFFSET.
>> 2665
>> 2666 If unsure, say N.
>> 2667
>> 2668 config RANDOMIZE_BASE_MAX_OFFSET
>> 2669 hex "Maximum kASLR offset" if EXPERT
>> 2670 depends on RANDOMIZE_BASE
>> 2671 range 0x0 0x40000000 if EVA || 64BIT
>> 2672 range 0x0 0x08000000
>> 2673 default "0x01000000"
>> 2674 help
>> 2675 When kASLR is active, this provides the maximum offset that will
>> 2676 be applied to the kernel image. It should be set according to the
>> 2677 amount of physical RAM available in the target system minus
>> 2678 PHYSICAL_START and must be a power of 2.
>> 2679
>> 2680 This is limited by the size of KSEG0, 256Mb on 32-bit or 1Gb with
>> 2681 EVA or 64-bit. The default is 16Mb.
>> 2682
>> 2683 config NODES_SHIFT
>> 2684 int
>> 2685 default "6"
>> 2686 depends on NUMA
>> 2687
>> 2688 config HW_PERF_EVENTS
>> 2689 bool "Enable hardware performance counter support for perf events"
>> 2690 depends on PERF_EVENTS && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON || CPU_LOONGSON64)
333 default y 2691 default y
>> 2692 help
>> 2693 Enable hardware performance counter support for perf events. If
>> 2694 disabled, perf events will use software events only.
334 2695
335 config DRAM_BASE !! 2696 config DMI
336 hex "DRAM start addr (the same with me !! 2697 bool "Enable DMI scanning"
337 default 0x0 !! 2698 depends on MACH_LOONGSON64
>> 2699 select DMI_SCAN_MACHINE_NON_EFI_FALLBACK
>> 2700 default y
>> 2701 help
>> 2702 Enabled scanning of DMI to identify machine quirks. Say Y
>> 2703 here unless you have verified that your setup is not
>> 2704 affected by entries in the DMI blacklist. Required by PNP
>> 2705 BIOS code.
>> 2706
>> 2707 config SMP
>> 2708 bool "Multi-Processing support"
>> 2709 depends on SYS_SUPPORTS_SMP
>> 2710 help
>> 2711 This enables support for systems with more than one CPU. If you have
>> 2712 a system with only one CPU, say N. If you have a system with more
>> 2713 than one CPU, say Y.
>> 2714
>> 2715 If you say N here, the kernel will run on uni- and multiprocessor
>> 2716 machines, but will use only one CPU of a multiprocessor machine. If
>> 2717 you say Y here, the kernel will run on many, but not all,
>> 2718 uniprocessor machines. On a uniprocessor machine, the kernel
>> 2719 will run faster if you say N here.
>> 2720
>> 2721 People using multiprocessor machines who say Y here should also say
>> 2722 Y to "Enhanced Real Time Clock Support", below.
>> 2723
>> 2724 See also the SMP-HOWTO available at
>> 2725 <https://www.tldp.org/docs.html#howto>.
>> 2726
>> 2727 If you don't know what to do here, say N.
338 2728
339 config HOTPLUG_CPU 2729 config HOTPLUG_CPU
340 bool "Support for hot-pluggable CPUs" 2730 bool "Support for hot-pluggable CPUs"
341 select GENERIC_IRQ_MIGRATION !! 2731 depends on SMP && SYS_SUPPORTS_HOTPLUG_CPU
342 depends on SMP <<
343 help 2732 help
344 Say Y here to allow turning CPUs off 2733 Say Y here to allow turning CPUs off and on. CPUs can be
345 controlled through /sys/devices/syst !! 2734 controlled through /sys/devices/system/cpu.
346 !! 2735 (Note: power management support will enable this option
>> 2736 automatically on SMP systems. )
347 Say N if you want to disable CPU hot 2737 Say N if you want to disable CPU hotplug.
348 2738
349 config HAVE_EFFICIENT_UNALIGNED_STRING_OPS !! 2739 config SMP_UP
350 bool "Enable EFFICIENT_UNALIGNED_STRIN !! 2740 bool
351 depends on CPU_CK807 || CPU_CK810 || C !! 2741
>> 2742 config SYS_SUPPORTS_MIPS_CPS
>> 2743 bool
>> 2744
>> 2745 config SYS_SUPPORTS_SMP
>> 2746 bool
>> 2747
>> 2748 config NR_CPUS_DEFAULT_4
>> 2749 bool
>> 2750
>> 2751 config NR_CPUS_DEFAULT_8
>> 2752 bool
>> 2753
>> 2754 config NR_CPUS_DEFAULT_16
>> 2755 bool
>> 2756
>> 2757 config NR_CPUS_DEFAULT_32
>> 2758 bool
>> 2759
>> 2760 config NR_CPUS_DEFAULT_64
>> 2761 bool
>> 2762
>> 2763 config NR_CPUS
>> 2764 int "Maximum number of CPUs (2-256)"
>> 2765 range 2 256
>> 2766 depends on SMP
>> 2767 default "4" if NR_CPUS_DEFAULT_4
>> 2768 default "8" if NR_CPUS_DEFAULT_8
>> 2769 default "16" if NR_CPUS_DEFAULT_16
>> 2770 default "32" if NR_CPUS_DEFAULT_32
>> 2771 default "64" if NR_CPUS_DEFAULT_64
352 help 2772 help
353 Say Y here to enable EFFICIENT_UNALI !! 2773 This allows you to specify the maximum number of CPUs which this
354 deal with unaligned access by hardwa !! 2774 kernel will support. The maximum supported value is 32 for 32-bit
>> 2775 kernel and 64 for 64-bit kernels; the minimum value which makes
>> 2776 sense is 1 for Qemu (useful only for kernel debugging purposes)
>> 2777 and 2 for all others.
>> 2778
>> 2779 This is purely to save memory - each supported CPU adds
>> 2780 approximately eight kilobytes to the kernel image. For best
>> 2781 performance should round up your number of processors to the next
>> 2782 power of two.
>> 2783
>> 2784 config MIPS_PERF_SHARED_TC_COUNTERS
>> 2785 bool
>> 2786
>> 2787 config MIPS_NR_CPU_NR_MAP_1024
>> 2788 bool
>> 2789
>> 2790 config MIPS_NR_CPU_NR_MAP
>> 2791 int
>> 2792 depends on SMP
>> 2793 default 1024 if MIPS_NR_CPU_NR_MAP_1024
>> 2794 default NR_CPUS if !MIPS_NR_CPU_NR_MAP_1024
>> 2795
>> 2796 #
>> 2797 # Timer Interrupt Frequency Configuration
>> 2798 #
>> 2799
>> 2800 choice
>> 2801 prompt "Timer frequency"
>> 2802 default HZ_250
>> 2803 help
>> 2804 Allows the configuration of the timer frequency.
>> 2805
>> 2806 config HZ_24
>> 2807 bool "24 HZ" if SYS_SUPPORTS_24HZ || SYS_SUPPORTS_ARBIT_HZ
>> 2808
>> 2809 config HZ_48
>> 2810 bool "48 HZ" if SYS_SUPPORTS_48HZ || SYS_SUPPORTS_ARBIT_HZ
>> 2811
>> 2812 config HZ_100
>> 2813 bool "100 HZ" if SYS_SUPPORTS_100HZ || SYS_SUPPORTS_ARBIT_HZ
>> 2814
>> 2815 config HZ_128
>> 2816 bool "128 HZ" if SYS_SUPPORTS_128HZ || SYS_SUPPORTS_ARBIT_HZ
>> 2817
>> 2818 config HZ_250
>> 2819 bool "250 HZ" if SYS_SUPPORTS_250HZ || SYS_SUPPORTS_ARBIT_HZ
>> 2820
>> 2821 config HZ_256
>> 2822 bool "256 HZ" if SYS_SUPPORTS_256HZ || SYS_SUPPORTS_ARBIT_HZ
>> 2823
>> 2824 config HZ_1000
>> 2825 bool "1000 HZ" if SYS_SUPPORTS_1000HZ || SYS_SUPPORTS_ARBIT_HZ
>> 2826
>> 2827 config HZ_1024
>> 2828 bool "1024 HZ" if SYS_SUPPORTS_1024HZ || SYS_SUPPORTS_ARBIT_HZ
>> 2829
>> 2830 endchoice
>> 2831
>> 2832 config SYS_SUPPORTS_24HZ
>> 2833 bool
>> 2834
>> 2835 config SYS_SUPPORTS_48HZ
>> 2836 bool
>> 2837
>> 2838 config SYS_SUPPORTS_100HZ
>> 2839 bool
>> 2840
>> 2841 config SYS_SUPPORTS_128HZ
>> 2842 bool
>> 2843
>> 2844 config SYS_SUPPORTS_250HZ
>> 2845 bool
>> 2846
>> 2847 config SYS_SUPPORTS_256HZ
>> 2848 bool
>> 2849
>> 2850 config SYS_SUPPORTS_1000HZ
>> 2851 bool
>> 2852
>> 2853 config SYS_SUPPORTS_1024HZ
>> 2854 bool
>> 2855
>> 2856 config SYS_SUPPORTS_ARBIT_HZ
>> 2857 bool
>> 2858 default y if !SYS_SUPPORTS_24HZ && \
>> 2859 !SYS_SUPPORTS_48HZ && \
>> 2860 !SYS_SUPPORTS_100HZ && \
>> 2861 !SYS_SUPPORTS_128HZ && \
>> 2862 !SYS_SUPPORTS_250HZ && \
>> 2863 !SYS_SUPPORTS_256HZ && \
>> 2864 !SYS_SUPPORTS_1000HZ && \
>> 2865 !SYS_SUPPORTS_1024HZ
>> 2866
>> 2867 config HZ
>> 2868 int
>> 2869 default 24 if HZ_24
>> 2870 default 48 if HZ_48
>> 2871 default 100 if HZ_100
>> 2872 default 128 if HZ_128
>> 2873 default 250 if HZ_250
>> 2874 default 256 if HZ_256
>> 2875 default 1000 if HZ_1000
>> 2876 default 1024 if HZ_1024
>> 2877
>> 2878 config SCHED_HRTICK
>> 2879 def_bool HIGH_RES_TIMERS
>> 2880
>> 2881 config KEXEC
>> 2882 bool "Kexec system call"
>> 2883 select KEXEC_CORE
>> 2884 help
>> 2885 kexec is a system call that implements the ability to shutdown your
>> 2886 current kernel, and to start another kernel. It is like a reboot
>> 2887 but it is independent of the system firmware. And like a reboot
>> 2888 you can start any kernel with it, not just Linux.
>> 2889
>> 2890 The name comes from the similarity to the exec system call.
>> 2891
>> 2892 It is an ongoing process to be certain the hardware in a machine
>> 2893 is properly shutdown, so do not be surprised if this code does not
>> 2894 initially work for you. As of this writing the exact hardware
>> 2895 interface is strongly in flux, so no good recommendation can be
>> 2896 made.
>> 2897
>> 2898 config CRASH_DUMP
>> 2899 bool "Kernel crash dumps"
>> 2900 help
>> 2901 Generate crash dump after being started by kexec.
>> 2902 This should be normally only set in special crash dump kernels
>> 2903 which are loaded in the main kernel with kexec-tools into
>> 2904 a specially reserved region and then later executed after
>> 2905 a crash by kdump/kexec. The crash dump kernel must be compiled
>> 2906 to a memory address not used by the main kernel or firmware using
>> 2907 PHYSICAL_START.
>> 2908
>> 2909 config PHYSICAL_START
>> 2910 hex "Physical address where the kernel is loaded"
>> 2911 default "0xffffffff84000000"
>> 2912 depends on CRASH_DUMP
>> 2913 help
>> 2914 This gives the CKSEG0 or KSEG0 address where the kernel is loaded.
>> 2915 If you plan to use kernel for capturing the crash dump change
>> 2916 this value to start of the reserved region (the "X" value as
>> 2917 specified in the "crashkernel=YM@XM" command line boot parameter
>> 2918 passed to the panic-ed kernel).
>> 2919
>> 2920 config MIPS_O32_FP64_SUPPORT
>> 2921 bool "Support for O32 binaries using 64-bit FP" if !CPU_MIPSR6
>> 2922 depends on 32BIT || MIPS32_O32
>> 2923 help
>> 2924 When this is enabled, the kernel will support use of 64-bit floating
>> 2925 point registers with binaries using the O32 ABI along with the
>> 2926 EF_MIPS_FP64 ELF header flag (typically built with -mfp64). On
>> 2927 32-bit MIPS systems this support is at the cost of increasing the
>> 2928 size and complexity of the compiled FPU emulator. Thus if you are
>> 2929 running a MIPS32 system and know that none of your userland binaries
>> 2930 will require 64-bit floating point, you may wish to reduce the size
>> 2931 of your kernel & potentially improve FP emulation performance by
>> 2932 saying N here.
>> 2933
>> 2934 Although binutils currently supports use of this flag the details
>> 2935 concerning its effect upon the O32 ABI in userland are still being
>> 2936 worked on. In order to avoid userland becoming dependent upon current
>> 2937 behaviour before the details have been finalised, this option should
>> 2938 be considered experimental and only enabled by those working upon
>> 2939 said details.
>> 2940
>> 2941 If unsure, say N.
>> 2942
>> 2943 config USE_OF
>> 2944 bool
>> 2945 select OF
>> 2946 select OF_EARLY_FLATTREE
>> 2947 select IRQ_DOMAIN
>> 2948
>> 2949 config UHI_BOOT
>> 2950 bool
>> 2951
>> 2952 config BUILTIN_DTB
>> 2953 bool
>> 2954
>> 2955 choice
>> 2956 prompt "Kernel appended dtb support" if USE_OF
>> 2957 default MIPS_NO_APPENDED_DTB
>> 2958
>> 2959 config MIPS_NO_APPENDED_DTB
>> 2960 bool "None"
>> 2961 help
>> 2962 Do not enable appended dtb support.
>> 2963
>> 2964 config MIPS_ELF_APPENDED_DTB
>> 2965 bool "vmlinux"
>> 2966 help
>> 2967 With this option, the boot code will look for a device tree binary
>> 2968 DTB) included in the vmlinux ELF section .appended_dtb. By default
>> 2969 it is empty and the DTB can be appended using binutils command
>> 2970 objcopy:
>> 2971
>> 2972 objcopy --update-section .appended_dtb=<filename>.dtb vmlinux
>> 2973
>> 2974 This is meant as a backward compatibility convenience for those
>> 2975 systems with a bootloader that can't be upgraded to accommodate
>> 2976 the documented boot protocol using a device tree.
>> 2977
>> 2978 config MIPS_RAW_APPENDED_DTB
>> 2979 bool "vmlinux.bin or vmlinuz.bin"
>> 2980 help
>> 2981 With this option, the boot code will look for a device tree binary
>> 2982 DTB) appended to raw vmlinux.bin or vmlinuz.bin.
>> 2983 (e.g. cat vmlinux.bin <filename>.dtb > vmlinux_w_dtb).
>> 2984
>> 2985 This is meant as a backward compatibility convenience for those
>> 2986 systems with a bootloader that can't be upgraded to accommodate
>> 2987 the documented boot protocol using a device tree.
>> 2988
>> 2989 Beware that there is very little in terms of protection against
>> 2990 this option being confused by leftover garbage in memory that might
>> 2991 look like a DTB header after a reboot if no actual DTB is appended
>> 2992 to vmlinux.bin. Do not leave this option active in a production kernel
>> 2993 if you don't intend to always append a DTB.
>> 2994 endchoice
>> 2995
>> 2996 choice
>> 2997 prompt "Kernel command line type" if !CMDLINE_OVERRIDE
>> 2998 default MIPS_CMDLINE_FROM_DTB if USE_OF && !ATH79 && !MACH_INGENIC && \
>> 2999 !MACH_LOONGSON64 && !MIPS_MALTA && \
>> 3000 !CAVIUM_OCTEON_SOC
>> 3001 default MIPS_CMDLINE_FROM_BOOTLOADER
>> 3002
>> 3003 config MIPS_CMDLINE_FROM_DTB
>> 3004 depends on USE_OF
>> 3005 bool "Dtb kernel arguments if available"
>> 3006
>> 3007 config MIPS_CMDLINE_DTB_EXTEND
>> 3008 depends on USE_OF
>> 3009 bool "Extend dtb kernel arguments with bootloader arguments"
>> 3010
>> 3011 config MIPS_CMDLINE_FROM_BOOTLOADER
>> 3012 bool "Bootloader kernel arguments if available"
>> 3013
>> 3014 config MIPS_CMDLINE_BUILTIN_EXTEND
>> 3015 depends on CMDLINE_BOOL
>> 3016 bool "Extend builtin kernel arguments with bootloader arguments"
>> 3017 endchoice
>> 3018
>> 3019 endmenu
>> 3020
>> 3021 config LOCKDEP_SUPPORT
>> 3022 bool
>> 3023 default y
>> 3024
>> 3025 config STACKTRACE_SUPPORT
>> 3026 bool
>> 3027 default y
>> 3028
>> 3029 config PGTABLE_LEVELS
>> 3030 int
>> 3031 default 4 if PAGE_SIZE_4KB && MIPS_VA_BITS_48
>> 3032 default 3 if 64BIT && (!PAGE_SIZE_64KB || MIPS_VA_BITS_48)
>> 3033 default 2
>> 3034
>> 3035 config MIPS_AUTO_PFN_OFFSET
>> 3036 bool
>> 3037
>> 3038 menu "Bus options (PCI, PCMCIA, EISA, ISA, TC)"
>> 3039
>> 3040 config PCI_DRIVERS_GENERIC
>> 3041 select PCI_DOMAINS_GENERIC if PCI
>> 3042 bool
>> 3043
>> 3044 config PCI_DRIVERS_LEGACY
>> 3045 def_bool !PCI_DRIVERS_GENERIC
>> 3046 select NO_GENERIC_PCI_IOPORT_MAP
>> 3047 select PCI_DOMAINS if PCI
>> 3048
>> 3049 #
>> 3050 # ISA support is now enabled via select. Too many systems still have the one
>> 3051 # or other ISA chip on the board that users don't know about so don't expect
>> 3052 # users to choose the right thing ...
>> 3053 #
>> 3054 config ISA
>> 3055 bool
>> 3056
>> 3057 config TC
>> 3058 bool "TURBOchannel support"
>> 3059 depends on MACH_DECSTATION
>> 3060 help
>> 3061 TURBOchannel is a DEC (now Compaq (now HP)) bus for Alpha and MIPS
>> 3062 processors. TURBOchannel programming specifications are available
>> 3063 at:
>> 3064 <ftp://ftp.hp.com/pub/alphaserver/archive/triadd/>
>> 3065 and:
>> 3066 <http://www.computer-refuge.org/classiccmp/ftp.digital.com/pub/DEC/TriAdd/>
>> 3067 Linux driver support status is documented at:
>> 3068 <http://www.linux-mips.org/wiki/DECstation>
>> 3069
>> 3070 config MMU
>> 3071 bool
>> 3072 default y
>> 3073
>> 3074 config ARCH_MMAP_RND_BITS_MIN
>> 3075 default 12 if 64BIT
>> 3076 default 8
>> 3077
>> 3078 config ARCH_MMAP_RND_BITS_MAX
>> 3079 default 18 if 64BIT
>> 3080 default 15
>> 3081
>> 3082 config ARCH_MMAP_RND_COMPAT_BITS_MIN
>> 3083 default 8
>> 3084
>> 3085 config ARCH_MMAP_RND_COMPAT_BITS_MAX
>> 3086 default 15
>> 3087
>> 3088 config I8253
>> 3089 bool
>> 3090 select CLKSRC_I8253
>> 3091 select CLKEVT_I8253
>> 3092 select MIPS_EXTERNAL_TIMER
>> 3093 endmenu
>> 3094
>> 3095 config TRAD_SIGNALS
>> 3096 bool
>> 3097
>> 3098 config MIPS32_COMPAT
>> 3099 bool
>> 3100
>> 3101 config COMPAT
>> 3102 bool
>> 3103
>> 3104 config MIPS32_O32
>> 3105 bool "Kernel support for o32 binaries"
>> 3106 depends on 64BIT
>> 3107 select ARCH_WANT_OLD_COMPAT_IPC
>> 3108 select COMPAT
>> 3109 select MIPS32_COMPAT
>> 3110 help
>> 3111 Select this option if you want to run o32 binaries. These are pure
>> 3112 32-bit binaries as used by the 32-bit Linux/MIPS port. Most of
>> 3113 existing binaries are in this format.
>> 3114
>> 3115 If unsure, say Y.
>> 3116
>> 3117 config MIPS32_N32
>> 3118 bool "Kernel support for n32 binaries"
>> 3119 depends on 64BIT
>> 3120 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
>> 3121 select COMPAT
>> 3122 select MIPS32_COMPAT
>> 3123 help
>> 3124 Select this option if you want to run n32 binaries. These are
>> 3125 64-bit binaries using 32-bit quantities for addressing and certain
>> 3126 data that would normally be 64-bit. They are used in special
>> 3127 cases.
>> 3128
>> 3129 If unsure, say N.
>> 3130
>> 3131 config CC_HAS_MNO_BRANCH_LIKELY
>> 3132 def_bool y
>> 3133 depends on $(cc-option,-mno-branch-likely)
>> 3134
>> 3135 # https://github.com/llvm/llvm-project/issues/61045
>> 3136 config CC_HAS_BROKEN_INLINE_COMPAT_BRANCH
>> 3137 def_bool y if CC_IS_CLANG
>> 3138
>> 3139 menu "Power management options"
>> 3140
>> 3141 config ARCH_HIBERNATION_POSSIBLE
>> 3142 def_bool y
>> 3143 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
>> 3144
>> 3145 config ARCH_SUSPEND_POSSIBLE
>> 3146 def_bool y
>> 3147 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
>> 3148
>> 3149 source "kernel/power/Kconfig"
>> 3150
>> 3151 endmenu
>> 3152
>> 3153 config MIPS_EXTERNAL_TIMER
>> 3154 bool
>> 3155
>> 3156 menu "CPU Power Management"
>> 3157
>> 3158 if CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
>> 3159 source "drivers/cpufreq/Kconfig"
>> 3160 endif # CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
>> 3161
>> 3162 source "drivers/cpuidle/Kconfig"
355 3163
356 endmenu 3164 endmenu
357 3165
358 source "arch/csky/Kconfig.platforms" !! 3166 source "arch/mips/kvm/Kconfig"
359 3167
360 source "kernel/Kconfig.hz" !! 3168 source "arch/mips/vdso/Kconfig"
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