1 /* SPDX-License-Identifier: GPL-2.0 */ 1 /* SPDX-License-Identifier: GPL-2.0 */
>> 2 #include <asm/asm-offsets.h>
>> 3 #include <asm/thread_info.h>
2 4
3 #include <asm/vmlinux.lds.h> !! 5 #define PAGE_SIZE _PAGE_SIZE
4 #include <asm/page.h> <<
5 #include <asm/memory.h> <<
6 6
7 OUTPUT_ARCH(csky) !! 7 /*
8 ENTRY(_start) !! 8 * Put .bss..swapper_pg_dir as the first thing in .bss. This will
9 !! 9 * ensure that it has .bss alignment (64K).
10 #ifndef __cskyBE__ !! 10 */
11 jiffies = jiffies_64; !! 11 #define BSS_FIRST_SECTIONS *(.bss..swapper_pg_dir)
>> 12
>> 13 #include <asm-generic/vmlinux.lds.h>
>> 14
>> 15 #undef mips
>> 16 #define mips mips
>> 17 OUTPUT_ARCH(mips)
>> 18 ENTRY(kernel_entry)
>> 19 PHDRS {
>> 20 text PT_LOAD FLAGS(7); /* RWX */
>> 21 #ifndef CONFIG_CAVIUM_OCTEON_SOC
>> 22 note PT_NOTE FLAGS(4); /* R__ */
>> 23 #endif /* CAVIUM_OCTEON_SOC */
>> 24 }
>> 25
>> 26 #ifdef CONFIG_32BIT
>> 27 #ifdef CONFIG_CPU_LITTLE_ENDIAN
>> 28 jiffies = jiffies_64;
>> 29 #else
>> 30 jiffies = jiffies_64 + 4;
>> 31 #endif
12 #else 32 #else
13 jiffies = jiffies_64 + 4; !! 33 jiffies = jiffies_64;
14 #endif 34 #endif
15 35
16 #define VBR_BASE \ <<
17 . = ALIGN(1024); \ <<
18 vec_base = .; \ <<
19 . += 512; <<
20 <<
21 SECTIONS 36 SECTIONS
22 { 37 {
23 . = PAGE_OFFSET + PHYS_OFFSET_OFFSET; !! 38 #ifdef CONFIG_BOOT_ELF64
>> 39 /* Read-only sections, merged into text segment: */
>> 40 /* . = 0xc000000000000000; */
>> 41
>> 42 /* This is the value for an Origin kernel, taken from an IRIX kernel. */
>> 43 /* . = 0xc00000000001c000; */
>> 44
>> 45 /* Set the vaddr for the text segment to a value
>> 46 * >= 0xa800 0000 0001 9000 if no symmon is going to configured
>> 47 * >= 0xa800 0000 0030 0000 otherwise
>> 48 */
24 49
25 _start = .; !! 50 /* . = 0xa800000000300000; */
26 HEAD_TEXT_SECTION !! 51 . = 0xffffffff80300000;
27 . = ALIGN(PAGE_SIZE); !! 52 #endif
28 !! 53 . = VMLINUX_LOAD_ADDRESS;
29 .text : AT(ADDR(.text) - LOAD_OFFSET) !! 54 /* read-only */
30 _text = .; !! 55 _text = .; /* Text and read-only data */
31 _stext = .; !! 56 .text : {
32 VBR_BASE <<
33 IRQENTRY_TEXT <<
34 SOFTIRQENTRY_TEXT <<
35 TEXT_TEXT 57 TEXT_TEXT
36 SCHED_TEXT 58 SCHED_TEXT
>> 59 CPUIDLE_TEXT
37 LOCK_TEXT 60 LOCK_TEXT
38 KPROBES_TEXT 61 KPROBES_TEXT
>> 62 IRQENTRY_TEXT
>> 63 SOFTIRQENTRY_TEXT
>> 64 *(.text.*)
39 *(.fixup) 65 *(.fixup)
40 *(.gnu.warning) 66 *(.gnu.warning)
41 } = 0 !! 67 } :text = 0
42 _etext = .; !! 68 _etext = .; /* End of text section */
43 69
44 /* __init_begin __init_end must be pag !! 70 EXCEPTION_TABLE(16)
45 . = ALIGN(PAGE_SIZE); <<
46 __init_begin = .; <<
47 INIT_TEXT_SECTION(PAGE_SIZE) <<
48 INIT_DATA_SECTION(PAGE_SIZE) <<
49 PERCPU_SECTION(L1_CACHE_BYTES) <<
50 . = ALIGN(PAGE_SIZE); <<
51 __init_end = .; <<
52 71
53 _sdata = .; !! 72 /* Exception table for data bus errors */
54 RO_DATA(PAGE_SIZE) !! 73 __dbe_table : {
55 RW_DATA(L1_CACHE_BYTES, PAGE_SIZE, THR !! 74 __start___dbe_table = .;
56 _edata = .; !! 75 *(__dbe_table)
57 !! 76 __stop___dbe_table = .;
58 #ifdef CONFIG_HAVE_TCM <<
59 .tcm_start : { <<
60 . = ALIGN(PAGE_SIZE); <<
61 __tcm_start = .; <<
62 } <<
63 <<
64 .text_data_tcm FIXADDR_TCM : AT(__tcm_ <<
65 { <<
66 . = ALIGN(4); <<
67 __stcm_text_data = .; <<
68 *(.tcm.text) <<
69 *(.tcm.rodata) <<
70 #ifndef CONFIG_HAVE_DTCM <<
71 *(.tcm.data) <<
72 #endif <<
73 . = ALIGN(4); <<
74 __etcm_text_data = .; <<
75 } 77 }
76 78
77 . = ADDR(.tcm_start) + SIZEOF(.tcm_sta !! 79 #ifdef CONFIG_CAVIUM_OCTEON_SOC
>> 80 #define NOTES_HEADER
>> 81 #else /* CONFIG_CAVIUM_OCTEON_SOC */
>> 82 #define NOTES_HEADER :note
>> 83 #endif /* CONFIG_CAVIUM_OCTEON_SOC */
>> 84 NOTES :text NOTES_HEADER
>> 85 .dummy : { *(.dummy) } :text
>> 86
>> 87 _sdata = .; /* Start of data section */
>> 88 RODATA
>> 89
>> 90 /* writeable */
>> 91 .data : { /* Data */
>> 92 . = . + DATAOFFSET; /* for CONFIG_MAPPED_KERNEL */
>> 93
>> 94 INIT_TASK_DATA(THREAD_SIZE)
>> 95 NOSAVE_DATA
>> 96 CACHELINE_ALIGNED_DATA(1 << CONFIG_MIPS_L1_CACHE_SHIFT)
>> 97 READ_MOSTLY_DATA(1 << CONFIG_MIPS_L1_CACHE_SHIFT)
>> 98 DATA_DATA
>> 99 CONSTRUCTORS
>> 100 }
>> 101 BUG_TABLE
>> 102 _gp = . + 0x8000;
>> 103 .lit8 : {
>> 104 *(.lit8)
>> 105 }
>> 106 .lit4 : {
>> 107 *(.lit4)
>> 108 }
>> 109 /* We want the small data sections together, so single-instruction offsets
>> 110 can access them all, and initialized data all before uninitialized, so
>> 111 we can shorten the on-disk segment size. */
>> 112 .sdata : {
>> 113 *(.sdata)
>> 114 }
>> 115 _edata = .; /* End of data section */
78 116
79 #ifdef CONFIG_HAVE_DTCM !! 117 /* will be freed after init */
80 #define ITCM_SIZE CONFIG_ITCM_NR !! 118 . = ALIGN(PAGE_SIZE); /* Init code and data */
>> 119 __init_begin = .;
>> 120 INIT_TEXT_SECTION(PAGE_SIZE)
>> 121 INIT_DATA_SECTION(16)
81 122
82 .dtcm_start : { !! 123 . = ALIGN(4);
83 __dtcm_start = .; !! 124 .mips.machines.init : AT(ADDR(.mips.machines.init) - LOAD_OFFSET) {
>> 125 __mips_machines_start = .;
>> 126 *(.mips.machines.init)
>> 127 __mips_machines_end = .;
84 } 128 }
85 129
86 .data_tcm FIXADDR_TCM + ITCM_SIZE : AT !! 130 /* .exit.text is discarded at runtime, not link time, to deal with
87 { !! 131 * references from .rodata
88 . = ALIGN(4); !! 132 */
89 __stcm_data = .; !! 133 .exit.text : {
90 *(.tcm.data) !! 134 EXIT_TEXT
91 . = ALIGN(4); <<
92 __etcm_data = .; <<
93 } 135 }
>> 136 .exit.data : {
>> 137 EXIT_DATA
>> 138 }
>> 139 #ifdef CONFIG_SMP
>> 140 PERCPU_SECTION(1 << CONFIG_MIPS_L1_CACHE_SHIFT)
>> 141 #endif
94 142
95 . = ADDR(.dtcm_start) + SIZEOF(.data_t !! 143 #ifdef CONFIG_RELOCATABLE
>> 144 . = ALIGN(4);
96 145
97 .tcm_end : AT(ADDR(.dtcm_start) + SIZE !! 146 .data.reloc : {
98 #else !! 147 _relocation_start = .;
99 .tcm_end : AT(ADDR(.tcm_start) + SIZEO !! 148 /*
>> 149 * Space for relocation table
>> 150 * This needs to be filled so that the
>> 151 * relocs tool can overwrite the content.
>> 152 * An invalid value is left at the start of the
>> 153 * section to abort relocation if the table
>> 154 * has not been filled in.
>> 155 */
>> 156 LONG(0xFFFFFFFF);
>> 157 FILL(0);
>> 158 . += CONFIG_RELOCATION_TABLE_SIZE - 4;
>> 159 _relocation_end = .;
>> 160 }
100 #endif 161 #endif
101 . = ALIGN(PAGE_SIZE); !! 162
102 __tcm_end = .; !! 163 #ifdef CONFIG_MIPS_RAW_APPENDED_DTB
>> 164 __appended_dtb = .;
>> 165 /* leave space for appended DTB */
>> 166 . += 0x100000;
>> 167 #elif defined(CONFIG_MIPS_ELF_APPENDED_DTB)
>> 168 .appended_dtb : AT(ADDR(.appended_dtb) - LOAD_OFFSET) {
>> 169 *(.appended_dtb)
>> 170 KEEP(*(.appended_dtb))
103 } 171 }
104 #endif 172 #endif
>> 173 /*
>> 174 * Align to 64K in attempt to eliminate holes before the
>> 175 * .bss..swapper_pg_dir section at the start of .bss. This
>> 176 * also satisfies PAGE_SIZE alignment as the largest page size
>> 177 * allowed is 64K.
>> 178 */
>> 179 . = ALIGN(0x10000);
>> 180 __init_end = .;
>> 181 /* freed after init ends here */
>> 182
>> 183 /*
>> 184 * Force .bss to 64K alignment so that .bss..swapper_pg_dir
>> 185 * gets that alignment. .sbss should be empty, so there will be
>> 186 * no holes after __init_end. */
>> 187 BSS_SECTION(0, 0x10000, 8)
105 188
106 EXCEPTION_TABLE(L1_CACHE_BYTES) <<
107 BSS_SECTION(L1_CACHE_BYTES, PAGE_SIZE, <<
108 _end = . ; 189 _end = . ;
109 190
>> 191 /* These mark the ABI of the kernel for debuggers. */
>> 192 .mdebug.abi32 : {
>> 193 KEEP(*(.mdebug.abi32))
>> 194 }
>> 195 .mdebug.abi64 : {
>> 196 KEEP(*(.mdebug.abi64))
>> 197 }
>> 198
>> 199 /* This is the MIPS specific mdebug section. */
>> 200 .mdebug : {
>> 201 *(.mdebug)
>> 202 }
>> 203
110 STABS_DEBUG 204 STABS_DEBUG
111 DWARF_DEBUG 205 DWARF_DEBUG
112 ELF_DETAILS <<
113 206
>> 207 /* These must appear regardless of . */
>> 208 .gptab.sdata : {
>> 209 *(.gptab.data)
>> 210 *(.gptab.sdata)
>> 211 }
>> 212 .gptab.sbss : {
>> 213 *(.gptab.bss)
>> 214 *(.gptab.sbss)
>> 215 }
>> 216
>> 217 /* Sections to be discarded */
114 DISCARDS 218 DISCARDS
>> 219 /DISCARD/ : {
>> 220 /* ABI crap starts here */
>> 221 *(.MIPS.abiflags)
>> 222 *(.MIPS.options)
>> 223 *(.options)
>> 224 *(.pdr)
>> 225 *(.reginfo)
>> 226 *(.eh_frame)
>> 227 }
115 } 228 }
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