1 /* SPDX-License-Identifier: GPL-2.0 */ 1 /* SPDX-License-Identifier: GPL-2.0 */
>> 2 #include <asm/asm-offsets.h>
>> 3 #include <asm/thread_info.h>
2 4
3 #include <asm/vmlinux.lds.h> !! 5 #define PAGE_SIZE _PAGE_SIZE
4 #include <asm/page.h> <<
5 #include <asm/memory.h> <<
6 6
7 OUTPUT_ARCH(csky) !! 7 /*
8 ENTRY(_start) !! 8 * Put .bss..swapper_pg_dir as the first thing in .bss. This will
>> 9 * ensure that it has .bss alignment (64K).
>> 10 */
>> 11 #define BSS_FIRST_SECTIONS *(.bss..swapper_pg_dir)
>> 12
>> 13 /* Cavium Octeon should not have a separate PT_NOTE Program Header. */
>> 14 #ifndef CONFIG_CAVIUM_OCTEON_SOC
>> 15 #define EMITS_PT_NOTE
>> 16 #endif
>> 17
>> 18 #include <asm-generic/vmlinux.lds.h>
9 19
10 #ifndef __cskyBE__ !! 20 #undef mips
11 jiffies = jiffies_64; !! 21 #define mips mips
>> 22 OUTPUT_ARCH(mips)
>> 23 ENTRY(kernel_entry)
>> 24 PHDRS {
>> 25 text PT_LOAD FLAGS(7); /* RWX */
>> 26 #ifndef CONFIG_CAVIUM_OCTEON_SOC
>> 27 note PT_NOTE FLAGS(4); /* R__ */
>> 28 #endif /* CAVIUM_OCTEON_SOC */
>> 29 }
>> 30
>> 31 #ifdef CONFIG_32BIT
>> 32 #ifdef CONFIG_CPU_LITTLE_ENDIAN
>> 33 jiffies = jiffies_64;
>> 34 #else
>> 35 jiffies = jiffies_64 + 4;
>> 36 #endif
12 #else 37 #else
13 jiffies = jiffies_64 + 4; !! 38 jiffies = jiffies_64;
14 #endif 39 #endif
15 40
16 #define VBR_BASE \ <<
17 . = ALIGN(1024); \ <<
18 vec_base = .; \ <<
19 . += 512; <<
20 <<
21 SECTIONS 41 SECTIONS
22 { 42 {
23 . = PAGE_OFFSET + PHYS_OFFSET_OFFSET; !! 43 #ifdef CONFIG_BOOT_ELF64
>> 44 /* Read-only sections, merged into text segment: */
>> 45 /* . = 0xc000000000000000; */
>> 46
>> 47 /* This is the value for an Origin kernel, taken from an IRIX kernel. */
>> 48 /* . = 0xc00000000001c000; */
>> 49
>> 50 /* Set the vaddr for the text segment to a value
>> 51 * >= 0xa800 0000 0001 9000 if no symmon is going to configured
>> 52 * >= 0xa800 0000 0030 0000 otherwise
>> 53 */
24 54
25 _start = .; !! 55 /* . = 0xa800000000300000; */
26 HEAD_TEXT_SECTION !! 56 . = 0xffffffff80300000;
27 . = ALIGN(PAGE_SIZE); !! 57 #endif
28 !! 58 . = LINKER_LOAD_ADDRESS;
29 .text : AT(ADDR(.text) - LOAD_OFFSET) !! 59 /* read-only */
30 _text = .; !! 60 _text = .; /* Text and read-only data */
31 _stext = .; !! 61 .text : {
32 VBR_BASE <<
33 IRQENTRY_TEXT <<
34 SOFTIRQENTRY_TEXT <<
35 TEXT_TEXT 62 TEXT_TEXT
36 SCHED_TEXT 63 SCHED_TEXT
>> 64 CPUIDLE_TEXT
37 LOCK_TEXT 65 LOCK_TEXT
38 KPROBES_TEXT 66 KPROBES_TEXT
>> 67 IRQENTRY_TEXT
>> 68 SOFTIRQENTRY_TEXT
>> 69 *(.text.*)
39 *(.fixup) 70 *(.fixup)
40 *(.gnu.warning) 71 *(.gnu.warning)
41 } = 0 !! 72 } :text = 0
42 _etext = .; !! 73 _etext = .; /* End of text section */
43 74
44 /* __init_begin __init_end must be pag !! 75 EXCEPTION_TABLE(16)
45 . = ALIGN(PAGE_SIZE); <<
46 __init_begin = .; <<
47 INIT_TEXT_SECTION(PAGE_SIZE) <<
48 INIT_DATA_SECTION(PAGE_SIZE) <<
49 PERCPU_SECTION(L1_CACHE_BYTES) <<
50 . = ALIGN(PAGE_SIZE); <<
51 __init_end = .; <<
52 <<
53 _sdata = .; <<
54 RO_DATA(PAGE_SIZE) <<
55 RW_DATA(L1_CACHE_BYTES, PAGE_SIZE, THR <<
56 _edata = .; <<
57 76
58 #ifdef CONFIG_HAVE_TCM !! 77 /* Exception table for data bus errors */
59 .tcm_start : { !! 78 __dbe_table : {
60 . = ALIGN(PAGE_SIZE); !! 79 __start___dbe_table = .;
61 __tcm_start = .; !! 80 KEEP(*(__dbe_table))
>> 81 __stop___dbe_table = .;
62 } 82 }
63 83
64 .text_data_tcm FIXADDR_TCM : AT(__tcm_ !! 84 _sdata = .; /* Start of data section */
65 { !! 85 RO_DATA(4096)
66 . = ALIGN(4); !! 86
67 __stcm_text_data = .; !! 87 /* writeable */
68 *(.tcm.text) !! 88 .data : { /* Data */
69 *(.tcm.rodata) !! 89 . = . + DATAOFFSET; /* for CONFIG_MAPPED_KERNEL */
70 #ifndef CONFIG_HAVE_DTCM !! 90
71 *(.tcm.data) !! 91 INIT_TASK_DATA(THREAD_SIZE)
72 #endif !! 92 NOSAVE_DATA
73 . = ALIGN(4); !! 93 PAGE_ALIGNED_DATA(PAGE_SIZE)
74 __etcm_text_data = .; !! 94 CACHELINE_ALIGNED_DATA(1 << CONFIG_MIPS_L1_CACHE_SHIFT)
>> 95 READ_MOSTLY_DATA(1 << CONFIG_MIPS_L1_CACHE_SHIFT)
>> 96 DATA_DATA
>> 97 CONSTRUCTORS
>> 98 }
>> 99 BUG_TABLE
>> 100 _gp = . + 0x8000;
>> 101 .lit8 : {
>> 102 *(.lit8)
75 } 103 }
>> 104 .lit4 : {
>> 105 *(.lit4)
>> 106 }
>> 107 /* We want the small data sections together, so single-instruction offsets
>> 108 can access them all, and initialized data all before uninitialized, so
>> 109 we can shorten the on-disk segment size. */
>> 110 .sdata : {
>> 111 *(.sdata)
>> 112 }
>> 113 _edata = .; /* End of data section */
76 114
77 . = ADDR(.tcm_start) + SIZEOF(.tcm_sta !! 115 /* will be freed after init */
>> 116 . = ALIGN(PAGE_SIZE); /* Init code and data */
>> 117 __init_begin = .;
>> 118 INIT_TEXT_SECTION(PAGE_SIZE)
>> 119 INIT_DATA_SECTION(16)
78 120
79 #ifdef CONFIG_HAVE_DTCM !! 121 . = ALIGN(4);
80 #define ITCM_SIZE CONFIG_ITCM_NR !! 122 .mips.machines.init : AT(ADDR(.mips.machines.init) - LOAD_OFFSET) {
>> 123 __mips_machines_start = .;
>> 124 KEEP(*(.mips.machines.init))
>> 125 __mips_machines_end = .;
>> 126 }
81 127
82 .dtcm_start : { !! 128 /* .exit.text is discarded at runtime, not link time, to deal with
83 __dtcm_start = .; !! 129 * references from .rodata
>> 130 */
>> 131 .exit.text : {
>> 132 EXIT_TEXT
>> 133 }
>> 134 .exit.data : {
>> 135 EXIT_DATA
84 } 136 }
>> 137 #ifdef CONFIG_SMP
>> 138 PERCPU_SECTION(1 << CONFIG_MIPS_L1_CACHE_SHIFT)
>> 139 #endif
85 140
86 .data_tcm FIXADDR_TCM + ITCM_SIZE : AT !! 141 #ifdef CONFIG_MIPS_ELF_APPENDED_DTB
87 { !! 142 .appended_dtb : AT(ADDR(.appended_dtb) - LOAD_OFFSET) {
88 . = ALIGN(4); !! 143 *(.appended_dtb)
89 __stcm_data = .; !! 144 KEEP(*(.appended_dtb))
90 *(.tcm.data) <<
91 . = ALIGN(4); <<
92 __etcm_data = .; <<
93 } 145 }
>> 146 #endif
94 147
95 . = ADDR(.dtcm_start) + SIZEOF(.data_t !! 148 #ifdef CONFIG_RELOCATABLE
>> 149 . = ALIGN(4);
96 150
97 .tcm_end : AT(ADDR(.dtcm_start) + SIZE !! 151 .data.reloc : {
98 #else !! 152 _relocation_start = .;
99 .tcm_end : AT(ADDR(.tcm_start) + SIZEO !! 153 /*
100 #endif !! 154 * Space for relocation table
101 . = ALIGN(PAGE_SIZE); !! 155 * This needs to be filled so that the
102 __tcm_end = .; !! 156 * relocs tool can overwrite the content.
>> 157 * An invalid value is left at the start of the
>> 158 * section to abort relocation if the table
>> 159 * has not been filled in.
>> 160 */
>> 161 LONG(0xFFFFFFFF);
>> 162 FILL(0);
>> 163 . += CONFIG_RELOCATION_TABLE_SIZE - 4;
>> 164 _relocation_end = .;
103 } 165 }
104 #endif 166 #endif
105 167
106 EXCEPTION_TABLE(L1_CACHE_BYTES) !! 168 #ifdef CONFIG_MIPS_RAW_APPENDED_DTB
107 BSS_SECTION(L1_CACHE_BYTES, PAGE_SIZE, !! 169 __appended_dtb = .;
>> 170 /* leave space for appended DTB */
>> 171 . += 0x100000;
>> 172 #endif
>> 173 /*
>> 174 * Align to 64K in attempt to eliminate holes before the
>> 175 * .bss..swapper_pg_dir section at the start of .bss. This
>> 176 * also satisfies PAGE_SIZE alignment as the largest page size
>> 177 * allowed is 64K.
>> 178 */
>> 179 . = ALIGN(0x10000);
>> 180 __init_end = .;
>> 181 /* freed after init ends here */
>> 182
>> 183 /*
>> 184 * Force .bss to 64K alignment so that .bss..swapper_pg_dir
>> 185 * gets that alignment. .sbss should be empty, so there will be
>> 186 * no holes after __init_end. */
>> 187 BSS_SECTION(0, 0x10000, 8)
>> 188
108 _end = . ; 189 _end = . ;
109 190
>> 191 /* These mark the ABI of the kernel for debuggers. */
>> 192 .mdebug.abi32 : {
>> 193 KEEP(*(.mdebug.abi32))
>> 194 }
>> 195 .mdebug.abi64 : {
>> 196 KEEP(*(.mdebug.abi64))
>> 197 }
>> 198
>> 199 /* This is the MIPS specific mdebug section. */
>> 200 .mdebug : {
>> 201 *(.mdebug)
>> 202 }
>> 203
110 STABS_DEBUG 204 STABS_DEBUG
111 DWARF_DEBUG 205 DWARF_DEBUG
112 ELF_DETAILS 206 ELF_DETAILS
113 207
>> 208 /* These must appear regardless of . */
>> 209 .gptab.sdata : {
>> 210 *(.gptab.data)
>> 211 *(.gptab.sdata)
>> 212 }
>> 213 .gptab.sbss : {
>> 214 *(.gptab.bss)
>> 215 *(.gptab.sbss)
>> 216 }
>> 217
>> 218 /* Sections to be discarded */
114 DISCARDS 219 DISCARDS
>> 220 /DISCARD/ : {
>> 221 /* ABI crap starts here */
>> 222 *(.MIPS.abiflags)
>> 223 *(.MIPS.options)
>> 224 *(.options)
>> 225 *(.pdr)
>> 226 *(.reginfo)
>> 227 }
115 } 228 }
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