1 /* SPDX-License-Identifier: GPL-2.0 */ 1 /* SPDX-License-Identifier: GPL-2.0 */
>> 2 /* ld script for sparc32/sparc64 kernel */
>> 3
>> 4 #include <asm-generic/vmlinux.lds.h>
2 5
3 #include <asm/vmlinux.lds.h> <<
4 #include <asm/page.h> 6 #include <asm/page.h>
5 #include <asm/memory.h> !! 7 #include <asm/thread_info.h>
6 8
7 OUTPUT_ARCH(csky) !! 9 #ifdef CONFIG_SPARC32
8 ENTRY(_start) !! 10 #define INITIAL_ADDRESS 0x10000 + SIZEOF_HEADERS
>> 11 #define TEXTSTART 0xf0004000
>> 12
>> 13 #define SMP_CACHE_BYTES_SHIFT 5
9 14
10 #ifndef __cskyBE__ <<
11 jiffies = jiffies_64; <<
12 #else 15 #else
>> 16 #define SMP_CACHE_BYTES_SHIFT 6
>> 17 #define INITIAL_ADDRESS 0x4000
>> 18 #define TEXTSTART 0x0000000000404000
>> 19
>> 20 #endif
>> 21
>> 22 #define SMP_CACHE_BYTES (1 << SMP_CACHE_BYTES_SHIFT)
>> 23
>> 24 #ifdef CONFIG_SPARC32
>> 25 OUTPUT_FORMAT("elf32-sparc", "elf32-sparc", "elf32-sparc")
>> 26 OUTPUT_ARCH(sparc)
>> 27 ENTRY(_start)
13 jiffies = jiffies_64 + 4; 28 jiffies = jiffies_64 + 4;
>> 29 #else
>> 30 /* sparc64 */
>> 31 OUTPUT_FORMAT("elf64-sparc", "elf64-sparc", "elf64-sparc")
>> 32 OUTPUT_ARCH(sparc:v9a)
>> 33 ENTRY(_start)
>> 34 jiffies = jiffies_64;
14 #endif 35 #endif
15 36
16 #define VBR_BASE \ !! 37 #ifdef CONFIG_SPARC64
17 . = ALIGN(1024); \ !! 38 ASSERT((swapper_tsb == 0x0000000000408000), "Error: sparc64 early assembler too large")
18 vec_base = .; \ !! 39 #endif
19 . += 512; <<
20 40
21 SECTIONS 41 SECTIONS
22 { 42 {
23 . = PAGE_OFFSET + PHYS_OFFSET_OFFSET; !! 43 #ifdef CONFIG_SPARC64
24 !! 44 swapper_pg_dir = 0x0000000000402000;
25 _start = .; !! 45 #endif
26 HEAD_TEXT_SECTION !! 46 . = INITIAL_ADDRESS;
27 . = ALIGN(PAGE_SIZE); !! 47 .text TEXTSTART :
28 !! 48 {
29 .text : AT(ADDR(.text) - LOAD_OFFSET) <<
30 _text = .; 49 _text = .;
31 _stext = .; !! 50 HEAD_TEXT
32 VBR_BASE <<
33 IRQENTRY_TEXT <<
34 SOFTIRQENTRY_TEXT <<
35 TEXT_TEXT 51 TEXT_TEXT
36 SCHED_TEXT 52 SCHED_TEXT
37 LOCK_TEXT 53 LOCK_TEXT
38 KPROBES_TEXT 54 KPROBES_TEXT
39 *(.fixup) !! 55 IRQENTRY_TEXT
>> 56 SOFTIRQENTRY_TEXT
40 *(.gnu.warning) 57 *(.gnu.warning)
41 } = 0 58 } = 0
42 _etext = .; 59 _etext = .;
43 60
44 /* __init_begin __init_end must be pag !! 61 RO_DATA(PAGE_SIZE)
45 . = ALIGN(PAGE_SIZE); <<
46 __init_begin = .; <<
47 INIT_TEXT_SECTION(PAGE_SIZE) <<
48 INIT_DATA_SECTION(PAGE_SIZE) <<
49 PERCPU_SECTION(L1_CACHE_BYTES) <<
50 . = ALIGN(PAGE_SIZE); <<
51 __init_end = .; <<
52 62
>> 63 /* Start of data section */
53 _sdata = .; 64 _sdata = .;
54 RO_DATA(PAGE_SIZE) <<
55 RW_DATA(L1_CACHE_BYTES, PAGE_SIZE, THR <<
56 _edata = .; <<
57 65
58 #ifdef CONFIG_HAVE_TCM !! 66 .data1 : {
59 .tcm_start : { !! 67 *(.data1)
60 . = ALIGN(PAGE_SIZE); <<
61 __tcm_start = .; <<
62 } 68 }
>> 69 RW_DATA(SMP_CACHE_BYTES, 0, THREAD_SIZE)
63 70
64 .text_data_tcm FIXADDR_TCM : AT(__tcm_ !! 71 /* End of data section */
65 { !! 72 _edata = .;
66 . = ALIGN(4); !! 73
67 __stcm_text_data = .; !! 74 .fixup : {
68 *(.tcm.text) !! 75 __start___fixup = .;
69 *(.tcm.rodata) !! 76 *(.fixup)
70 #ifndef CONFIG_HAVE_DTCM !! 77 __stop___fixup = .;
71 *(.tcm.data) <<
72 #endif <<
73 . = ALIGN(4); <<
74 __etcm_text_data = .; <<
75 } 78 }
>> 79 EXCEPTION_TABLE(16)
76 80
77 . = ADDR(.tcm_start) + SIZEOF(.tcm_sta !! 81 . = ALIGN(PAGE_SIZE);
>> 82 __init_begin = ALIGN(PAGE_SIZE);
>> 83 INIT_TEXT_SECTION(PAGE_SIZE)
>> 84 __init_text_end = .;
>> 85 INIT_DATA_SECTION(16)
78 86
79 #ifdef CONFIG_HAVE_DTCM !! 87 . = ALIGN(4);
80 #define ITCM_SIZE CONFIG_ITCM_NR !! 88 .tsb_ldquad_phys_patch : {
>> 89 __tsb_ldquad_phys_patch = .;
>> 90 *(.tsb_ldquad_phys_patch)
>> 91 __tsb_ldquad_phys_patch_end = .;
>> 92 }
81 93
82 .dtcm_start : { !! 94 .tsb_phys_patch : {
83 __dtcm_start = .; !! 95 __tsb_phys_patch = .;
>> 96 *(.tsb_phys_patch)
>> 97 __tsb_phys_patch_end = .;
84 } 98 }
85 99
86 .data_tcm FIXADDR_TCM + ITCM_SIZE : AT !! 100 .cpuid_patch : {
87 { !! 101 __cpuid_patch = .;
88 . = ALIGN(4); !! 102 *(.cpuid_patch)
89 __stcm_data = .; !! 103 __cpuid_patch_end = .;
90 *(.tcm.data) !! 104 }
91 . = ALIGN(4); !! 105
92 __etcm_data = .; !! 106 .sun4v_1insn_patch : {
>> 107 __sun4v_1insn_patch = .;
>> 108 *(.sun4v_1insn_patch)
>> 109 __sun4v_1insn_patch_end = .;
>> 110 }
>> 111 .sun4v_2insn_patch : {
>> 112 __sun4v_2insn_patch = .;
>> 113 *(.sun4v_2insn_patch)
>> 114 __sun4v_2insn_patch_end = .;
>> 115 }
>> 116 .leon_1insn_patch : {
>> 117 __leon_1insn_patch = .;
>> 118 *(.leon_1insn_patch)
>> 119 __leon_1insn_patch_end = .;
>> 120 }
>> 121 .swapper_tsb_phys_patch : {
>> 122 __swapper_tsb_phys_patch = .;
>> 123 *(.swapper_tsb_phys_patch)
>> 124 __swapper_tsb_phys_patch_end = .;
>> 125 }
>> 126 .swapper_4m_tsb_phys_patch : {
>> 127 __swapper_4m_tsb_phys_patch = .;
>> 128 *(.swapper_4m_tsb_phys_patch)
>> 129 __swapper_4m_tsb_phys_patch_end = .;
93 } 130 }
>> 131 .popc_3insn_patch : {
>> 132 __popc_3insn_patch = .;
>> 133 *(.popc_3insn_patch)
>> 134 __popc_3insn_patch_end = .;
>> 135 }
>> 136 .popc_6insn_patch : {
>> 137 __popc_6insn_patch = .;
>> 138 *(.popc_6insn_patch)
>> 139 __popc_6insn_patch_end = .;
>> 140 }
>> 141 .pause_3insn_patch : {
>> 142 __pause_3insn_patch = .;
>> 143 *(.pause_3insn_patch)
>> 144 __pause_3insn_patch_end = .;
>> 145 }
>> 146 .sun_m7_1insn_patch : {
>> 147 __sun_m7_1insn_patch = .;
>> 148 *(.sun_m7_1insn_patch)
>> 149 __sun_m7_1insn_patch_end = .;
>> 150 }
>> 151 .sun_m7_2insn_patch : {
>> 152 __sun_m7_2insn_patch = .;
>> 153 *(.sun_m7_2insn_patch)
>> 154 __sun_m7_2insn_patch_end = .;
>> 155 }
>> 156 .get_tick_patch : {
>> 157 __get_tick_patch = .;
>> 158 *(.get_tick_patch)
>> 159 __get_tick_patch_end = .;
>> 160 }
>> 161 .pud_huge_patch : {
>> 162 __pud_huge_patch = .;
>> 163 *(.pud_huge_patch)
>> 164 __pud_huge_patch_end = .;
>> 165 }
>> 166 .fast_win_ctrl_1insn_patch : {
>> 167 __fast_win_ctrl_1insn_patch = .;
>> 168 *(.fast_win_ctrl_1insn_patch)
>> 169 __fast_win_ctrl_1insn_patch_end = .;
>> 170 }
>> 171 PERCPU_SECTION(SMP_CACHE_BYTES)
94 172
95 . = ADDR(.dtcm_start) + SIZEOF(.data_t !! 173 . = ALIGN(PAGE_SIZE);
>> 174 .exit.text : {
>> 175 EXIT_TEXT
>> 176 }
96 177
97 .tcm_end : AT(ADDR(.dtcm_start) + SIZE !! 178 .exit.data : {
98 #else !! 179 EXIT_DATA
99 .tcm_end : AT(ADDR(.tcm_start) + SIZEO <<
100 #endif <<
101 . = ALIGN(PAGE_SIZE); <<
102 __tcm_end = .; <<
103 } 180 }
104 #endif <<
105 181
106 EXCEPTION_TABLE(L1_CACHE_BYTES) !! 182 . = ALIGN(PAGE_SIZE);
107 BSS_SECTION(L1_CACHE_BYTES, PAGE_SIZE, !! 183 __init_end = .;
>> 184 BSS_SECTION(0, 0, 0)
108 _end = . ; 185 _end = . ;
109 186
110 STABS_DEBUG 187 STABS_DEBUG
111 DWARF_DEBUG 188 DWARF_DEBUG
112 ELF_DETAILS 189 ELF_DETAILS
113 190
114 DISCARDS 191 DISCARDS
115 } 192 }
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